1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "dis-asm.h"
26 #include "libiberty.h"
27 #include "opcode/mips.h"
28 #include "opintl.h"
29
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
34
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
37 #include "elf-bfd.h"
38 #include "elf/mips.h"
39 #endif
40
41 /* Mips instructions are at maximum this many bytes long. */
42 #define INSNLEN 4
43
44
45 /* FIXME: These should be shared with gdb somehow. */
46
47 struct mips_cp0sel_name
48 {
49 unsigned int cp0reg;
50 unsigned int sel;
51 const char * const name;
52 };
53
54 /* The mips16 register names. */
55 static const char * const mips16_reg_names[] =
56 {
57 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
58 };
59
60 static const char * const mips_gpr_names_numeric[32] =
61 {
62 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
63 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
64 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
65 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
66 };
67
68 static const char * const mips_gpr_names_oldabi[32] =
69 {
70 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
71 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
72 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
73 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
74 };
75
76 static const char * const mips_gpr_names_newabi[32] =
77 {
78 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
79 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
80 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
81 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
82 };
83
84 static const char * const mips_fpr_names_numeric[32] =
85 {
86 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
87 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
88 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
89 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
90 };
91
92 static const char * const mips_fpr_names_32[32] =
93 {
94 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
95 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
96 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
97 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
98 };
99
100 static const char * const mips_fpr_names_n32[32] =
101 {
102 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
103 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
104 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
105 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
106 };
107
108 static const char * const mips_fpr_names_64[32] =
109 {
110 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
111 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
112 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
113 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
114 };
115
116 static const char * const mips_cp0_names_numeric[32] =
117 {
118 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
119 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
120 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
121 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
122 };
123
124 static const char * const mips_cp0_names_mips3264[32] =
125 {
126 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
127 "c0_context", "c0_pagemask", "c0_wired", "$7",
128 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
129 "c0_status", "c0_cause", "c0_epc", "c0_prid",
130 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
131 "c0_xcontext", "$21", "$22", "c0_debug",
132 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
133 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
134 };
135
136 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
137 {
138 { 16, 1, "c0_config1" },
139 { 16, 2, "c0_config2" },
140 { 16, 3, "c0_config3" },
141 { 18, 1, "c0_watchlo,1" },
142 { 18, 2, "c0_watchlo,2" },
143 { 18, 3, "c0_watchlo,3" },
144 { 18, 4, "c0_watchlo,4" },
145 { 18, 5, "c0_watchlo,5" },
146 { 18, 6, "c0_watchlo,6" },
147 { 18, 7, "c0_watchlo,7" },
148 { 19, 1, "c0_watchhi,1" },
149 { 19, 2, "c0_watchhi,2" },
150 { 19, 3, "c0_watchhi,3" },
151 { 19, 4, "c0_watchhi,4" },
152 { 19, 5, "c0_watchhi,5" },
153 { 19, 6, "c0_watchhi,6" },
154 { 19, 7, "c0_watchhi,7" },
155 { 25, 1, "c0_perfcnt,1" },
156 { 25, 2, "c0_perfcnt,2" },
157 { 25, 3, "c0_perfcnt,3" },
158 { 25, 4, "c0_perfcnt,4" },
159 { 25, 5, "c0_perfcnt,5" },
160 { 25, 6, "c0_perfcnt,6" },
161 { 25, 7, "c0_perfcnt,7" },
162 { 27, 1, "c0_cacheerr,1" },
163 { 27, 2, "c0_cacheerr,2" },
164 { 27, 3, "c0_cacheerr,3" },
165 { 28, 1, "c0_datalo" },
166 { 29, 1, "c0_datahi" }
167 };
168
169 static const char * const mips_cp0_names_mips3264r2[32] =
170 {
171 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
172 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
173 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
174 "c0_status", "c0_cause", "c0_epc", "c0_prid",
175 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
176 "c0_xcontext", "$21", "$22", "c0_debug",
177 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
178 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
179 };
180
181 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
182 {
183 { 4, 1, "c0_contextconfig" },
184 { 5, 1, "c0_pagegrain" },
185 { 12, 1, "c0_intctl" },
186 { 12, 2, "c0_srsctl" },
187 { 12, 3, "c0_srsmap" },
188 { 15, 1, "c0_ebase" },
189 { 16, 1, "c0_config1" },
190 { 16, 2, "c0_config2" },
191 { 16, 3, "c0_config3" },
192 { 18, 1, "c0_watchlo,1" },
193 { 18, 2, "c0_watchlo,2" },
194 { 18, 3, "c0_watchlo,3" },
195 { 18, 4, "c0_watchlo,4" },
196 { 18, 5, "c0_watchlo,5" },
197 { 18, 6, "c0_watchlo,6" },
198 { 18, 7, "c0_watchlo,7" },
199 { 19, 1, "c0_watchhi,1" },
200 { 19, 2, "c0_watchhi,2" },
201 { 19, 3, "c0_watchhi,3" },
202 { 19, 4, "c0_watchhi,4" },
203 { 19, 5, "c0_watchhi,5" },
204 { 19, 6, "c0_watchhi,6" },
205 { 19, 7, "c0_watchhi,7" },
206 { 23, 1, "c0_tracecontrol" },
207 { 23, 2, "c0_tracecontrol2" },
208 { 23, 3, "c0_usertracedata" },
209 { 23, 4, "c0_tracebpc" },
210 { 25, 1, "c0_perfcnt,1" },
211 { 25, 2, "c0_perfcnt,2" },
212 { 25, 3, "c0_perfcnt,3" },
213 { 25, 4, "c0_perfcnt,4" },
214 { 25, 5, "c0_perfcnt,5" },
215 { 25, 6, "c0_perfcnt,6" },
216 { 25, 7, "c0_perfcnt,7" },
217 { 27, 1, "c0_cacheerr,1" },
218 { 27, 2, "c0_cacheerr,2" },
219 { 27, 3, "c0_cacheerr,3" },
220 { 28, 1, "c0_datalo" },
221 { 28, 2, "c0_taglo1" },
222 { 28, 3, "c0_datalo1" },
223 { 28, 4, "c0_taglo2" },
224 { 28, 5, "c0_datalo2" },
225 { 28, 6, "c0_taglo3" },
226 { 28, 7, "c0_datalo3" },
227 { 29, 1, "c0_datahi" },
228 { 29, 2, "c0_taghi1" },
229 { 29, 3, "c0_datahi1" },
230 { 29, 4, "c0_taghi2" },
231 { 29, 5, "c0_datahi2" },
232 { 29, 6, "c0_taghi3" },
233 { 29, 7, "c0_datahi3" },
234 };
235
236 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
237 static const char * const mips_cp0_names_sb1[32] =
238 {
239 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
240 "c0_context", "c0_pagemask", "c0_wired", "$7",
241 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
242 "c0_status", "c0_cause", "c0_epc", "c0_prid",
243 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
244 "c0_xcontext", "$21", "$22", "c0_debug",
245 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
246 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
247 };
248
249 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
250 {
251 { 16, 1, "c0_config1" },
252 { 18, 1, "c0_watchlo,1" },
253 { 19, 1, "c0_watchhi,1" },
254 { 22, 0, "c0_perftrace" },
255 { 23, 3, "c0_edebug" },
256 { 25, 1, "c0_perfcnt,1" },
257 { 25, 2, "c0_perfcnt,2" },
258 { 25, 3, "c0_perfcnt,3" },
259 { 25, 4, "c0_perfcnt,4" },
260 { 25, 5, "c0_perfcnt,5" },
261 { 25, 6, "c0_perfcnt,6" },
262 { 25, 7, "c0_perfcnt,7" },
263 { 26, 1, "c0_buserr_pa" },
264 { 27, 1, "c0_cacheerr_d" },
265 { 27, 3, "c0_cacheerr_d_pa" },
266 { 28, 1, "c0_datalo_i" },
267 { 28, 2, "c0_taglo_d" },
268 { 28, 3, "c0_datalo_d" },
269 { 29, 1, "c0_datahi_i" },
270 { 29, 2, "c0_taghi_d" },
271 { 29, 3, "c0_datahi_d" },
272 };
273
274 static const char * const mips_hwr_names_numeric[32] =
275 {
276 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
277 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
278 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
279 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
280 };
281
282 static const char * const mips_hwr_names_mips3264r2[32] =
283 {
284 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
285 "$4", "$5", "$6", "$7",
286 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
287 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
288 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
289 };
290
291 struct mips_abi_choice
292 {
293 const char * name;
294 const char * const *gpr_names;
295 const char * const *fpr_names;
296 };
297
298 struct mips_abi_choice mips_abi_choices[] =
299 {
300 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
301 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
302 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
303 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
304 };
305
306 struct mips_arch_choice
307 {
308 const char *name;
309 int bfd_mach_valid;
310 unsigned long bfd_mach;
311 int processor;
312 int isa;
313 const char * const *cp0_names;
314 const struct mips_cp0sel_name *cp0sel_names;
315 unsigned int cp0sel_names_len;
316 const char * const *hwr_names;
317 };
318
319 const struct mips_arch_choice mips_arch_choices[] =
320 {
321 { "numeric", 0, 0, 0, 0,
322 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
323
324 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
325 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
326 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
327 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
328 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
329 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
330 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
331 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
332 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
333 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
334 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
335 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
336 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
337 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
338 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
339 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
340 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
341 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
342 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
343 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
344 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
345 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
346 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
347 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
348 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
349 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
350 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
351 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
352 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
354 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
356 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
360 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
363 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
364 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
365 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
366
367 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
368 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
369 _MIPS32 Architecture For Programmers Volume I: Introduction to the
370 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
371 page 1. */
372 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
373 ISA_MIPS32 | INSN_MIPS16 | INSN_DSP,
374 mips_cp0_names_mips3264,
375 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
376 mips_hwr_names_numeric },
377
378 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
379 ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
380 mips_cp0_names_mips3264r2,
381 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
382 mips_hwr_names_mips3264r2 },
383
384 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
385 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
386 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
387 mips_cp0_names_mips3264,
388 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
389 mips_hwr_names_numeric },
390
391 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
392 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
393 mips_cp0_names_mips3264r2,
394 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
395 mips_hwr_names_mips3264r2 },
396
397 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
398 ISA_MIPS64R2 | INSN_OCTEON,
399 mips_cp0_names_mips3264r2,
400 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
401 mips_hwr_names_mips3264r2 },
402
403 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
404 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
405 mips_cp0_names_sb1,
406 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
407 mips_hwr_names_numeric },
408
409 /* This entry, mips16, is here only for ISA/processor selection; do
410 not print its name. */
411 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
412 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
413 };
414
415 /* ISA and processor type to disassemble for, and register names to use.
416 set_default_mips_dis_options and parse_mips_dis_options fill in these
417 values. */
418 static int mips_processor;
419 static int mips_isa;
420 static const char * const *mips_gpr_names;
421 static const char * const *mips_fpr_names;
422 static const char * const *mips_cp0_names;
423 static const struct mips_cp0sel_name *mips_cp0sel_names;
424 static int mips_cp0sel_names_len;
425 static const char * const *mips_hwr_names;
426
427 /* Other options */
428 static int no_aliases; /* If set disassemble as most general inst. */
429
430 static const struct mips_abi_choice *
choose_abi_by_name(const char * name,unsigned int namelen)431 choose_abi_by_name (const char *name, unsigned int namelen)
432 {
433 const struct mips_abi_choice *c;
434 unsigned int i;
435
436 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
437 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
438 && strlen (mips_abi_choices[i].name) == namelen)
439 c = &mips_abi_choices[i];
440
441 return c;
442 }
443
444 static const struct mips_arch_choice *
choose_arch_by_name(const char * name,unsigned int namelen)445 choose_arch_by_name (const char *name, unsigned int namelen)
446 {
447 const struct mips_arch_choice *c = NULL;
448 unsigned int i;
449
450 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
451 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
452 && strlen (mips_arch_choices[i].name) == namelen)
453 c = &mips_arch_choices[i];
454
455 return c;
456 }
457
458 static const struct mips_arch_choice *
choose_arch_by_number(unsigned long mach)459 choose_arch_by_number (unsigned long mach)
460 {
461 static unsigned long hint_bfd_mach;
462 static const struct mips_arch_choice *hint_arch_choice;
463 const struct mips_arch_choice *c;
464 unsigned int i;
465
466 /* We optimize this because even if the user specifies no
467 flags, this will be done for every instruction! */
468 if (hint_bfd_mach == mach
469 && hint_arch_choice != NULL
470 && hint_arch_choice->bfd_mach == hint_bfd_mach)
471 return hint_arch_choice;
472
473 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
474 {
475 if (mips_arch_choices[i].bfd_mach_valid
476 && mips_arch_choices[i].bfd_mach == mach)
477 {
478 c = &mips_arch_choices[i];
479 hint_bfd_mach = mach;
480 hint_arch_choice = c;
481 }
482 }
483 return c;
484 }
485
486 /* Check if the object uses NewABI conventions. */
487
488 static int
is_newabi(Elf_Internal_Ehdr * header)489 is_newabi (Elf_Internal_Ehdr *header)
490 {
491 /* There are no old-style ABIs which use 64-bit ELF. */
492 if (header->e_ident[EI_CLASS] == ELFCLASS64)
493 return 1;
494
495 /* If a 32-bit ELF file, n32 is a new-style ABI. */
496 if ((header->e_flags & EF_MIPS_ABI2) != 0)
497 return 1;
498
499 return 0;
500 }
501
502 static void
set_default_mips_dis_options(struct disassemble_info * info)503 set_default_mips_dis_options (struct disassemble_info *info)
504 {
505 const struct mips_arch_choice *chosen_arch;
506
507 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
508 and numeric FPR, CP0 register, and HWR names. */
509 mips_isa = ISA_MIPS3;
510 mips_processor = CPU_R3000;
511 mips_gpr_names = mips_gpr_names_oldabi;
512 mips_fpr_names = mips_fpr_names_numeric;
513 mips_cp0_names = mips_cp0_names_numeric;
514 mips_cp0sel_names = NULL;
515 mips_cp0sel_names_len = 0;
516 mips_hwr_names = mips_hwr_names_numeric;
517 no_aliases = 0;
518
519 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
520 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
521 {
522 Elf_Internal_Ehdr *header;
523
524 header = elf_elfheader (info->section->owner);
525 if (is_newabi (header))
526 mips_gpr_names = mips_gpr_names_newabi;
527 }
528
529 /* Set ISA, architecture, and cp0 register names as best we can. */
530 #if ! SYMTAB_AVAILABLE
531 /* This is running out on a target machine, not in a host tool.
532 FIXME: Where does mips_target_info come from? */
533 target_processor = mips_target_info.processor;
534 mips_isa = mips_target_info.isa;
535 #else
536 chosen_arch = choose_arch_by_number (info->mach);
537 if (chosen_arch != NULL)
538 {
539 mips_processor = chosen_arch->processor;
540 mips_isa = chosen_arch->isa;
541 mips_cp0_names = chosen_arch->cp0_names;
542 mips_cp0sel_names = chosen_arch->cp0sel_names;
543 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
544 mips_hwr_names = chosen_arch->hwr_names;
545 }
546 #endif
547 }
548
549 static void
parse_mips_dis_option(const char * option,unsigned int len)550 parse_mips_dis_option (const char *option, unsigned int len)
551 {
552 unsigned int i, optionlen, vallen;
553 const char *val;
554 const struct mips_abi_choice *chosen_abi;
555 const struct mips_arch_choice *chosen_arch;
556
557 /* Try to match options that are simple flags */
558 if (strncmp (option, "no-aliases", 10) == 0)
559 {
560 no_aliases = 1;
561 return;
562 }
563
564 /* Look for the = that delimits the end of the option name. */
565 for (i = 0; i < len; i++)
566 if (option[i] == '=')
567 break;
568
569 if (i == 0) /* Invalid option: no name before '='. */
570 return;
571 if (i == len) /* Invalid option: no '='. */
572 return;
573 if (i == (len - 1)) /* Invalid option: no value after '='. */
574 return;
575
576 optionlen = i;
577 val = option + (optionlen + 1);
578 vallen = len - (optionlen + 1);
579
580 if (strncmp ("gpr-names", option, optionlen) == 0
581 && strlen ("gpr-names") == optionlen)
582 {
583 chosen_abi = choose_abi_by_name (val, vallen);
584 if (chosen_abi != NULL)
585 mips_gpr_names = chosen_abi->gpr_names;
586 return;
587 }
588
589 if (strncmp ("fpr-names", option, optionlen) == 0
590 && strlen ("fpr-names") == optionlen)
591 {
592 chosen_abi = choose_abi_by_name (val, vallen);
593 if (chosen_abi != NULL)
594 mips_fpr_names = chosen_abi->fpr_names;
595 return;
596 }
597
598 if (strncmp ("cp0-names", option, optionlen) == 0
599 && strlen ("cp0-names") == optionlen)
600 {
601 chosen_arch = choose_arch_by_name (val, vallen);
602 if (chosen_arch != NULL)
603 {
604 mips_cp0_names = chosen_arch->cp0_names;
605 mips_cp0sel_names = chosen_arch->cp0sel_names;
606 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
607 }
608 return;
609 }
610
611 if (strncmp ("hwr-names", option, optionlen) == 0
612 && strlen ("hwr-names") == optionlen)
613 {
614 chosen_arch = choose_arch_by_name (val, vallen);
615 if (chosen_arch != NULL)
616 mips_hwr_names = chosen_arch->hwr_names;
617 return;
618 }
619
620 if (strncmp ("reg-names", option, optionlen) == 0
621 && strlen ("reg-names") == optionlen)
622 {
623 /* We check both ABI and ARCH here unconditionally, so
624 that "numeric" will do the desirable thing: select
625 numeric register names for all registers. Other than
626 that, a given name probably won't match both. */
627 chosen_abi = choose_abi_by_name (val, vallen);
628 if (chosen_abi != NULL)
629 {
630 mips_gpr_names = chosen_abi->gpr_names;
631 mips_fpr_names = chosen_abi->fpr_names;
632 }
633 chosen_arch = choose_arch_by_name (val, vallen);
634 if (chosen_arch != NULL)
635 {
636 mips_cp0_names = chosen_arch->cp0_names;
637 mips_cp0sel_names = chosen_arch->cp0sel_names;
638 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
639 mips_hwr_names = chosen_arch->hwr_names;
640 }
641 return;
642 }
643
644 /* Invalid option. */
645 }
646
647 static void
parse_mips_dis_options(const char * options)648 parse_mips_dis_options (const char *options)
649 {
650 const char *option_end;
651
652 if (options == NULL)
653 return;
654
655 while (*options != '\0')
656 {
657 /* Skip empty options. */
658 if (*options == ',')
659 {
660 options++;
661 continue;
662 }
663
664 /* We know that *options is neither NUL or a comma. */
665 option_end = options + 1;
666 while (*option_end != ',' && *option_end != '\0')
667 option_end++;
668
669 parse_mips_dis_option (options, option_end - options);
670
671 /* Go on to the next one. If option_end points to a comma, it
672 will be skipped above. */
673 options = option_end;
674 }
675 }
676
677 static const struct mips_cp0sel_name *
lookup_mips_cp0sel_name(const struct mips_cp0sel_name * names,unsigned int len,unsigned int cp0reg,unsigned int sel)678 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
679 unsigned int len,
680 unsigned int cp0reg,
681 unsigned int sel)
682 {
683 unsigned int i;
684
685 for (i = 0; i < len; i++)
686 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
687 return &names[i];
688 return NULL;
689 }
690
691 /* Print insn arguments for 32/64-bit code. */
692
693 static void
print_insn_args(const char * d,register unsigned long int l,bfd_vma pc,struct disassemble_info * info)694 print_insn_args (const char *d,
695 register unsigned long int l,
696 bfd_vma pc,
697 struct disassemble_info *info)
698 {
699 int op, delta;
700 unsigned int lsb, msb, msbd;
701
702 lsb = 0;
703
704 for (; *d != '\0'; d++)
705 {
706 switch (*d)
707 {
708 case ',':
709 case '(':
710 case ')':
711 case '[':
712 case ']':
713 (*info->fprintf_func) (info->stream, "%c", *d);
714 break;
715
716 case '+':
717 /* Extension character; switch for second char. */
718 d++;
719 switch (*d)
720 {
721 case '\0':
722 /* xgettext:c-format */
723 (*info->fprintf_func) (info->stream,
724 _("# internal error, incomplete extension sequence (+)"));
725 return;
726
727 case 'A':
728 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
729 (*info->fprintf_func) (info->stream, "0x%x", lsb);
730 break;
731
732 case 'B':
733 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
734 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
735 break;
736
737 case 'C':
738 case 'H':
739 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
740 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
741 break;
742
743 case 'D':
744 {
745 const struct mips_cp0sel_name *n;
746 unsigned int cp0reg, sel;
747
748 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
749 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
750
751 /* CP0 register including 'sel' code for mtcN (et al.), to be
752 printed textually if known. If not known, print both
753 CP0 register name and sel numerically since CP0 register
754 with sel 0 may have a name unrelated to register being
755 printed. */
756 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
757 mips_cp0sel_names_len, cp0reg, sel);
758 if (n != NULL)
759 (*info->fprintf_func) (info->stream, "%s", n->name);
760 else
761 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
762 break;
763 }
764
765 case 'E':
766 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
767 (*info->fprintf_func) (info->stream, "0x%x", lsb);
768 break;
769
770 case 'F':
771 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
772 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
773 break;
774
775 case 'G':
776 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
777 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
778 break;
779
780 case 't': /* Coprocessor 0 reg name */
781 (*info->fprintf_func) (info->stream, "%s",
782 mips_cp0_names[(l >> OP_SH_RT) &
783 OP_MASK_RT]);
784 break;
785
786 case 'T': /* Coprocessor 0 reg name */
787 {
788 const struct mips_cp0sel_name *n;
789 unsigned int cp0reg, sel;
790
791 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
792 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
793
794 /* CP0 register including 'sel' code for mftc0, to be
795 printed textually if known. If not known, print both
796 CP0 register name and sel numerically since CP0 register
797 with sel 0 may have a name unrelated to register being
798 printed. */
799 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
800 mips_cp0sel_names_len, cp0reg, sel);
801 if (n != NULL)
802 (*info->fprintf_func) (info->stream, "%s", n->name);
803 else
804 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
805 break;
806 }
807
808 default:
809 /* xgettext:c-format */
810 (*info->fprintf_func) (info->stream,
811 _("# internal error, undefined extension sequence (+%c)"),
812 *d);
813 return;
814 }
815 break;
816
817 case '3':
818 (*info->fprintf_func) (info->stream, "0x%lx",
819 (l >> OP_SH_SA3) & OP_MASK_SA3);
820 break;
821
822 case '4':
823 (*info->fprintf_func) (info->stream, "0x%lx",
824 (l >> OP_SH_SA4) & OP_MASK_SA4);
825 break;
826
827 case '5':
828 (*info->fprintf_func) (info->stream, "0x%lx",
829 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
830 break;
831
832 case '6':
833 (*info->fprintf_func) (info->stream, "0x%lx",
834 (l >> OP_SH_RS) & OP_MASK_RS);
835 break;
836
837 case '7':
838 (*info->fprintf_func) (info->stream, "$ac%ld",
839 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
840 break;
841
842 case '8':
843 (*info->fprintf_func) (info->stream, "0x%lx",
844 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
845 break;
846
847 case '9':
848 (*info->fprintf_func) (info->stream, "$ac%ld",
849 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
850 break;
851
852 case '0': /* dsp 6-bit signed immediate in bit 20 */
853 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
854 if (delta & 0x20) /* test sign bit */
855 delta |= ~OP_MASK_DSPSFT;
856 (*info->fprintf_func) (info->stream, "%d", delta);
857 break;
858
859 case ':': /* dsp 7-bit signed immediate in bit 19 */
860 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
861 if (delta & 0x40) /* test sign bit */
862 delta |= ~OP_MASK_DSPSFT_7;
863 (*info->fprintf_func) (info->stream, "%d", delta);
864 break;
865
866 case '\'':
867 (*info->fprintf_func) (info->stream, "0x%lx",
868 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
869 break;
870
871 case '@': /* dsp 10-bit signed immediate in bit 16 */
872 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
873 if (delta & 0x200) /* test sign bit */
874 delta |= ~OP_MASK_IMM10;
875 (*info->fprintf_func) (info->stream, "%d", delta);
876 break;
877
878 case '!':
879 (*info->fprintf_func) (info->stream, "%ld",
880 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
881 break;
882
883 case '$':
884 (*info->fprintf_func) (info->stream, "%ld",
885 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
886 break;
887
888 case '*':
889 (*info->fprintf_func) (info->stream, "$ac%ld",
890 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
891 break;
892
893 case '&':
894 (*info->fprintf_func) (info->stream, "$ac%ld",
895 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
896 break;
897
898 case 'g':
899 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
900 (*info->fprintf_func) (info->stream, "$%ld",
901 (l >> OP_SH_RD) & OP_MASK_RD);
902 break;
903
904 case 's':
905 case 'b':
906 case 'r':
907 case 'v':
908 (*info->fprintf_func) (info->stream, "%s",
909 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
910 break;
911
912 case 't':
913 case 'w':
914 (*info->fprintf_func) (info->stream, "%s",
915 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
916 break;
917
918 case 'i':
919 case 'u':
920 (*info->fprintf_func) (info->stream, "0x%lx",
921 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
922 break;
923
924 case 'j': /* Same as i, but sign-extended. */
925 case 'o':
926 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
927 if (delta & 0x8000)
928 delta |= ~0xffff;
929 (*info->fprintf_func) (info->stream, "%d",
930 delta);
931 break;
932
933 case 'h':
934 (*info->fprintf_func) (info->stream, "0x%x",
935 (unsigned int) ((l >> OP_SH_PREFX)
936 & OP_MASK_PREFX));
937 break;
938
939 case 'k':
940 (*info->fprintf_func) (info->stream, "0x%x",
941 (unsigned int) ((l >> OP_SH_CACHE)
942 & OP_MASK_CACHE));
943 break;
944
945 case 'a':
946 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
947 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
948 (*info->print_address_func) (info->target, info);
949 break;
950
951 case 'p':
952 /* Sign extend the displacement. */
953 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
954 if (delta & 0x8000)
955 delta |= ~0xffff;
956 info->target = (delta << 2) + pc + INSNLEN;
957 (*info->print_address_func) (info->target, info);
958 break;
959
960 case 'd':
961 (*info->fprintf_func) (info->stream, "%s",
962 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
963 break;
964
965 case 'U':
966 {
967 /* First check for both rd and rt being equal. */
968 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
969 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
970 (*info->fprintf_func) (info->stream, "%s",
971 mips_gpr_names[reg]);
972 else
973 {
974 /* If one is zero use the other. */
975 if (reg == 0)
976 (*info->fprintf_func) (info->stream, "%s",
977 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
978 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
979 (*info->fprintf_func) (info->stream, "%s",
980 mips_gpr_names[reg]);
981 else /* Bogus, result depends on processor. */
982 (*info->fprintf_func) (info->stream, "%s or %s",
983 mips_gpr_names[reg],
984 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
985 }
986 }
987 break;
988
989 case 'z':
990 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
991 break;
992
993 case '<':
994 (*info->fprintf_func) (info->stream, "0x%lx",
995 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
996 break;
997
998 case 'c':
999 (*info->fprintf_func) (info->stream, "0x%lx",
1000 (l >> OP_SH_CODE) & OP_MASK_CODE);
1001 break;
1002
1003 case 'q':
1004 (*info->fprintf_func) (info->stream, "0x%lx",
1005 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1006 break;
1007
1008 case 'C':
1009 (*info->fprintf_func) (info->stream, "0x%lx",
1010 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1011 break;
1012
1013 case 'B':
1014 (*info->fprintf_func) (info->stream, "0x%lx",
1015
1016 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1017 break;
1018
1019 case 'J':
1020 (*info->fprintf_func) (info->stream, "0x%lx",
1021 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1022 break;
1023
1024 case 'S':
1025 case 'V':
1026 (*info->fprintf_func) (info->stream, "%s",
1027 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1028 break;
1029
1030 case 'T':
1031 case 'W':
1032 (*info->fprintf_func) (info->stream, "%s",
1033 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1034 break;
1035
1036 case 'D':
1037 (*info->fprintf_func) (info->stream, "%s",
1038 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1039 break;
1040
1041 case 'R':
1042 (*info->fprintf_func) (info->stream, "%s",
1043 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1044 break;
1045
1046 case 'E':
1047 /* Coprocessor register for lwcN instructions, et al.
1048
1049 Note that there is no load/store cp0 instructions, and
1050 that FPU (cp1) instructions disassemble this field using
1051 'T' format. Therefore, until we gain understanding of
1052 cp2 register names, we can simply print the register
1053 numbers. */
1054 (*info->fprintf_func) (info->stream, "$%ld",
1055 (l >> OP_SH_RT) & OP_MASK_RT);
1056 break;
1057
1058 case 'G':
1059 /* Coprocessor register for mtcN instructions, et al. Note
1060 that FPU (cp1) instructions disassemble this field using
1061 'S' format. Therefore, we only need to worry about cp0,
1062 cp2, and cp3. */
1063 op = (l >> OP_SH_OP) & OP_MASK_OP;
1064 if (op == OP_OP_COP0)
1065 (*info->fprintf_func) (info->stream, "%s",
1066 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1067 else
1068 (*info->fprintf_func) (info->stream, "$%ld",
1069 (l >> OP_SH_RD) & OP_MASK_RD);
1070 break;
1071
1072 case 'K':
1073 (*info->fprintf_func) (info->stream, "%s",
1074 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1075 break;
1076
1077 case 'N':
1078 (*info->fprintf_func) (info->stream, "$fcc%ld",
1079 (l >> OP_SH_BCC) & OP_MASK_BCC);
1080 break;
1081
1082 case 'M':
1083 (*info->fprintf_func) (info->stream, "$fcc%ld",
1084 (l >> OP_SH_CCC) & OP_MASK_CCC);
1085 break;
1086
1087 case 'P':
1088 (*info->fprintf_func) (info->stream, "%ld",
1089 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1090 break;
1091
1092 case 'e':
1093 (*info->fprintf_func) (info->stream, "%ld",
1094 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1095 break;
1096
1097 case '%':
1098 (*info->fprintf_func) (info->stream, "%ld",
1099 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1100 break;
1101
1102 case 'H':
1103 (*info->fprintf_func) (info->stream, "%ld",
1104 (l >> OP_SH_SEL) & OP_MASK_SEL);
1105 break;
1106
1107 case 'O':
1108 (*info->fprintf_func) (info->stream, "%ld",
1109 (l >> OP_SH_ALN) & OP_MASK_ALN);
1110 break;
1111
1112 case 'Q':
1113 {
1114 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1115
1116 if ((vsel & 0x10) == 0)
1117 {
1118 int fmt;
1119
1120 vsel &= 0x0f;
1121 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1122 if ((vsel & 1) == 0)
1123 break;
1124 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1125 (l >> OP_SH_FT) & OP_MASK_FT,
1126 vsel >> 1);
1127 }
1128 else if ((vsel & 0x08) == 0)
1129 {
1130 (*info->fprintf_func) (info->stream, "$v%ld",
1131 (l >> OP_SH_FT) & OP_MASK_FT);
1132 }
1133 else
1134 {
1135 (*info->fprintf_func) (info->stream, "0x%lx",
1136 (l >> OP_SH_FT) & OP_MASK_FT);
1137 }
1138 }
1139 break;
1140
1141 case 'X':
1142 (*info->fprintf_func) (info->stream, "$v%ld",
1143 (l >> OP_SH_FD) & OP_MASK_FD);
1144 break;
1145
1146 case 'Y':
1147 (*info->fprintf_func) (info->stream, "$v%ld",
1148 (l >> OP_SH_FS) & OP_MASK_FS);
1149 break;
1150
1151 case 'Z':
1152 (*info->fprintf_func) (info->stream, "$v%ld",
1153 (l >> OP_SH_FT) & OP_MASK_FT);
1154 break;
1155
1156 default:
1157 /* xgettext:c-format */
1158 (*info->fprintf_func) (info->stream,
1159 _("# internal error, undefined modifier(%c)"),
1160 *d);
1161 return;
1162 }
1163 }
1164 }
1165
1166 /* Print the mips instruction at address MEMADDR in debugged memory,
1167 on using INFO. Returns length of the instruction, in bytes, which is
1168 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1169 this is little-endian code. */
1170
1171 static int
print_insn_mips(bfd_vma memaddr,unsigned long int word,struct disassemble_info * info)1172 print_insn_mips (bfd_vma memaddr,
1173 unsigned long int word,
1174 struct disassemble_info *info)
1175 {
1176 const struct mips_opcode *op;
1177 static bfd_boolean init = 0;
1178 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1179
1180 /* Build a hash table to shorten the search time. */
1181 if (! init)
1182 {
1183 unsigned int i;
1184
1185 for (i = 0; i <= OP_MASK_OP; i++)
1186 {
1187 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1188 {
1189 if (op->pinfo == INSN_MACRO
1190 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1191 continue;
1192 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1193 {
1194 mips_hash[i] = op;
1195 break;
1196 }
1197 }
1198 }
1199
1200 init = 1;
1201 }
1202
1203 info->bytes_per_chunk = INSNLEN;
1204 info->display_endian = info->endian;
1205 info->insn_info_valid = 1;
1206 info->branch_delay_insns = 0;
1207 info->data_size = 0;
1208 info->insn_type = dis_nonbranch;
1209 info->target = 0;
1210 info->target2 = 0;
1211
1212 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1213 if (op != NULL)
1214 {
1215 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1216 {
1217 if (op->pinfo != INSN_MACRO
1218 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1219 && (word & op->mask) == op->match)
1220 {
1221 const char *d;
1222
1223 /* We always allow to disassemble the jalx instruction. */
1224 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1225 && strcmp (op->name, "jalx"))
1226 continue;
1227
1228 /* Figure out instruction type and branch delay information. */
1229 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1230 {
1231 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1232 info->insn_type = dis_jsr;
1233 else
1234 info->insn_type = dis_branch;
1235 info->branch_delay_insns = 1;
1236 }
1237 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1238 | INSN_COND_BRANCH_LIKELY)) != 0)
1239 {
1240 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1241 info->insn_type = dis_condjsr;
1242 else
1243 info->insn_type = dis_condbranch;
1244 info->branch_delay_insns = 1;
1245 }
1246 else if ((op->pinfo & (INSN_STORE_MEMORY
1247 | INSN_LOAD_MEMORY_DELAY)) != 0)
1248 info->insn_type = dis_dref;
1249
1250 (*info->fprintf_func) (info->stream, "%s", op->name);
1251
1252 d = op->args;
1253 if (d != NULL && *d != '\0')
1254 {
1255 (*info->fprintf_func) (info->stream, "\t");
1256 print_insn_args (d, word, memaddr, info);
1257 }
1258
1259 return INSNLEN;
1260 }
1261 }
1262 }
1263
1264 /* Handle undefined instructions. */
1265 info->insn_type = dis_noninsn;
1266 (*info->fprintf_func) (info->stream, "0x%lx", word);
1267 return INSNLEN;
1268 }
1269
1270 /* Disassemble an operand for a mips16 instruction. */
1271
1272 static void
print_mips16_insn_arg(char type,const struct mips_opcode * op,int l,bfd_boolean use_extend,int extend,bfd_vma memaddr,struct disassemble_info * info)1273 print_mips16_insn_arg (char type,
1274 const struct mips_opcode *op,
1275 int l,
1276 bfd_boolean use_extend,
1277 int extend,
1278 bfd_vma memaddr,
1279 struct disassemble_info *info)
1280 {
1281 switch (type)
1282 {
1283 case ',':
1284 case '(':
1285 case ')':
1286 (*info->fprintf_func) (info->stream, "%c", type);
1287 break;
1288
1289 case 'y':
1290 case 'w':
1291 (*info->fprintf_func) (info->stream, "%s",
1292 mips16_reg_names[((l >> MIPS16OP_SH_RY)
1293 & MIPS16OP_MASK_RY)]);
1294 break;
1295
1296 case 'x':
1297 case 'v':
1298 (*info->fprintf_func) (info->stream, "%s",
1299 mips16_reg_names[((l >> MIPS16OP_SH_RX)
1300 & MIPS16OP_MASK_RX)]);
1301 break;
1302
1303 case 'z':
1304 (*info->fprintf_func) (info->stream, "%s",
1305 mips16_reg_names[((l >> MIPS16OP_SH_RZ)
1306 & MIPS16OP_MASK_RZ)]);
1307 break;
1308
1309 case 'Z':
1310 (*info->fprintf_func) (info->stream, "%s",
1311 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
1312 & MIPS16OP_MASK_MOVE32Z)]);
1313 break;
1314
1315 case '0':
1316 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1317 break;
1318
1319 case 'S':
1320 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1321 break;
1322
1323 case 'P':
1324 (*info->fprintf_func) (info->stream, "$pc");
1325 break;
1326
1327 case 'R':
1328 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1329 break;
1330
1331 case 'X':
1332 (*info->fprintf_func) (info->stream, "%s",
1333 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1334 & MIPS16OP_MASK_REGR32)]);
1335 break;
1336
1337 case 'Y':
1338 (*info->fprintf_func) (info->stream, "%s",
1339 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1340 break;
1341
1342 case '<':
1343 case '>':
1344 case '[':
1345 case ']':
1346 case '4':
1347 case '5':
1348 case 'H':
1349 case 'W':
1350 case 'D':
1351 case 'j':
1352 case '6':
1353 case '8':
1354 case 'V':
1355 case 'C':
1356 case 'U':
1357 case 'k':
1358 case 'K':
1359 case 'p':
1360 case 'q':
1361 case 'A':
1362 case 'B':
1363 case 'E':
1364 {
1365 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1366
1367 shift = 0;
1368 signedp = 0;
1369 extbits = 16;
1370 pcrel = 0;
1371 extu = 0;
1372 branch = 0;
1373 switch (type)
1374 {
1375 case '<':
1376 nbits = 3;
1377 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1378 extbits = 5;
1379 extu = 1;
1380 break;
1381 case '>':
1382 nbits = 3;
1383 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1384 extbits = 5;
1385 extu = 1;
1386 break;
1387 case '[':
1388 nbits = 3;
1389 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1390 extbits = 6;
1391 extu = 1;
1392 break;
1393 case ']':
1394 nbits = 3;
1395 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1396 extbits = 6;
1397 extu = 1;
1398 break;
1399 case '4':
1400 nbits = 4;
1401 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1402 signedp = 1;
1403 extbits = 15;
1404 break;
1405 case '5':
1406 nbits = 5;
1407 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1408 info->insn_type = dis_dref;
1409 info->data_size = 1;
1410 break;
1411 case 'H':
1412 nbits = 5;
1413 shift = 1;
1414 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1415 info->insn_type = dis_dref;
1416 info->data_size = 2;
1417 break;
1418 case 'W':
1419 nbits = 5;
1420 shift = 2;
1421 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1422 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1423 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1424 {
1425 info->insn_type = dis_dref;
1426 info->data_size = 4;
1427 }
1428 break;
1429 case 'D':
1430 nbits = 5;
1431 shift = 3;
1432 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1433 info->insn_type = dis_dref;
1434 info->data_size = 8;
1435 break;
1436 case 'j':
1437 nbits = 5;
1438 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1439 signedp = 1;
1440 break;
1441 case '6':
1442 nbits = 6;
1443 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1444 break;
1445 case '8':
1446 nbits = 8;
1447 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1448 break;
1449 case 'V':
1450 nbits = 8;
1451 shift = 2;
1452 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1453 /* FIXME: This might be lw, or it might be addiu to $sp or
1454 $pc. We assume it's load. */
1455 info->insn_type = dis_dref;
1456 info->data_size = 4;
1457 break;
1458 case 'C':
1459 nbits = 8;
1460 shift = 3;
1461 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1462 info->insn_type = dis_dref;
1463 info->data_size = 8;
1464 break;
1465 case 'U':
1466 nbits = 8;
1467 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1468 extu = 1;
1469 break;
1470 case 'k':
1471 nbits = 8;
1472 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1473 signedp = 1;
1474 break;
1475 case 'K':
1476 nbits = 8;
1477 shift = 3;
1478 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1479 signedp = 1;
1480 break;
1481 case 'p':
1482 nbits = 8;
1483 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1484 signedp = 1;
1485 pcrel = 1;
1486 branch = 1;
1487 info->insn_type = dis_condbranch;
1488 break;
1489 case 'q':
1490 nbits = 11;
1491 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1492 signedp = 1;
1493 pcrel = 1;
1494 branch = 1;
1495 info->insn_type = dis_branch;
1496 break;
1497 case 'A':
1498 nbits = 8;
1499 shift = 2;
1500 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1501 pcrel = 1;
1502 /* FIXME: This can be lw or la. We assume it is lw. */
1503 info->insn_type = dis_dref;
1504 info->data_size = 4;
1505 break;
1506 case 'B':
1507 nbits = 5;
1508 shift = 3;
1509 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1510 pcrel = 1;
1511 info->insn_type = dis_dref;
1512 info->data_size = 8;
1513 break;
1514 case 'E':
1515 nbits = 5;
1516 shift = 2;
1517 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1518 pcrel = 1;
1519 break;
1520 default:
1521 abort ();
1522 }
1523
1524 if (! use_extend)
1525 {
1526 if (signedp && immed >= (1 << (nbits - 1)))
1527 immed -= 1 << nbits;
1528 immed <<= shift;
1529 if ((type == '<' || type == '>' || type == '[' || type == ']')
1530 && immed == 0)
1531 immed = 8;
1532 }
1533 else
1534 {
1535 if (extbits == 16)
1536 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1537 else if (extbits == 15)
1538 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1539 else
1540 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1541 immed &= (1 << extbits) - 1;
1542 if (! extu && immed >= (1 << (extbits - 1)))
1543 immed -= 1 << extbits;
1544 }
1545
1546 if (! pcrel)
1547 (*info->fprintf_func) (info->stream, "%d", immed);
1548 else
1549 {
1550 bfd_vma baseaddr;
1551
1552 if (branch)
1553 {
1554 immed *= 2;
1555 baseaddr = memaddr + 2;
1556 }
1557 else if (use_extend)
1558 baseaddr = memaddr - 2;
1559 else
1560 {
1561 int status;
1562 bfd_byte buffer[2];
1563
1564 baseaddr = memaddr;
1565
1566 /* If this instruction is in the delay slot of a jr
1567 instruction, the base address is the address of the
1568 jr instruction. If it is in the delay slot of jalr
1569 instruction, the base address is the address of the
1570 jalr instruction. This test is unreliable: we have
1571 no way of knowing whether the previous word is
1572 instruction or data. */
1573 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1574 info);
1575 if (status == 0
1576 && (((info->endian == BFD_ENDIAN_BIG
1577 ? bfd_getb16 (buffer)
1578 : bfd_getl16 (buffer))
1579 & 0xf800) == 0x1800))
1580 baseaddr = memaddr - 4;
1581 else
1582 {
1583 status = (*info->read_memory_func) (memaddr - 2, buffer,
1584 2, info);
1585 if (status == 0
1586 && (((info->endian == BFD_ENDIAN_BIG
1587 ? bfd_getb16 (buffer)
1588 : bfd_getl16 (buffer))
1589 & 0xf81f) == 0xe800))
1590 baseaddr = memaddr - 2;
1591 }
1592 }
1593 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1594 (*info->print_address_func) (info->target, info);
1595 }
1596 }
1597 break;
1598
1599 case 'a':
1600 if (! use_extend)
1601 extend = 0;
1602 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1603 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1604 (*info->print_address_func) (info->target, info);
1605 info->insn_type = dis_jsr;
1606 info->branch_delay_insns = 1;
1607 break;
1608
1609 case 'l':
1610 case 'L':
1611 {
1612 int need_comma, amask, smask;
1613
1614 need_comma = 0;
1615
1616 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1617
1618 amask = (l >> 3) & 7;
1619
1620 if (amask > 0 && amask < 5)
1621 {
1622 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1623 if (amask > 1)
1624 (*info->fprintf_func) (info->stream, "-%s",
1625 mips_gpr_names[amask + 3]);
1626 need_comma = 1;
1627 }
1628
1629 smask = (l >> 1) & 3;
1630 if (smask == 3)
1631 {
1632 (*info->fprintf_func) (info->stream, "%s??",
1633 need_comma ? "," : "");
1634 need_comma = 1;
1635 }
1636 else if (smask > 0)
1637 {
1638 (*info->fprintf_func) (info->stream, "%s%s",
1639 need_comma ? "," : "",
1640 mips_gpr_names[16]);
1641 if (smask > 1)
1642 (*info->fprintf_func) (info->stream, "-%s",
1643 mips_gpr_names[smask + 15]);
1644 need_comma = 1;
1645 }
1646
1647 if (l & 1)
1648 {
1649 (*info->fprintf_func) (info->stream, "%s%s",
1650 need_comma ? "," : "",
1651 mips_gpr_names[31]);
1652 need_comma = 1;
1653 }
1654
1655 if (amask == 5 || amask == 6)
1656 {
1657 (*info->fprintf_func) (info->stream, "%s$f0",
1658 need_comma ? "," : "");
1659 if (amask == 6)
1660 (*info->fprintf_func) (info->stream, "-$f1");
1661 }
1662 }
1663 break;
1664
1665 case 'm':
1666 case 'M':
1667 /* MIPS16e save/restore. */
1668 {
1669 int need_comma = 0;
1670 int amask, args, statics;
1671 int nsreg, smask;
1672 int framesz;
1673 int i, j;
1674
1675 l = l & 0x7f;
1676 if (use_extend)
1677 l |= extend << 16;
1678
1679 amask = (l >> 16) & 0xf;
1680 if (amask == MIPS16_ALL_ARGS)
1681 {
1682 args = 4;
1683 statics = 0;
1684 }
1685 else if (amask == MIPS16_ALL_STATICS)
1686 {
1687 args = 0;
1688 statics = 4;
1689 }
1690 else
1691 {
1692 args = amask >> 2;
1693 statics = amask & 3;
1694 }
1695
1696 if (args > 0) {
1697 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1698 if (args > 1)
1699 (*info->fprintf_func) (info->stream, "-%s",
1700 mips_gpr_names[4 + args - 1]);
1701 need_comma = 1;
1702 }
1703
1704 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1705 if (framesz == 0 && !use_extend)
1706 framesz = 128;
1707
1708 (*info->fprintf_func) (info->stream, "%s%d",
1709 need_comma ? "," : "",
1710 framesz);
1711
1712 if (l & 0x40) /* $ra */
1713 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1714
1715 nsreg = (l >> 24) & 0x7;
1716 smask = 0;
1717 if (l & 0x20) /* $s0 */
1718 smask |= 1 << 0;
1719 if (l & 0x10) /* $s1 */
1720 smask |= 1 << 1;
1721 if (nsreg > 0) /* $s2-$s8 */
1722 smask |= ((1 << nsreg) - 1) << 2;
1723
1724 /* Find first set static reg bit. */
1725 for (i = 0; i < 9; i++)
1726 {
1727 if (smask & (1 << i))
1728 {
1729 (*info->fprintf_func) (info->stream, ",%s",
1730 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1731 /* Skip over string of set bits. */
1732 for (j = i; smask & (2 << j); j++)
1733 continue;
1734 if (j > i)
1735 (*info->fprintf_func) (info->stream, "-%s",
1736 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1737 i = j + 1;
1738 }
1739 }
1740
1741 /* Statics $ax - $a3. */
1742 if (statics == 1)
1743 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1744 else if (statics > 0)
1745 (*info->fprintf_func) (info->stream, ",%s-%s",
1746 mips_gpr_names[7 - statics + 1],
1747 mips_gpr_names[7]);
1748 }
1749 break;
1750
1751 default:
1752 /* xgettext:c-format */
1753 (*info->fprintf_func)
1754 (info->stream,
1755 _("# internal disassembler error, unrecognised modifier (%c)"),
1756 type);
1757 abort ();
1758 }
1759 }
1760
1761 /* Disassemble mips16 instructions. */
1762
1763 static int
print_insn_mips16(bfd_vma memaddr,struct disassemble_info * info)1764 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1765 {
1766 int status;
1767 bfd_byte buffer[2];
1768 int length;
1769 int insn;
1770 bfd_boolean use_extend;
1771 int extend = 0;
1772 const struct mips_opcode *op, *opend;
1773
1774 info->bytes_per_chunk = 2;
1775 info->display_endian = info->endian;
1776 info->insn_info_valid = 1;
1777 info->branch_delay_insns = 0;
1778 info->data_size = 0;
1779 info->insn_type = dis_nonbranch;
1780 info->target = 0;
1781 info->target2 = 0;
1782
1783 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1784 if (status != 0)
1785 {
1786 (*info->memory_error_func) (status, memaddr, info);
1787 return -1;
1788 }
1789
1790 length = 2;
1791
1792 if (info->endian == BFD_ENDIAN_BIG)
1793 insn = bfd_getb16 (buffer);
1794 else
1795 insn = bfd_getl16 (buffer);
1796
1797 /* Handle the extend opcode specially. */
1798 use_extend = FALSE;
1799 if ((insn & 0xf800) == 0xf000)
1800 {
1801 use_extend = TRUE;
1802 extend = insn & 0x7ff;
1803
1804 memaddr += 2;
1805
1806 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1807 if (status != 0)
1808 {
1809 (*info->fprintf_func) (info->stream, "extend 0x%x",
1810 (unsigned int) extend);
1811 (*info->memory_error_func) (status, memaddr, info);
1812 return -1;
1813 }
1814
1815 if (info->endian == BFD_ENDIAN_BIG)
1816 insn = bfd_getb16 (buffer);
1817 else
1818 insn = bfd_getl16 (buffer);
1819
1820 /* Check for an extend opcode followed by an extend opcode. */
1821 if ((insn & 0xf800) == 0xf000)
1822 {
1823 (*info->fprintf_func) (info->stream, "extend 0x%x",
1824 (unsigned int) extend);
1825 info->insn_type = dis_noninsn;
1826 return length;
1827 }
1828
1829 length += 2;
1830 }
1831
1832 /* FIXME: Should probably use a hash table on the major opcode here. */
1833
1834 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1835 for (op = mips16_opcodes; op < opend; op++)
1836 {
1837 if (op->pinfo != INSN_MACRO
1838 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1839 && (insn & op->mask) == op->match)
1840 {
1841 const char *s;
1842
1843 if (strchr (op->args, 'a') != NULL)
1844 {
1845 if (use_extend)
1846 {
1847 (*info->fprintf_func) (info->stream, "extend 0x%x",
1848 (unsigned int) extend);
1849 info->insn_type = dis_noninsn;
1850 return length - 2;
1851 }
1852
1853 use_extend = FALSE;
1854
1855 memaddr += 2;
1856
1857 status = (*info->read_memory_func) (memaddr, buffer, 2,
1858 info);
1859 if (status == 0)
1860 {
1861 use_extend = TRUE;
1862 if (info->endian == BFD_ENDIAN_BIG)
1863 extend = bfd_getb16 (buffer);
1864 else
1865 extend = bfd_getl16 (buffer);
1866 length += 2;
1867 }
1868 }
1869
1870 (*info->fprintf_func) (info->stream, "%s", op->name);
1871 if (op->args[0] != '\0')
1872 (*info->fprintf_func) (info->stream, "\t");
1873
1874 for (s = op->args; *s != '\0'; s++)
1875 {
1876 if (*s == ','
1877 && s[1] == 'w'
1878 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1879 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1880 {
1881 /* Skip the register and the comma. */
1882 ++s;
1883 continue;
1884 }
1885 if (*s == ','
1886 && s[1] == 'v'
1887 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1888 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1889 {
1890 /* Skip the register and the comma. */
1891 ++s;
1892 continue;
1893 }
1894 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1895 info);
1896 }
1897
1898 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1899 {
1900 info->branch_delay_insns = 1;
1901 if (info->insn_type != dis_jsr)
1902 info->insn_type = dis_branch;
1903 }
1904
1905 return length;
1906 }
1907 }
1908
1909 if (use_extend)
1910 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1911 (*info->fprintf_func) (info->stream, "0x%x", insn);
1912 info->insn_type = dis_noninsn;
1913
1914 return length;
1915 }
1916
1917 /* In an environment where we do not know the symbol type of the
1918 instruction we are forced to assume that the low order bit of the
1919 instructions' address may mark it as a mips16 instruction. If we
1920 are single stepping, or the pc is within the disassembled function,
1921 this works. Otherwise, we need a clue. Sometimes. */
1922
1923 static int
_print_insn_mips(bfd_vma memaddr,struct disassemble_info * info,enum bfd_endian endianness)1924 _print_insn_mips (bfd_vma memaddr,
1925 struct disassemble_info *info,
1926 enum bfd_endian endianness)
1927 {
1928 bfd_byte buffer[INSNLEN];
1929 int status;
1930
1931 set_default_mips_dis_options (info);
1932 parse_mips_dis_options (info->disassembler_options);
1933
1934 #if 1
1935 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1936 /* Only a few tools will work this way. */
1937 if (memaddr & 0x01)
1938 return print_insn_mips16 (memaddr, info);
1939 #endif
1940
1941 #if SYMTAB_AVAILABLE
1942 if (info->mach == bfd_mach_mips16
1943 || (info->flavour == bfd_target_elf_flavour
1944 && info->symbols != NULL
1945 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1946 == STO_MIPS16)))
1947 return print_insn_mips16 (memaddr, info);
1948 #endif
1949
1950 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
1951 if (status == 0)
1952 {
1953 unsigned long insn;
1954
1955 if (endianness == BFD_ENDIAN_BIG)
1956 insn = (unsigned long) bfd_getb32 (buffer);
1957 else
1958 insn = (unsigned long) bfd_getl32 (buffer);
1959
1960 return print_insn_mips (memaddr, insn, info);
1961 }
1962 else
1963 {
1964 (*info->memory_error_func) (status, memaddr, info);
1965 return -1;
1966 }
1967 }
1968
1969 int
print_insn_big_mips(bfd_vma memaddr,struct disassemble_info * info)1970 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
1971 {
1972 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
1973 }
1974
1975 int
print_insn_little_mips(bfd_vma memaddr,struct disassemble_info * info)1976 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
1977 {
1978 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
1979 }
1980
1981 void
print_mips_disassembler_options(FILE * stream)1982 print_mips_disassembler_options (FILE *stream)
1983 {
1984 unsigned int i;
1985
1986 fprintf (stream, _("\n\
1987 The following MIPS specific disassembler options are supported for use\n\
1988 with the -M switch (multiple options should be separated by commas):\n"));
1989
1990 fprintf (stream, _("\n\
1991 gpr-names=ABI Print GPR names according to specified ABI.\n\
1992 Default: based on binary being disassembled.\n"));
1993
1994 fprintf (stream, _("\n\
1995 fpr-names=ABI Print FPR names according to specified ABI.\n\
1996 Default: numeric.\n"));
1997
1998 fprintf (stream, _("\n\
1999 cp0-names=ARCH Print CP0 register names according to\n\
2000 specified architecture.\n\
2001 Default: based on binary being disassembled.\n"));
2002
2003 fprintf (stream, _("\n\
2004 hwr-names=ARCH Print HWR names according to specified \n\
2005 architecture.\n\
2006 Default: based on binary being disassembled.\n"));
2007
2008 fprintf (stream, _("\n\
2009 reg-names=ABI Print GPR and FPR names according to\n\
2010 specified ABI.\n"));
2011
2012 fprintf (stream, _("\n\
2013 reg-names=ARCH Print CP0 register and HWR names according to\n\
2014 specified architecture.\n"));
2015
2016 fprintf (stream, _("\n\
2017 For the options above, the following values are supported for \"ABI\":\n\
2018 "));
2019 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2020 fprintf (stream, " %s", mips_abi_choices[i].name);
2021 fprintf (stream, _("\n"));
2022
2023 fprintf (stream, _("\n\
2024 For the options above, The following values are supported for \"ARCH\":\n\
2025 "));
2026 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2027 if (*mips_arch_choices[i].name != '\0')
2028 fprintf (stream, " %s", mips_arch_choices[i].name);
2029 fprintf (stream, _("\n"));
2030
2031 fprintf (stream, _("\n"));
2032 }
2033