1 //===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AMDGPU specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AMDGPUTargetStreamer.h"
14 #include "AMDGPUPTNote.h"
15 #include "AMDKernelCodeT.h"
16 #include "Utils/AMDGPUBaseInfo.h"
17 #include "Utils/AMDKernelCodeTUtils.h"
18 #include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h"
19 #include "llvm/BinaryFormat/ELF.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCELFStreamer.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/AMDGPUMetadata.h"
26 #include "llvm/Support/AMDHSAKernelDescriptor.h"
27 #include "llvm/Support/Casting.h"
28 #include "llvm/Support/FormattedStream.h"
29 #include "llvm/Support/TargetParser.h"
30
31 using namespace llvm;
32 using namespace llvm::AMDGPU;
33
34 //===----------------------------------------------------------------------===//
35 // AMDGPUTargetStreamer
36 //===----------------------------------------------------------------------===//
37
convertIsaVersionV2(uint32_t & Major,uint32_t & Minor,uint32_t & Stepping,bool Sramecc,bool Xnack)38 static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor,
39 uint32_t &Stepping, bool Sramecc, bool Xnack) {
40 if (Major == 9 && Minor == 0) {
41 switch (Stepping) {
42 case 0:
43 case 2:
44 case 4:
45 case 6:
46 if (Xnack)
47 Stepping++;
48 }
49 }
50 }
51
EmitHSAMetadataV2(StringRef HSAMetadataString)52 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) {
53 HSAMD::Metadata HSAMetadata;
54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
55 return false;
56 return EmitHSAMetadata(HSAMetadata);
57 }
58
EmitHSAMetadataV3(StringRef HSAMetadataString)59 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
60 msgpack::Document HSAMetadataDoc;
61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
62 return false;
63 return EmitHSAMetadata(HSAMetadataDoc, false);
64 }
65
getArchNameFromElfMach(unsigned ElfMach)66 StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
67 AMDGPU::GPUKind AK;
68
69 switch (ElfMach) {
70 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type");
71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
73 case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
74 case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
75 case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
76 case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
77 case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
78 case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
79 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
80 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
81 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
83 case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
84 case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
85 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
86 case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
87 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
88 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
89 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break;
90 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
91 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
92 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
93 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
94 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
95 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break;
96 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
97 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
98 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
99 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break;
100 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
101 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
102 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
103 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
104 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
105 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break;
106 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
107 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: AK = GK_GFX90A; break;
108 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
109 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: AK = GK_GFX940; break;
110 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
111 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break;
112 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break;
113 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: AK = GK_GFX1013; break;
114 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break;
115 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break;
116 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break;
117 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break;
118 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: AK = GK_GFX1034; break;
119 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: AK = GK_GFX1035; break;
120 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: AK = GK_GFX1036; break;
121 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: AK = GK_GFX1100; break;
122 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: AK = GK_GFX1101; break;
123 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: AK = GK_GFX1102; break;
124 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: AK = GK_GFX1103; break;
125 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
126 }
127
128 StringRef GPUName = getArchNameAMDGCN(AK);
129 if (GPUName != "")
130 return GPUName;
131 return getArchNameR600(AK);
132 }
133
getElfMach(StringRef GPU)134 unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
135 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
136 if (AK == AMDGPU::GPUKind::GK_NONE)
137 AK = parseArchR600(GPU);
138
139 switch (AK) {
140 case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
141 case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
142 case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
143 case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
144 case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
145 case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
146 case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
147 case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
148 case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
149 case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
150 case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
151 case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
152 case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
153 case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
154 case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
155 case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
156 case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
157 case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
158 case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602;
159 case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
160 case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
161 case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
162 case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
163 case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
164 case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705;
165 case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
166 case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
167 case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
168 case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805;
169 case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
170 case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
171 case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
172 case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
173 case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
174 case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908;
175 case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
176 case GK_GFX90A: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A;
177 case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
178 case GK_GFX940: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX940;
179 case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;
180 case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011;
181 case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012;
182 case GK_GFX1013: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013;
183 case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030;
184 case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031;
185 case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032;
186 case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033;
187 case GK_GFX1034: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034;
188 case GK_GFX1035: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035;
189 case GK_GFX1036: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036;
190 case GK_GFX1100: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100;
191 case GK_GFX1101: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101;
192 case GK_GFX1102: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102;
193 case GK_GFX1103: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103;
194 case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
195 }
196
197 llvm_unreachable("unknown GPU");
198 }
199
200 //===----------------------------------------------------------------------===//
201 // AMDGPUTargetAsmStreamer
202 //===----------------------------------------------------------------------===//
203
AMDGPUTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS)204 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
205 formatted_raw_ostream &OS)
206 : AMDGPUTargetStreamer(S), OS(OS) { }
207
208 // A hook for emitting stuff at the end.
209 // We use it for emitting the accumulated PAL metadata as directives.
210 // The PAL metadata is reset after it is emitted.
finish()211 void AMDGPUTargetAsmStreamer::finish() {
212 std::string S;
213 getPALMetadata()->toString(S);
214 OS << S;
215
216 // Reset the pal metadata so its data will not affect a compilation that
217 // reuses this object.
218 getPALMetadata()->reset();
219 }
220
EmitDirectiveAMDGCNTarget()221 void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
222 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
223 }
224
EmitDirectiveHSACodeObjectVersion(uint32_t Major,uint32_t Minor)225 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
226 uint32_t Major, uint32_t Minor) {
227 OS << "\t.hsa_code_object_version " <<
228 Twine(Major) << "," << Twine(Minor) << '\n';
229 }
230
231 void
EmitDirectiveHSACodeObjectISAV2(uint32_t Major,uint32_t Minor,uint32_t Stepping,StringRef VendorName,StringRef ArchName)232 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
233 uint32_t Minor,
234 uint32_t Stepping,
235 StringRef VendorName,
236 StringRef ArchName) {
237 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
238 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << ","
239 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
240 }
241
242 void
EmitAMDKernelCodeT(const amd_kernel_code_t & Header)243 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
244 OS << "\t.amd_kernel_code_t\n";
245 dumpAmdKernelCode(&Header, OS, "\t\t");
246 OS << "\t.end_amd_kernel_code_t\n";
247 }
248
EmitAMDGPUSymbolType(StringRef SymbolName,unsigned Type)249 void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
250 unsigned Type) {
251 switch (Type) {
252 default: llvm_unreachable("Invalid AMDGPU symbol type");
253 case ELF::STT_AMDGPU_HSA_KERNEL:
254 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
255 break;
256 }
257 }
258
emitAMDGPULDS(MCSymbol * Symbol,unsigned Size,Align Alignment)259 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
260 Align Alignment) {
261 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
262 << Alignment.value() << '\n';
263 }
264
EmitISAVersion()265 bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
266 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
267 return true;
268 }
269
EmitHSAMetadata(const AMDGPU::HSAMD::Metadata & HSAMetadata)270 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
271 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
272 std::string HSAMetadataString;
273 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
274 return false;
275
276 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
277 OS << HSAMetadataString << '\n';
278 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
279 return true;
280 }
281
EmitHSAMetadata(msgpack::Document & HSAMetadataDoc,bool Strict)282 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
283 msgpack::Document &HSAMetadataDoc, bool Strict) {
284 HSAMD::V3::MetadataVerifier Verifier(Strict);
285 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
286 return false;
287
288 std::string HSAMetadataString;
289 raw_string_ostream StrOS(HSAMetadataString);
290 HSAMetadataDoc.toYAML(StrOS);
291
292 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
293 OS << StrOS.str() << '\n';
294 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
295 return true;
296 }
297
EmitCodeEnd(const MCSubtargetInfo & STI)298 bool AMDGPUTargetAsmStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
299 const uint32_t Encoded_s_code_end = 0xbf9f0000;
300 const uint32_t Encoded_s_nop = 0xbf800000;
301 uint32_t Encoded_pad = Encoded_s_code_end;
302
303 // Instruction cache line size in bytes.
304 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
305 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
306
307 // Extra padding amount in bytes to support prefetch mode 3.
308 unsigned FillSize = 3 * CacheLineSize;
309
310 if (AMDGPU::isGFX90A(STI)) {
311 Encoded_pad = Encoded_s_nop;
312 FillSize = 16 * CacheLineSize;
313 }
314
315 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
316 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
317 return true;
318 }
319
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo & STI,StringRef KernelName,const amdhsa::kernel_descriptor_t & KD,uint64_t NextVGPR,uint64_t NextSGPR,bool ReserveVCC,bool ReserveFlatScr)320 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
321 const MCSubtargetInfo &STI, StringRef KernelName,
322 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
323 bool ReserveVCC, bool ReserveFlatScr) {
324 IsaVersion IVersion = getIsaVersion(STI.getCPU());
325
326 OS << "\t.amdhsa_kernel " << KernelName << '\n';
327
328 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
329 STREAM << "\t\t" << DIRECTIVE << " " \
330 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
331
332 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
333 << '\n';
334 OS << "\t\t.amdhsa_private_segment_fixed_size "
335 << KD.private_segment_fixed_size << '\n';
336 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
337
338 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD,
339 compute_pgm_rsrc2,
340 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
341
342 if (!hasArchitectedFlatScratch(STI))
343 PRINT_FIELD(
344 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
345 kernel_code_properties,
346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
347 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
348 kernel_code_properties,
349 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
350 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
351 kernel_code_properties,
352 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
353 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
354 kernel_code_properties,
355 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
356 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
357 kernel_code_properties,
358 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
359 if (!hasArchitectedFlatScratch(STI))
360 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
361 kernel_code_properties,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
363 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
364 kernel_code_properties,
365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
366 if (IVersion.Major >= 10)
367 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
368 kernel_code_properties,
369 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
370 if (AMDGPU::getAmdhsaCodeObjectVersion() >= 5)
371 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
372 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
373 PRINT_FIELD(OS,
374 (hasArchitectedFlatScratch(STI)
375 ? ".amdhsa_enable_private_segment"
376 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"),
377 KD, compute_pgm_rsrc2,
378 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
379 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
380 compute_pgm_rsrc2,
381 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
382 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
383 compute_pgm_rsrc2,
384 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
385 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
386 compute_pgm_rsrc2,
387 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
388 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
389 compute_pgm_rsrc2,
390 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
391 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
392 compute_pgm_rsrc2,
393 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
394
395 // These directives are required.
396 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
397 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
398
399 if (AMDGPU::isGFX90A(STI))
400 OS << "\t\t.amdhsa_accum_offset " <<
401 (AMDHSA_BITS_GET(KD.compute_pgm_rsrc3,
402 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
403 << '\n';
404
405 if (!ReserveVCC)
406 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
407 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
408 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
409
410 if (std::optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) {
411 switch (*HsaAbiVer) {
412 default:
413 break;
414 case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
415 break;
416 case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
417 case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
418 case ELF::ELFABIVERSION_AMDGPU_HSA_V5:
419 if (getTargetID()->isXnackSupported())
420 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
421 break;
422 }
423 }
424
425 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
426 compute_pgm_rsrc1,
427 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
428 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
429 compute_pgm_rsrc1,
430 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
431 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
432 compute_pgm_rsrc1,
433 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
434 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
435 compute_pgm_rsrc1,
436 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
437 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
438 compute_pgm_rsrc1,
439 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
440 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
441 compute_pgm_rsrc1,
442 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
443 if (IVersion.Major >= 9)
444 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
445 compute_pgm_rsrc1,
446 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
447 if (AMDGPU::isGFX90A(STI))
448 PRINT_FIELD(OS, ".amdhsa_tg_split", KD,
449 compute_pgm_rsrc3,
450 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
451 if (IVersion.Major >= 10) {
452 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
453 compute_pgm_rsrc1,
454 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE);
455 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
456 compute_pgm_rsrc1,
457 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED);
458 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
459 compute_pgm_rsrc1,
460 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS);
461 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
462 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
463 }
464 PRINT_FIELD(
465 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
466 compute_pgm_rsrc2,
467 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
468 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
469 compute_pgm_rsrc2,
470 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
471 PRINT_FIELD(
472 OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
473 compute_pgm_rsrc2,
474 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
475 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
476 compute_pgm_rsrc2,
477 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
478 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
479 compute_pgm_rsrc2,
480 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
481 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
482 compute_pgm_rsrc2,
483 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
484 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
485 compute_pgm_rsrc2,
486 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
487 #undef PRINT_FIELD
488
489 OS << "\t.end_amdhsa_kernel\n";
490 }
491
492 //===----------------------------------------------------------------------===//
493 // AMDGPUTargetELFStreamer
494 //===----------------------------------------------------------------------===//
495
AMDGPUTargetELFStreamer(MCStreamer & S,const MCSubtargetInfo & STI)496 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S,
497 const MCSubtargetInfo &STI)
498 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
499
getStreamer()500 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
501 return static_cast<MCELFStreamer &>(Streamer);
502 }
503
504 // A hook for emitting stuff at the end.
505 // We use it for emitting the accumulated PAL metadata as a .note record.
506 // The PAL metadata is reset after it is emitted.
finish()507 void AMDGPUTargetELFStreamer::finish() {
508 MCAssembler &MCA = getStreamer().getAssembler();
509 MCA.setELFHeaderEFlags(getEFlags());
510
511 std::string Blob;
512 const char *Vendor = getPALMetadata()->getVendor();
513 unsigned Type = getPALMetadata()->getType();
514 getPALMetadata()->toBlob(Type, Blob);
515 if (Blob.empty())
516 return;
517 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
518 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
519
520 // Reset the pal metadata so its data will not affect a compilation that
521 // reuses this object.
522 getPALMetadata()->reset();
523 }
524
EmitNote(StringRef Name,const MCExpr * DescSZ,unsigned NoteType,function_ref<void (MCELFStreamer &)> EmitDesc)525 void AMDGPUTargetELFStreamer::EmitNote(
526 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
527 function_ref<void(MCELFStreamer &)> EmitDesc) {
528 auto &S = getStreamer();
529 auto &Context = S.getContext();
530
531 auto NameSZ = Name.size() + 1;
532
533 unsigned NoteFlags = 0;
534 // TODO Apparently, this is currently needed for OpenCL as mentioned in
535 // https://reviews.llvm.org/D74995
536 if (STI.getTargetTriple().getOS() == Triple::AMDHSA)
537 NoteFlags = ELF::SHF_ALLOC;
538
539 S.pushSection();
540 S.switchSection(
541 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
542 S.emitInt32(NameSZ); // namesz
543 S.emitValue(DescSZ, 4); // descz
544 S.emitInt32(NoteType); // type
545 S.emitBytes(Name); // name
546 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
547 EmitDesc(S); // desc
548 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
549 S.popSection();
550 }
551
getEFlags()552 unsigned AMDGPUTargetELFStreamer::getEFlags() {
553 switch (STI.getTargetTriple().getArch()) {
554 default:
555 llvm_unreachable("Unsupported Arch");
556 case Triple::r600:
557 return getEFlagsR600();
558 case Triple::amdgcn:
559 return getEFlagsAMDGCN();
560 }
561 }
562
getEFlagsR600()563 unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
564 assert(STI.getTargetTriple().getArch() == Triple::r600);
565
566 return getElfMach(STI.getCPU());
567 }
568
getEFlagsAMDGCN()569 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
570 assert(STI.getTargetTriple().getArch() == Triple::amdgcn);
571
572 switch (STI.getTargetTriple().getOS()) {
573 default:
574 // TODO: Why are some tests have "mingw" listed as OS?
575 // llvm_unreachable("Unsupported OS");
576 case Triple::UnknownOS:
577 return getEFlagsUnknownOS();
578 case Triple::AMDHSA:
579 return getEFlagsAMDHSA();
580 case Triple::AMDPAL:
581 return getEFlagsAMDPAL();
582 case Triple::Mesa3D:
583 return getEFlagsMesa3D();
584 }
585 }
586
getEFlagsUnknownOS()587 unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
588 // TODO: Why are some tests have "mingw" listed as OS?
589 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
590
591 return getEFlagsV3();
592 }
593
getEFlagsAMDHSA()594 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
595 assert(STI.getTargetTriple().getOS() == Triple::AMDHSA);
596
597 if (std::optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) {
598 switch (*HsaAbiVer) {
599 case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
600 case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
601 return getEFlagsV3();
602 case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
603 case ELF::ELFABIVERSION_AMDGPU_HSA_V5:
604 return getEFlagsV4();
605 }
606 }
607
608 llvm_unreachable("HSA OS ABI Version identification must be defined");
609 }
610
getEFlagsAMDPAL()611 unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
612 assert(STI.getTargetTriple().getOS() == Triple::AMDPAL);
613
614 return getEFlagsV3();
615 }
616
getEFlagsMesa3D()617 unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
618 assert(STI.getTargetTriple().getOS() == Triple::Mesa3D);
619
620 return getEFlagsV3();
621 }
622
getEFlagsV3()623 unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
624 unsigned EFlagsV3 = 0;
625
626 // mach.
627 EFlagsV3 |= getElfMach(STI.getCPU());
628
629 // xnack.
630 if (getTargetID()->isXnackOnOrAny())
631 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3;
632 // sramecc.
633 if (getTargetID()->isSramEccOnOrAny())
634 EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3;
635
636 return EFlagsV3;
637 }
638
getEFlagsV4()639 unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
640 unsigned EFlagsV4 = 0;
641
642 // mach.
643 EFlagsV4 |= getElfMach(STI.getCPU());
644
645 // xnack.
646 switch (getTargetID()->getXnackSetting()) {
647 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
648 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4;
649 break;
650 case AMDGPU::IsaInfo::TargetIDSetting::Any:
651 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4;
652 break;
653 case AMDGPU::IsaInfo::TargetIDSetting::Off:
654 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4;
655 break;
656 case AMDGPU::IsaInfo::TargetIDSetting::On:
657 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4;
658 break;
659 }
660 // sramecc.
661 switch (getTargetID()->getSramEccSetting()) {
662 case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
663 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4;
664 break;
665 case AMDGPU::IsaInfo::TargetIDSetting::Any:
666 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4;
667 break;
668 case AMDGPU::IsaInfo::TargetIDSetting::Off:
669 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4;
670 break;
671 case AMDGPU::IsaInfo::TargetIDSetting::On:
672 EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4;
673 break;
674 }
675
676 return EFlagsV4;
677 }
678
EmitDirectiveAMDGCNTarget()679 void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
680
EmitDirectiveHSACodeObjectVersion(uint32_t Major,uint32_t Minor)681 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
682 uint32_t Major, uint32_t Minor) {
683
684 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()),
685 ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) {
686 OS.emitInt32(Major);
687 OS.emitInt32(Minor);
688 });
689 }
690
691 void
EmitDirectiveHSACodeObjectISAV2(uint32_t Major,uint32_t Minor,uint32_t Stepping,StringRef VendorName,StringRef ArchName)692 AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
693 uint32_t Minor,
694 uint32_t Stepping,
695 StringRef VendorName,
696 StringRef ArchName) {
697 uint16_t VendorNameSize = VendorName.size() + 1;
698 uint16_t ArchNameSize = ArchName.size() + 1;
699
700 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
701 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
702 VendorNameSize + ArchNameSize;
703
704 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
705 EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()),
706 ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) {
707 OS.emitInt16(VendorNameSize);
708 OS.emitInt16(ArchNameSize);
709 OS.emitInt32(Major);
710 OS.emitInt32(Minor);
711 OS.emitInt32(Stepping);
712 OS.emitBytes(VendorName);
713 OS.emitInt8(0); // NULL terminate VendorName
714 OS.emitBytes(ArchName);
715 OS.emitInt8(0); // NULL terminate ArchName
716 });
717 }
718
719 void
EmitAMDKernelCodeT(const amd_kernel_code_t & Header)720 AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
721
722 MCStreamer &OS = getStreamer();
723 OS.pushSection();
724 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
725 OS.popSection();
726 }
727
EmitAMDGPUSymbolType(StringRef SymbolName,unsigned Type)728 void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
729 unsigned Type) {
730 MCSymbolELF *Symbol = cast<MCSymbolELF>(
731 getStreamer().getContext().getOrCreateSymbol(SymbolName));
732 Symbol->setType(Type);
733 }
734
emitAMDGPULDS(MCSymbol * Symbol,unsigned Size,Align Alignment)735 void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
736 Align Alignment) {
737 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
738 SymbolELF->setType(ELF::STT_OBJECT);
739
740 if (!SymbolELF->isBindingSet()) {
741 SymbolELF->setBinding(ELF::STB_GLOBAL);
742 SymbolELF->setExternal(true);
743 }
744
745 if (SymbolELF->declareCommon(Size, Alignment, true)) {
746 report_fatal_error("Symbol: " + Symbol->getName() +
747 " redeclared as different type");
748 }
749
750 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
751 SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
752 }
753
EmitISAVersion()754 bool AMDGPUTargetELFStreamer::EmitISAVersion() {
755 // Create two labels to mark the beginning and end of the desc field
756 // and a MCExpr to calculate the size of the desc field.
757 auto &Context = getContext();
758 auto *DescBegin = Context.createTempSymbol();
759 auto *DescEnd = Context.createTempSymbol();
760 auto *DescSZ = MCBinaryExpr::createSub(
761 MCSymbolRefExpr::create(DescEnd, Context),
762 MCSymbolRefExpr::create(DescBegin, Context), Context);
763
764 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
765 [&](MCELFStreamer &OS) {
766 OS.emitLabel(DescBegin);
767 OS.emitBytes(getTargetID()->toString());
768 OS.emitLabel(DescEnd);
769 });
770 return true;
771 }
772
EmitHSAMetadata(msgpack::Document & HSAMetadataDoc,bool Strict)773 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
774 bool Strict) {
775 HSAMD::V3::MetadataVerifier Verifier(Strict);
776 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
777 return false;
778
779 std::string HSAMetadataString;
780 HSAMetadataDoc.writeToBlob(HSAMetadataString);
781
782 // Create two labels to mark the beginning and end of the desc field
783 // and a MCExpr to calculate the size of the desc field.
784 auto &Context = getContext();
785 auto *DescBegin = Context.createTempSymbol();
786 auto *DescEnd = Context.createTempSymbol();
787 auto *DescSZ = MCBinaryExpr::createSub(
788 MCSymbolRefExpr::create(DescEnd, Context),
789 MCSymbolRefExpr::create(DescBegin, Context), Context);
790
791 EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA,
792 [&](MCELFStreamer &OS) {
793 OS.emitLabel(DescBegin);
794 OS.emitBytes(HSAMetadataString);
795 OS.emitLabel(DescEnd);
796 });
797 return true;
798 }
799
EmitHSAMetadata(const AMDGPU::HSAMD::Metadata & HSAMetadata)800 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(
801 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
802 std::string HSAMetadataString;
803 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
804 return false;
805
806 // Create two labels to mark the beginning and end of the desc field
807 // and a MCExpr to calculate the size of the desc field.
808 auto &Context = getContext();
809 auto *DescBegin = Context.createTempSymbol();
810 auto *DescEnd = Context.createTempSymbol();
811 auto *DescSZ = MCBinaryExpr::createSub(
812 MCSymbolRefExpr::create(DescEnd, Context),
813 MCSymbolRefExpr::create(DescBegin, Context), Context);
814
815 EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA,
816 [&](MCELFStreamer &OS) {
817 OS.emitLabel(DescBegin);
818 OS.emitBytes(HSAMetadataString);
819 OS.emitLabel(DescEnd);
820 });
821 return true;
822 }
823
EmitCodeEnd(const MCSubtargetInfo & STI)824 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
825 const uint32_t Encoded_s_code_end = 0xbf9f0000;
826 const uint32_t Encoded_s_nop = 0xbf800000;
827 uint32_t Encoded_pad = Encoded_s_code_end;
828
829 // Instruction cache line size in bytes.
830 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
831 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
832
833 // Extra padding amount in bytes to support prefetch mode 3.
834 unsigned FillSize = 3 * CacheLineSize;
835
836 if (AMDGPU::isGFX90A(STI)) {
837 Encoded_pad = Encoded_s_nop;
838 FillSize = 16 * CacheLineSize;
839 }
840
841 MCStreamer &OS = getStreamer();
842 OS.pushSection();
843 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
844 for (unsigned I = 0; I < FillSize; I += 4)
845 OS.emitInt32(Encoded_pad);
846 OS.popSection();
847 return true;
848 }
849
EmitAmdhsaKernelDescriptor(const MCSubtargetInfo & STI,StringRef KernelName,const amdhsa::kernel_descriptor_t & KernelDescriptor,uint64_t NextVGPR,uint64_t NextSGPR,bool ReserveVCC,bool ReserveFlatScr)850 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
851 const MCSubtargetInfo &STI, StringRef KernelName,
852 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
853 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) {
854 auto &Streamer = getStreamer();
855 auto &Context = Streamer.getContext();
856
857 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
858 Context.getOrCreateSymbol(Twine(KernelName)));
859 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
860 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
861
862 // Copy kernel descriptor symbol's binding, other and visibility from the
863 // kernel code symbol.
864 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
865 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
866 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
867 // Kernel descriptor symbol's type and size are fixed.
868 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
869 KernelDescriptorSymbol->setSize(
870 MCConstantExpr::create(sizeof(KernelDescriptor), Context));
871
872 // The visibility of the kernel code symbol must be protected or less to allow
873 // static relocations from the kernel descriptor to be used.
874 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
875 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
876
877 Streamer.emitLabel(KernelDescriptorSymbol);
878 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
879 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
880 Streamer.emitInt32(KernelDescriptor.kernarg_size);
881
882 for (uint8_t Res : KernelDescriptor.reserved0)
883 Streamer.emitInt8(Res);
884
885 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
886 // expression being created is:
887 // (start of kernel code) - (start of kernel descriptor)
888 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
889 Streamer.emitValue(MCBinaryExpr::createSub(
890 MCSymbolRefExpr::create(
891 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
892 MCSymbolRefExpr::create(
893 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
894 Context),
895 sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
896 for (uint8_t Res : KernelDescriptor.reserved1)
897 Streamer.emitInt8(Res);
898 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
899 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
900 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
901 Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
902 for (uint8_t Res : KernelDescriptor.reserved2)
903 Streamer.emitInt8(Res);
904 }
905