1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #include <sys/types.h>
28 #include <sys/time.h>
29 #include <sys/nvpair.h>
30 #include <sys/cmn_err.h>
31 #include <sys/cred.h>
32 #include <sys/open.h>
33 #include <sys/ddi.h>
34 #include <sys/sunddi.h>
35 #include <sys/conf.h>
36 #include <sys/modctl.h>
37 #include <sys/cyclic.h>
38 #include <sys/errorq.h>
39 #include <sys/stat.h>
40 #include <sys/cpuvar.h>
41 #include <sys/mc_intel.h>
42 #include <sys/mc.h>
43 #include <sys/fm/protocol.h>
44 #include "nb_log.h"
45 #include "nb5000.h"
46
47 char _depends_on[] = "drv/smbios";
48
49 nvlist_t *inb_mc_nvl;
50 krwlock_t inb_mc_lock;
51
52 char *inb_mc_snapshot;
53 uint_t nb_config_gen;
54 uint_t inb_mc_snapshotgen;
55 size_t inb_mc_snapshotsz;
56 static dev_info_t *inb_dip;
57 int nb_allow_detach = 0;
58 int nb_no_smbios;
59
60 static uint64_t
rank_to_base(uint8_t branch,uint8_t rank,uint8_t * interleave,uint64_t * limit,uint64_t * hole_base,uint64_t * hole_size,uint8_t * wayp,uint8_t * branch_interleavep)61 rank_to_base(uint8_t branch, uint8_t rank, uint8_t *interleave, uint64_t *limit,
62 uint64_t *hole_base, uint64_t *hole_size, uint8_t *wayp,
63 uint8_t *branch_interleavep)
64 {
65 uint8_t i, j;
66 uint64_t base = 0;
67 uint64_t lt = 0;
68 uint64_t h = 0;
69 uint64_t hs = 0;
70 uint8_t il = 1;
71 uint8_t way = 0;
72 uint8_t branch_interleave = 0;
73
74 for (i = 0; i < NB_MEM_RANK_SELECT; i++) {
75 for (j = 0; j < NB_RANKS_IN_SELECT; j++) {
76 if (nb_ranks[branch][i].rank[j] == rank) {
77 base = nb_ranks[branch][i].base;
78 lt = nb_ranks[branch][i].limit;
79 il = nb_ranks[branch][i].interleave;
80 h = nb_ranks[branch][i].hole_base;
81 hs = nb_ranks[branch][i].hole_size;
82 way = j;
83 branch_interleave =
84 nb_ranks[branch][i].branch_interleave;
85 i = NB_MEM_RANK_SELECT;
86 break;
87 }
88 }
89 }
90 if (lt == 0) {
91 for (i = 0; lt == 0 && i < NB_MEM_BRANCH_SELECT; i++) {
92 if (nb_banks[i].way[branch] &&
93 base >= nb_banks[i].base &&
94 base < nb_banks[i].base + nb_banks[i].limit) {
95 lt = nb_banks[i].limit;
96 break;
97 }
98 }
99 }
100 *interleave = il;
101 *limit = lt;
102 *hole_base = h;
103 *hole_size = hs;
104 *wayp = way;
105 *branch_interleavep = branch_interleave;
106 return (base);
107 }
108
109 /*ARGSUSED*/
110 void
inb_rank(nvlist_t * newdimm,nb_dimm_t * nb_dimm,uint8_t channel,uint32_t dimm)111 inb_rank(nvlist_t *newdimm, nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm)
112 {
113 nvlist_t **newrank;
114 int i;
115
116 newrank = kmem_zalloc(sizeof (nvlist_t *) * nb_dimm->nranks, KM_SLEEP);
117 for (i = 0; i < nb_dimm->nranks; i++) {
118 uint64_t dimm_base;
119 uint64_t limit;
120 uint8_t interleave;
121 uint8_t way;
122 uint8_t branch_interleave;
123 uint64_t hole_base;
124 uint64_t hole_size;
125
126 dimm_base = rank_to_base(channel/nb_channels_per_branch,
127 nb_dimm->start_rank + i, &interleave,
128 &limit, &hole_base, &hole_size, &way, &branch_interleave);
129 (void) nvlist_alloc(&newrank[i], NV_UNIQUE_NAME, KM_SLEEP);
130
131 (void) nvlist_add_uint64(newrank[i], "dimm-rank-base",
132 dimm_base);
133 if (hole_size) {
134 (void) nvlist_add_uint64(newrank[i], "dimm-hole",
135 hole_base);
136 (void) nvlist_add_uint64(newrank[i], "dimm-hole-size",
137 hole_size);
138 }
139 (void) nvlist_add_uint64(newrank[i], "dimm-rank-limit",
140 limit);
141 if (interleave > 1) {
142 (void) nvlist_add_uint32(newrank[i],
143 "dimm-rank-interleave", (uint32_t)interleave);
144 (void) nvlist_add_uint32(newrank[i],
145 "dimm-rank-interleave-way", (uint32_t)way);
146 if (branch_interleave) {
147 (void) nvlist_add_uint32(newrank[i],
148 "dimm-rank-interleave-branch", (uint32_t)1);
149 }
150 }
151 }
152 (void) nvlist_add_nvlist_array(newdimm, MCINTEL_NVLIST_RANKS, newrank,
153 nb_dimm->nranks);
154 for (i = 0; i < nb_dimm->nranks; i++)
155 nvlist_free(newrank[i]);
156 kmem_free(newrank, sizeof (nvlist_t *) * nb_dimm->nranks);
157 }
158
159 nvlist_t *
inb_dimm(nb_dimm_t * nb_dimm,uint8_t channel,uint32_t dimm)160 inb_dimm(nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm)
161 {
162 nvlist_t *newdimm;
163 uint8_t t;
164 char sbuf[65];
165
166 (void) nvlist_alloc(&newdimm, NV_UNIQUE_NAME, KM_SLEEP);
167 (void) nvlist_add_uint32(newdimm, "dimm-number", dimm);
168
169 if (nb_dimm->dimm_size >= 1024*1024*1024) {
170 (void) snprintf(sbuf, sizeof (sbuf), "%dG",
171 (int)(nb_dimm->dimm_size / (1024*1024*1024)));
172 } else {
173 (void) snprintf(sbuf, sizeof (sbuf), "%dM",
174 (int)(nb_dimm->dimm_size / (1024*1024)));
175 }
176 (void) nvlist_add_string(newdimm, "dimm-size", sbuf);
177 (void) nvlist_add_uint64(newdimm, "size", nb_dimm->dimm_size);
178 (void) nvlist_add_uint32(newdimm, "nbanks", (uint32_t)nb_dimm->nbanks);
179 (void) nvlist_add_uint32(newdimm, "ncolumn",
180 (uint32_t)nb_dimm->ncolumn);
181 (void) nvlist_add_uint32(newdimm, "nrow", (uint32_t)nb_dimm->nrow);
182 (void) nvlist_add_uint32(newdimm, "width", (uint32_t)nb_dimm->width);
183 (void) nvlist_add_int32(newdimm, MCINTEL_NVLIST_1ST_RANK,
184 (int32_t)nb_dimm->start_rank);
185 (void) nvlist_add_uint32(newdimm, "ranks", (uint32_t)nb_dimm->nranks);
186 inb_rank(newdimm, nb_dimm, channel, dimm);
187 (void) nvlist_add_uint32(newdimm, "manufacture-id",
188 (uint32_t)nb_dimm->manufacture_id);
189 (void) nvlist_add_uint32(newdimm, "manufacture-location",
190 (uint32_t)nb_dimm->manufacture_location);
191 (void) nvlist_add_uint32(newdimm, "manufacture-week",
192 (uint32_t)nb_dimm->manufacture_week);
193 (void) nvlist_add_uint32(newdimm, "manufacture-year",
194 (uint32_t)nb_dimm->manufacture_year + 2000);
195 /* create Sun Serial number from SPD data */
196 (void) snprintf(sbuf, sizeof (sbuf), "%04x%02x%02x%02x%08x",
197 (uint32_t)nb_dimm->manufacture_id & 0x7fff,
198 (uint32_t)nb_dimm->manufacture_location,
199 (uint32_t)nb_dimm->manufacture_year,
200 (uint32_t)nb_dimm->manufacture_week,
201 nb_dimm->serial_number);
202 (void) nvlist_add_string(newdimm, FM_FMRI_HC_SERIAL_ID, sbuf);
203 if (nb_dimm->part_number && nb_dimm->part_number[0]) {
204 t = sizeof (nb_dimm->part_number);
205 (void) strncpy(sbuf, nb_dimm->part_number, t);
206 sbuf[t] = 0;
207 (void) nvlist_add_string(newdimm, FM_FMRI_HC_PART, sbuf);
208 }
209 if (nb_dimm->revision && nb_dimm->revision[0]) {
210 t = sizeof (nb_dimm->revision);
211 (void) strncpy(sbuf, nb_dimm->revision, t);
212 sbuf[t] = 0;
213 (void) nvlist_add_string(newdimm, FM_FMRI_HC_REVISION, sbuf);
214 }
215 t = sizeof (nb_dimm->label);
216 (void) strncpy(sbuf, nb_dimm->label, t);
217 sbuf[t] = 0;
218 (void) nvlist_add_string(newdimm, FM_FAULT_FRU_LABEL, sbuf);
219 return (newdimm);
220 }
221
222 static void
inb_dimmlist(nvlist_t * nvl)223 inb_dimmlist(nvlist_t *nvl)
224 {
225 nvlist_t **dimmlist;
226 nvlist_t **newchannel;
227 int nchannels = nb_number_memory_controllers * nb_channels_per_branch;
228 int nd;
229 uint8_t i, j;
230 nb_dimm_t **dimmpp;
231 nb_dimm_t *dimmp;
232
233 dimmlist = kmem_zalloc(sizeof (nvlist_t *) * nb_dimms_per_channel,
234 KM_SLEEP);
235 newchannel = kmem_zalloc(sizeof (nvlist_t *) * nchannels, KM_SLEEP);
236 dimmpp = nb_dimms;
237 for (i = 0; i < nchannels; i++) {
238 (void) nvlist_alloc(&newchannel[i], NV_UNIQUE_NAME, KM_SLEEP);
239 nd = 0;
240 for (j = 0; j < nb_dimms_per_channel; j++) {
241 dimmp = *dimmpp;
242 if (dimmp != NULL) {
243 dimmlist[nd] = inb_dimm(dimmp, i, (uint32_t)j);
244 nd++;
245 }
246 dimmpp++;
247 }
248 if (nd) {
249 (void) nvlist_add_nvlist_array(newchannel[i],
250 "memory-dimms", dimmlist, nd);
251 for (j = 0; j < nd; j++)
252 nvlist_free(dimmlist[j]);
253 }
254 }
255 (void) nvlist_add_nvlist_array(nvl, MCINTEL_NVLIST_MC, newchannel,
256 nchannels);
257 for (i = 0; i < nchannels; i++)
258 nvlist_free(newchannel[i]);
259 kmem_free(dimmlist, sizeof (nvlist_t *) * nb_dimms_per_channel);
260 kmem_free(newchannel, sizeof (nvlist_t *) * nchannels);
261 }
262
263 static char *
inb_mc_name()264 inb_mc_name()
265 {
266 char *mc;
267
268 switch (nb_chipset) {
269 case INTEL_NB_7300:
270 mc = "Intel 7300";
271 break;
272 case INTEL_NB_5400:
273 mc = "Intel 5400";
274 break;
275 case INTEL_NB_5400A:
276 mc = "Intel 5400A";
277 break;
278 case INTEL_NB_5400B:
279 mc = "Intel 5400B";
280 break;
281 case INTEL_NB_5100:
282 mc = "Intel 5100";
283 break;
284 case INTEL_NB_5000P:
285 mc = "Intel 5000P";
286 break;
287 case INTEL_NB_5000V:
288 mc = "Intel 5000V";
289 break;
290 case INTEL_NB_5000X:
291 mc = "Intel 5000X";
292 break;
293 case INTEL_NB_5000Z:
294 mc = "Intel 5000Z";
295 break;
296 default:
297 mc = "Intel 5000";
298 break;
299 }
300 return (mc);
301 }
302
303 static void
inb_create_nvl()304 inb_create_nvl()
305 {
306 nvlist_t *nvl;
307
308 (void) nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
309 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_VERSTR,
310 MCINTEL_NVLIST_VERS);
311 (void) nvlist_add_string(nvl, "memory-controller", inb_mc_name());
312 if (nb_chipset == INTEL_NB_5100)
313 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_NMEM,
314 (uint8_t)nb_number_memory_controllers);
315 inb_dimmlist(nvl);
316
317 if (inb_mc_nvl)
318 nvlist_free(inb_mc_nvl);
319 inb_mc_nvl = nvl;
320 }
321
322 static void
inb_mc_snapshot_destroy()323 inb_mc_snapshot_destroy()
324 {
325 ASSERT(RW_LOCK_HELD(&inb_mc_lock));
326
327 if (inb_mc_snapshot == NULL)
328 return;
329
330 kmem_free(inb_mc_snapshot, inb_mc_snapshotsz);
331 inb_mc_snapshot = NULL;
332 inb_mc_snapshotsz = 0;
333 inb_mc_snapshotgen++;
334 }
335
336 static int
inb_mc_snapshot_update()337 inb_mc_snapshot_update()
338 {
339 ASSERT(RW_LOCK_HELD(&inb_mc_lock));
340
341 if (inb_mc_snapshot != NULL)
342 return (0);
343
344 if (nvlist_pack(inb_mc_nvl, &inb_mc_snapshot, &inb_mc_snapshotsz,
345 NV_ENCODE_XDR, KM_SLEEP) != 0)
346 return (-1);
347
348 return (0);
349 }
350
351 /*ARGSUSED*/
352 static int
inb_mc_ioctl(dev_t dev,int cmd,intptr_t arg,int mode,cred_t * credp,int * rvalp)353 inb_mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
354 int *rvalp)
355 {
356 int rc = 0;
357 mc_snapshot_info_t mcs;
358
359 if (cmd != MC_IOC_SNAPSHOT_INFO && cmd != MC_IOC_SNAPSHOT)
360 return (EINVAL);
361
362 rw_enter(&inb_mc_lock, RW_READER);
363 if (inb_mc_nvl == NULL || inb_mc_snapshotgen != nb_config_gen) {
364 if (!rw_tryupgrade(&inb_mc_lock)) {
365 rw_exit(&inb_mc_lock);
366 return (EAGAIN);
367 }
368 if (inb_mc_nvl)
369 inb_mc_snapshot_destroy();
370 inb_create_nvl();
371 nb_config_gen = inb_mc_snapshotgen;
372 (void) inb_mc_snapshot_update();
373 }
374 switch (cmd) {
375 case MC_IOC_SNAPSHOT_INFO:
376 mcs.mcs_size = (uint32_t)inb_mc_snapshotsz;
377 mcs.mcs_gen = inb_mc_snapshotgen;
378
379 if (ddi_copyout(&mcs, (void *)arg, sizeof (mc_snapshot_info_t),
380 mode) < 0)
381 rc = EFAULT;
382 break;
383 case MC_IOC_SNAPSHOT:
384 if (ddi_copyout(inb_mc_snapshot, (void *)arg, inb_mc_snapshotsz,
385 mode) < 0)
386 rc = EFAULT;
387 break;
388 }
389 rw_exit(&inb_mc_lock);
390 return (rc);
391 }
392
393 /*ARGSUSED*/
394 static int
inb_mc_getinfo(dev_info_t * dip,ddi_info_cmd_t infocmd,void * arg,void ** result)395 inb_mc_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg,
396 void **result)
397 {
398 if ((infocmd != DDI_INFO_DEVT2DEVINFO &&
399 infocmd != DDI_INFO_DEVT2INSTANCE) || inb_dip == NULL) {
400 *result = NULL;
401 return (DDI_FAILURE);
402 }
403 if (infocmd == DDI_INFO_DEVT2DEVINFO)
404 *result = inb_dip;
405 else
406 *result = (void *)(uintptr_t)ddi_get_instance(inb_dip);
407 return (0);
408 }
409
410 static int
inb_mc_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)411 inb_mc_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
412 {
413 if (cmd == DDI_RESUME) {
414 nb_dev_reinit();
415 return (DDI_SUCCESS);
416 }
417 if (cmd != DDI_ATTACH)
418 return (DDI_FAILURE);
419 if (inb_dip == NULL) {
420 inb_dip = dip;
421 nb_no_smbios = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
422 DDI_PROP_DONTPASS, "no-smbios", 0);
423 nb_pci_cfg_setup(dip);
424 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
425 inb_mc_name());
426 if (nb_dev_init()) {
427 nb_pci_cfg_free();
428 inb_dip = NULL;
429 return (DDI_FAILURE);
430 }
431 if (ddi_create_minor_node(dip, "mc-intel", S_IFCHR, 0,
432 "ddi_mem_ctrl", 0) != DDI_SUCCESS) {
433 cmn_err(CE_WARN, "failed to create minor node"
434 " for memory controller\n");
435 }
436 cmi_hdl_walk(inb_mc_register, NULL, NULL, NULL);
437 }
438
439 return (DDI_SUCCESS);
440 }
441
442 /*ARGSUSED*/
443 static int
inb_mc_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)444 inb_mc_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
445 {
446 if (nb_allow_detach && cmd == DDI_DETACH && dip == inb_dip) {
447 rw_enter(&inb_mc_lock, RW_WRITER);
448 inb_mc_snapshot_destroy();
449 rw_exit(&inb_mc_lock);
450 inb_dip = NULL;
451 return (DDI_SUCCESS);
452 } else if (cmd == DDI_SUSPEND || cmd == DDI_PM_SUSPEND) {
453 return (DDI_SUCCESS);
454 } else {
455 return (DDI_FAILURE);
456 }
457 }
458
459 /*ARGSUSED*/
460 static int
inb_mc_open(dev_t * devp,int flag,int otyp,cred_t * credp)461 inb_mc_open(dev_t *devp, int flag, int otyp, cred_t *credp)
462 {
463 if (otyp != OTYP_CHR)
464 return (EINVAL);
465
466 rw_enter(&inb_mc_lock, RW_READER);
467 if (getminor(*devp) >= 1) {
468 rw_exit(&inb_mc_lock);
469 return (EINVAL);
470 }
471 rw_exit(&inb_mc_lock);
472
473 return (0);
474 }
475
476 /*ARGSUSED*/
477 static int
inb_mc_close(dev_t dev,int flag,int otyp,cred_t * credp)478 inb_mc_close(dev_t dev, int flag, int otyp, cred_t *credp)
479 {
480 return (0);
481 }
482
483
484 static struct cb_ops inb_mc_cb_ops = {
485 inb_mc_open,
486 inb_mc_close,
487 nodev, /* not a block driver */
488 nodev, /* no print routine */
489 nodev, /* no dump routine */
490 nodev, /* no read routine */
491 nodev, /* no write routine */
492 inb_mc_ioctl,
493 nodev, /* no devmap routine */
494 nodev, /* no mmap routine */
495 nodev, /* no segmap routine */
496 nochpoll, /* no chpoll routine */
497 ddi_prop_op,
498 0, /* not a STREAMS driver */
499 D_NEW | D_MP, /* safe for multi-thread/multi-processor */
500 };
501
502 static struct dev_ops inb_mc_ops = {
503 DEVO_REV, /* devo_rev */
504 0, /* devo_refcnt */
505 inb_mc_getinfo, /* devo_getinfo */
506 nulldev, /* devo_identify */
507 nulldev, /* devo_probe */
508 inb_mc_attach, /* devo_attach */
509 inb_mc_detach, /* devo_detach */
510 nodev, /* devo_reset */
511 &inb_mc_cb_ops, /* devo_cb_ops */
512 NULL, /* devo_bus_ops */
513 NULL, /* devo_power */
514 ddi_quiesce_not_needed, /* devo_quiesce */
515 };
516
517 static struct modldrv modldrv = {
518 &mod_driverops,
519 "Intel 5000 Memory Controller Hub Module",
520 &inb_mc_ops
521 };
522
523 static struct modlinkage modlinkage = {
524 MODREV_1,
525 (void *)&modldrv,
526 NULL
527 };
528
529 int
_init(void)530 _init(void)
531 {
532 int err;
533
534 err = nb_init();
535 if (err == 0 && (err = mod_install(&modlinkage)) == 0)
536 rw_init(&inb_mc_lock, NULL, RW_DRIVER, NULL);
537
538 return (err);
539 }
540
541 int
_info(struct modinfo * modinfop)542 _info(struct modinfo *modinfop)
543 {
544 return (mod_info(&modlinkage, modinfop));
545 }
546
547 int
_fini(void)548 _fini(void)
549 {
550 int err;
551
552 if ((err = mod_remove(&modlinkage)) == 0) {
553 nb_unload();
554 rw_destroy(&inb_mc_lock);
555 }
556
557 return (err);
558 }
559