xref: /netbsd-src/usr.sbin/tprof/arch/tprof_armv8.c (revision 0b7c38e1ef9d0813a36844384f5499fe5fd45577)
1 /* $NetBSD: tprof_armv8.c,v 1.1 2018/07/15 16:25:31 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #include <sys/types.h>
31 
32 #include <err.h>
33 #include <stdio.h>
34 #include <stdint.h>
35 #include <stdlib.h>
36 #include <string.h>
37 
38 #include <dev/tprof/tprof_ioctl.h>
39 #include "../tprof.h"
40 
41 struct pmu_event {
42 	uint16_t		event;
43 	const char		*name;
44 };
45 
46 struct pmu_event_table {
47 	const char		*name;
48 	struct pmu_event	*events;
49 	u_int			nevents;
50 	struct pmu_event_table	*next;
51 };
52 
53 /*
54  * Common event numbers, from ARMv8 ARM.
55  */
56 static struct pmu_event pmu_armv8_common_events[] = {
57 	{ 0x0000,	"SW_INCR" },
58 	{ 0x0001,	"L1I_CACHE_REFILL" },
59 	{ 0x0002,	"L1I_TLB_REFILL" },
60 	{ 0x0003,	"L1D_CACHE_REFILL" },
61 	{ 0x0004,	"L1D_CACHE" },
62 	{ 0x0005,	"L1D_TLB_REFILL" },
63 	{ 0x0006,	"LD_RETIRED" },
64 	{ 0x0007,	"ST_RETIRED" },
65 	{ 0x0008,	"INST_RETIRED" },
66 	{ 0x0009,	"EXC_TAKEN" },
67 	{ 0x000a,	"EXC_RETURN" },
68 	{ 0x000b,	"CID_WRITE_RETIRED" },
69 	{ 0x000c,	"PC_WRITE_RETIRED" },
70 	{ 0x000d,	"BR_IMMED_RETIRED" },
71 	{ 0x000e,	"BR_RETURN_RETIRED" },
72 	{ 0x000f,	"UNALIGNED_LDST_RETIRED" },
73 	{ 0x0010,	"BR_MIS_PRED" },
74 	{ 0x0011,	"CPU_CYCLES" },
75 	{ 0x0012,	"BR_PRED" },
76 	{ 0x0013,	"MEM_ACCESS" },
77 	{ 0x0014,	"L1I_CACHE" },
78 	{ 0x0015,	"L1D_CACHE_WB" },
79 	{ 0x0016,	"L2D_CACHE" },
80 	{ 0x0017,	"L2D_CACHE_REFILL" },
81 	{ 0x0018,	"L2D_CACHE_WB" },
82 	{ 0x0019,	"BUS_ACCESS" },
83 	{ 0x001a,	"MEMORY_ERROR" },
84 	{ 0x001b,	"INST_SPEC" },
85 	{ 0x001c,	"TTBR_WRITE_RETIRED" },
86 	{ 0x001d,	"BUS_CYCLES" },
87 	{ 0x001e,	"CHAIN" },
88 	{ 0x001f,	"L1D_CACHE_ALLOCATE" },
89 	{ 0x0020,	"L2D_CACHE_ALLOCATE" },
90 	{ 0x0021,	"BR_RETIRED" },
91 	{ 0x0022,	"BR_MIS_PRED_RETIRED" },
92 	{ 0x0023,	"STALL_FRONTEND" },
93 	{ 0x0024,	"STALL_BACKEND" },
94 	{ 0x0025,	"L1D_TLB" },
95 	{ 0x0026,	"L1I_TLB" },
96 	{ 0x0027,	"L2I_CACHE" },
97 	{ 0x0028,	"L2I_CACHE_REFILL" },
98 	{ 0x0029,	"L3D_CACHE_ALLOCATE" },
99 	{ 0x002a,	"L3D_CACHE_REFILL" },
100 	{ 0x002b,	"L3D_CACHE" },
101 	{ 0x002c,	"L3D_CACHE_WB" },
102 	{ 0x002d,	"L2D_TLB_REFILL" },
103 	{ 0x002e,	"L2I_TLB_REFILL" },
104 	{ 0x002f,	"L2D_TLB" },
105 	{ 0x0030,	"L2I_TLB" },
106 	{ 0x0031,	"REMOTE_ACCESS" },
107 	{ 0x0032,	"LL_CACHE" },
108 	{ 0x0033,	"LL_CACHE_MISS" },
109 	{ 0x0034,	"DTLB_WALK" },
110 	{ 0x0035,	"ITLB_WALK" },
111 	{ 0x0036,	"LL_CACHE_RD" },
112 	{ 0x0037,	"LL_CACHE_MISS_RD" },
113 	{ 0x0038,	"REMOTE_ACCESS_RD" },
114 };
115 
116 static struct pmu_event_table pmu_armv8 = {
117 	.name = "ARMv8 common architectural and microarchitectural events",
118 	.events = pmu_armv8_common_events,
119 	.nevents = __arraycount(pmu_armv8_common_events),
120 	.next = NULL
121 };
122 
123 static struct pmu_event_table *events = NULL;
124 
125 int
tprof_event_init(uint32_t ident)126 tprof_event_init(uint32_t ident)
127 {
128 	if (ident != TPROF_IDENT_ARMV8_GENERIC)
129 		return -1;
130 
131 	events = &pmu_armv8;
132 
133 	return 0;
134 }
135 
136 static void
tprof_event_list_table(struct pmu_event_table * tbl)137 tprof_event_list_table(struct pmu_event_table *tbl)
138 {
139 	u_int n;
140 
141 	printf("%s:\n", tbl->name);
142 	for (n = 0; n < tbl->nevents; n++) {
143 		printf("\t%s\n", tbl->events[n].name);
144 	}
145 
146 	if (tbl->next)
147 		tprof_event_list_table(tbl->next);
148 }
149 
150 void
tprof_event_list(void)151 tprof_event_list(void)
152 {
153 	tprof_event_list_table(events);
154 }
155 
156 static void
tprof_event_lookup_table(const char * name,struct tprof_param * param,struct pmu_event_table * tbl)157 tprof_event_lookup_table(const char *name, struct tprof_param *param,
158     struct pmu_event_table *tbl)
159 {
160 	u_int n;
161 
162 	for (n = 0; n < tbl->nevents; n++) {
163 		if (strcmp(tbl->events[n].name, name) == 0) {
164 			param->p_event = tbl->events[n].event;
165 			param->p_unit = 0;
166 			return;
167 		}
168 	}
169 
170 	if (tbl->next)
171 		tprof_event_lookup_table(name, param, tbl->next);
172 	else
173 		errx(EXIT_FAILURE, "event '%s' unknown", name);
174 }
175 
176 void
tprof_event_lookup(const char * name,struct tprof_param * param)177 tprof_event_lookup(const char *name, struct tprof_param *param)
178 {
179 	tprof_event_lookup_table(name, param, events);
180 }
181