1 /* $NetBSD: motg.c,v 1.43 2024/04/05 18:57:10 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net) at
9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill@invisible.ca),
10 * Matthew R. Green (mrg@eterna23.net), and Manuel Bouyer (bouyer@netbsd.org).
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34
35 /*
36 * This file contains the driver for the Mentor Graphics Inventra USB
37 * 2.0 High Speed Dual-Role controller.
38 *
39 * NOTE: The current implementation only supports Device Side Mode!
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.43 2024/04/05 18:57:10 riastradh Exp $");
44
45 #ifdef _KERNEL_OPT
46 #include "opt_usb.h"
47 #endif
48
49 #include <sys/param.h>
50
51 #include <sys/bus.h>
52 #include <sys/cpu.h>
53 #include <sys/device.h>
54 #include <sys/kernel.h>
55 #include <sys/kmem.h>
56 #include <sys/proc.h>
57 #include <sys/queue.h>
58 #include <sys/select.h>
59 #include <sys/sysctl.h>
60 #include <sys/systm.h>
61
62 #include <machine/endian.h>
63
64 #include <dev/usb/usb.h>
65 #include <dev/usb/usbdi.h>
66 #include <dev/usb/usbdivar.h>
67 #include <dev/usb/usb_mem.h>
68 #include <dev/usb/usbhist.h>
69
70 #include <dev/usb/motgreg.h>
71 #include <dev/usb/motgvar.h>
72 #include <dev/usb/usbroothub.h>
73
74 #ifdef USB_DEBUG
75 #ifndef MOTG_DEBUG
76 #define motgdebug 0
77 #else
78 int motgdebug = 0;
79
80 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup")
81 {
82 int err;
83 const struct sysctlnode *rnode;
84 const struct sysctlnode *cnode;
85
86 err = sysctl_createv(clog, 0, NULL, &rnode,
87 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg",
88 SYSCTL_DESCR("motg global controls"),
89 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
90
91 if (err)
92 goto fail;
93
94 /* control debugging printfs */
95 err = sysctl_createv(clog, 0, &rnode, &cnode,
96 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
97 "debug", SYSCTL_DESCR("Enable debugging output"),
98 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL);
99 if (err)
100 goto fail;
101
102 return;
103 fail:
104 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
105 }
106
107 #endif /* MOTG_DEBUG */
108 #endif /* USB_DEBUG */
109
110 #define MD_ROOT 0x0002
111 #define MD_CTRL 0x0004
112 #define MD_BULK 0x0008
113
114 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D)
115 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D)
116 #define MOTGHIST_FUNC() USBHIST_FUNC()
117 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug)
118
119
120 /* various timeouts, for various speeds */
121 /* control NAK timeouts */
122 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */
123 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */
124
125 /* intr/iso polling intervals */
126 #define POLL_TO 100 /* 100 frames, about 0.1s */
127 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */
128
129 /* bulk NAK timeouts */
130 #define NAK_TO_BULK 0 /* disabled */
131 #define NAK_TO_BULK_HIGH 0
132
133 static void motg_hub_change(struct motg_softc *);
134
135 static usbd_status motg_root_intr_transfer(struct usbd_xfer *);
136 static usbd_status motg_root_intr_start(struct usbd_xfer *);
137 static void motg_root_intr_abort(struct usbd_xfer *);
138 static void motg_root_intr_close(struct usbd_pipe *);
139 static void motg_root_intr_done(struct usbd_xfer *);
140
141 static usbd_status motg_open(struct usbd_pipe *);
142 static void motg_poll(struct usbd_bus *);
143 static void motg_softintr(void *);
144 static struct usbd_xfer *
145 motg_allocx(struct usbd_bus *, unsigned int);
146 static void motg_freex(struct usbd_bus *, struct usbd_xfer *);
147 static bool motg_dying(struct usbd_bus *);
148 static void motg_get_lock(struct usbd_bus *, kmutex_t **);
149 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *,
150 void *, int);
151
152 static void motg_noop(struct usbd_pipe *pipe);
153 static usbd_status motg_portreset(struct motg_softc*);
154
155 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *);
156 static usbd_status motg_device_ctrl_start(struct usbd_xfer *);
157 static void motg_device_ctrl_abort(struct usbd_xfer *);
158 static void motg_device_ctrl_close(struct usbd_pipe *);
159 static void motg_device_ctrl_done(struct usbd_xfer *);
160 static usbd_status motg_device_ctrl_start1(struct motg_softc *);
161 static void motg_device_ctrl_read(struct usbd_xfer *);
162 static void motg_device_ctrl_intr_rx(struct motg_softc *);
163 static void motg_device_ctrl_intr_tx(struct motg_softc *);
164
165 static usbd_status motg_device_data_transfer(struct usbd_xfer *);
166 static usbd_status motg_device_data_start(struct usbd_xfer *);
167 static usbd_status motg_device_data_start1(struct motg_softc *,
168 struct motg_hw_ep *);
169 static void motg_device_data_abort(struct usbd_xfer *);
170 static void motg_device_data_close(struct usbd_pipe *);
171 static void motg_device_data_done(struct usbd_xfer *);
172 static void motg_device_intr_rx(struct motg_softc *, int);
173 static void motg_device_intr_tx(struct motg_softc *, int);
174 static void motg_device_data_read(struct usbd_xfer *);
175 static void motg_device_data_write(struct usbd_xfer *);
176
177 static void motg_device_clear_toggle(struct usbd_pipe *);
178 static void motg_abortx(struct usbd_xfer *);
179
180 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \
181 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
182 #define UWRITE1(sc, r, x) \
183 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \
184 } while (/*CONSTCOND*/0)
185 #define UWRITE2(sc, r, x) \
186 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \
187 } while (/*CONSTCOND*/0)
188 #define UWRITE4(sc, r, x) \
189 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \
190 } while (/*CONSTCOND*/0)
191
192 static __inline uint32_t
UREAD1(struct motg_softc * sc,bus_size_t r)193 UREAD1(struct motg_softc *sc, bus_size_t r)
194 {
195
196 UBARR(sc);
197 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r);
198 }
199 static __inline uint32_t
UREAD2(struct motg_softc * sc,bus_size_t r)200 UREAD2(struct motg_softc *sc, bus_size_t r)
201 {
202
203 UBARR(sc);
204 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r);
205 }
206
207 #if 0
208 static __inline uint32_t
209 UREAD4(struct motg_softc *sc, bus_size_t r)
210 {
211
212 UBARR(sc);
213 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r);
214 }
215 #endif
216
217 static void
musbotg_pull_common(struct motg_softc * sc,uint8_t on)218 musbotg_pull_common(struct motg_softc *sc, uint8_t on)
219 {
220 uint8_t val;
221
222 val = UREAD1(sc, MUSB2_REG_POWER);
223 if (on)
224 val |= MUSB2_MASK_SOFTC;
225 else
226 val &= ~MUSB2_MASK_SOFTC;
227
228 UWRITE1(sc, MUSB2_REG_POWER, val);
229 }
230
231 const struct usbd_bus_methods motg_bus_methods = {
232 .ubm_open = motg_open,
233 .ubm_softint = motg_softintr,
234 .ubm_dopoll = motg_poll,
235 .ubm_allocx = motg_allocx,
236 .ubm_freex = motg_freex,
237 .ubm_abortx = motg_abortx,
238 .ubm_dying = motg_dying,
239 .ubm_getlock = motg_get_lock,
240 .ubm_rhctrl = motg_roothub_ctrl,
241 };
242
243 const struct usbd_pipe_methods motg_root_intr_methods = {
244 .upm_transfer = motg_root_intr_transfer,
245 .upm_start = motg_root_intr_start,
246 .upm_abort = motg_root_intr_abort,
247 .upm_close = motg_root_intr_close,
248 .upm_cleartoggle = motg_noop,
249 .upm_done = motg_root_intr_done,
250 };
251
252 const struct usbd_pipe_methods motg_device_ctrl_methods = {
253 .upm_transfer = motg_device_ctrl_transfer,
254 .upm_start = motg_device_ctrl_start,
255 .upm_abort = motg_device_ctrl_abort,
256 .upm_close = motg_device_ctrl_close,
257 .upm_cleartoggle = motg_noop,
258 .upm_done = motg_device_ctrl_done,
259 };
260
261 const struct usbd_pipe_methods motg_device_data_methods = {
262 .upm_transfer = motg_device_data_transfer,
263 .upm_start = motg_device_data_start,
264 .upm_abort = motg_device_data_abort,
265 .upm_close = motg_device_data_close,
266 .upm_cleartoggle = motg_device_clear_toggle,
267 .upm_done = motg_device_data_done,
268 };
269
270 int
motg_init(struct motg_softc * sc)271 motg_init(struct motg_softc *sc)
272 {
273 uint32_t nrx, ntx, val;
274 int dynfifo;
275 int offset, i;
276
277 MOTGHIST_FUNC(); MOTGHIST_CALLED();
278
279 if (sc->sc_mode == MOTG_MODE_DEVICE)
280 return ENOTSUP; /* not supported */
281
282 /* disable all interrupts */
283 UWRITE1(sc, MUSB2_REG_INTUSBE, 0);
284 UWRITE2(sc, MUSB2_REG_INTTXE, 0);
285 UWRITE2(sc, MUSB2_REG_INTRXE, 0);
286 /* disable pullup */
287
288 musbotg_pull_common(sc, 0);
289
290 #ifdef MUSB2_REG_RXDBDIS
291 /* disable double packet buffering XXX what's this ? */
292 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
293 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
294 #endif
295
296 /* enable HighSpeed and ISO Update flags */
297
298 UWRITE1(sc, MUSB2_REG_POWER,
299 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
300
301 if (sc->sc_mode == MOTG_MODE_DEVICE) {
302 /* clear Session bit, if set */
303 val = UREAD1(sc, MUSB2_REG_DEVCTL);
304 val &= ~MUSB2_MASK_SESS;
305 UWRITE1(sc, MUSB2_REG_DEVCTL, val);
306 } else {
307 /* Enter session for Host mode */
308 val = UREAD1(sc, MUSB2_REG_DEVCTL);
309 val |= MUSB2_MASK_SESS;
310 UWRITE1(sc, MUSB2_REG_DEVCTL, val);
311 }
312 delay(1000);
313 DPRINTF("DEVCTL %#jx", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0);
314
315 /* disable testmode */
316
317 UWRITE1(sc, MUSB2_REG_TESTMODE, 0);
318
319 #ifdef MUSB2_REG_MISC
320 /* set default value */
321
322 UWRITE1(sc, MUSB2_REG_MISC, 0);
323 #endif
324
325 /* select endpoint index 0 */
326
327 UWRITE1(sc, MUSB2_REG_EPINDEX, 0);
328
329 if (sc->sc_ep_max == 0) {
330 /* read out number of endpoints */
331 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16);
332
333 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16);
334
335 /* these numbers exclude the control endpoint */
336
337 DPRINTFN(1,"RX/TX endpoints: %ju/%ju", nrx, ntx, 0, 0);
338
339 sc->sc_ep_max = MAX(nrx, ntx);
340 } else {
341 nrx = ntx = sc->sc_ep_max;
342 }
343 if (sc->sc_ep_max == 0) {
344 aprint_error_dev(sc->sc_dev, " no endpoints\n");
345 return -1;
346 }
347 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP);
348 /* read out configuration data */
349 val = UREAD1(sc, MUSB2_REG_CONFDATA);
350
351 DPRINTF("Config Data: 0x%02jx", val, 0, 0, 0);
352
353 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
354
355 if (dynfifo) {
356 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, "
357 "assuming 16Kbytes of FIFO RAM\n");
358 }
359
360 DPRINTF("HW version: 0x%04jx\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0);
361
362 /* initialise endpoint profiles */
363 sc->sc_in_ep[0].ep_fifo_size = 64;
364 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */
365 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0;
366 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes);
367 offset = 64;
368
369 for (i = 1; i <= sc->sc_ep_max; i++) {
370 int fiforx_size, fifotx_size, fifo_size;
371
372 /* select endpoint */
373 UWRITE1(sc, MUSB2_REG_EPINDEX, i);
374
375 if (sc->sc_ep_fifosize) {
376 fiforx_size = fifotx_size = sc->sc_ep_fifosize;
377 } else {
378 val = UREAD1(sc, MUSB2_REG_FSIZE);
379 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4;
380 fifotx_size = (val & MUSB2_MASK_TX_FSIZE);
381 }
382
383 DPRINTF("Endpoint %ju FIFO size: IN=%ju, OUT=%ju, DYN=%jd",
384 i, fifotx_size, fiforx_size, dynfifo);
385
386 if (dynfifo) {
387 if (sc->sc_ep_fifosize) {
388 fifo_size = ffs(sc->sc_ep_fifosize) - 1;
389 } else {
390 if (i < 3) {
391 fifo_size = 12; /* 4K */
392 } else if (i < 10) {
393 fifo_size = 10; /* 1K */
394 } else {
395 fifo_size = 7; /* 128 bytes */
396 }
397 }
398 if (fiforx_size && (i <= nrx)) {
399 fiforx_size = fifo_size;
400 if (fifo_size > 7) {
401 #if 0
402 UWRITE1(sc, MUSB2_REG_RXFIFOSZ,
403 MUSB2_VAL_FIFOSZ(fifo_size) |
404 MUSB2_MASK_FIFODB);
405 #else
406 UWRITE1(sc, MUSB2_REG_RXFIFOSZ,
407 MUSB2_VAL_FIFOSZ(fifo_size));
408 #endif
409 } else {
410 UWRITE1(sc, MUSB2_REG_RXFIFOSZ,
411 MUSB2_VAL_FIFOSZ(fifo_size));
412 }
413 UWRITE2(sc, MUSB2_REG_RXFIFOADD,
414 offset >> 3);
415 offset += (1 << fiforx_size);
416 }
417 if (fifotx_size && (i <= ntx)) {
418 fifotx_size = fifo_size;
419 if (fifo_size > 7) {
420 #if 0
421 UWRITE1(sc, MUSB2_REG_TXFIFOSZ,
422 MUSB2_VAL_FIFOSZ(fifo_size) |
423 MUSB2_MASK_FIFODB);
424 #else
425 UWRITE1(sc, MUSB2_REG_TXFIFOSZ,
426 MUSB2_VAL_FIFOSZ(fifo_size));
427 #endif
428 } else {
429 UWRITE1(sc, MUSB2_REG_TXFIFOSZ,
430 MUSB2_VAL_FIFOSZ(fifo_size));
431 }
432
433 UWRITE2(sc, MUSB2_REG_TXFIFOADD,
434 offset >> 3);
435
436 offset += (1 << fifotx_size);
437 }
438 }
439 if (fiforx_size && (i <= nrx)) {
440 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size);
441 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes);
442 }
443 if (fifotx_size && (i <= ntx)) {
444 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size);
445 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes);
446 }
447 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i;
448 }
449
450
451 DPRINTF("Dynamic FIFO size = %jd bytes", offset, 0, 0, 0);
452
453 /* turn on default interrupts */
454
455 if (sc->sc_mode == MOTG_MODE_HOST) {
456 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff);
457 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff);
458 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff);
459 } else
460 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET);
461
462 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0,
463 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL);
464
465 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
466 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
467
468 /* Set up the bus struct. */
469 sc->sc_bus.ub_methods = &motg_bus_methods;
470 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe);
471 sc->sc_bus.ub_revision = USBREV_2_0;
472 sc->sc_bus.ub_usedma = false;
473 sc->sc_bus.ub_hcpriv = sc;
474 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint,
475 CFARGS_NONE);
476 return 0;
477 }
478
479 static int
motg_select_ep(struct motg_softc * sc,struct usbd_pipe * pipe)480 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe)
481 {
482 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe);
483 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
484 struct motg_hw_ep *ep;
485 int i, size;
486
487 MOTGHIST_FUNC(); MOTGHIST_CALLED();
488
489 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ?
490 sc->sc_in_ep : sc->sc_out_ep;
491 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize));
492
493 for (i = sc->sc_ep_max; i >= 1; i--) {
494 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ?
495 "in_ep[%jd].ep_fifo_size %jd size %jd ref %jd" :
496 "out_ep[%jd].ep_fifo_size %jd size %jd ref %jd", i,
497 ep[i].ep_fifo_size, size, ep[i].refcount);
498 if (ep[i].ep_fifo_size >= size) {
499 /* found a suitable endpoint */
500 otgpipe->hw_ep = &ep[i];
501 mutex_enter(&sc->sc_lock);
502 if (otgpipe->hw_ep->refcount > 0) {
503 /* no luck, try next */
504 mutex_exit(&sc->sc_lock);
505 otgpipe->hw_ep = NULL;
506 } else {
507 otgpipe->hw_ep->refcount++;
508 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes,
509 otgpipe, ep_pipe_list);
510 mutex_exit(&sc->sc_lock);
511 return 0;
512 }
513 }
514 }
515 return -1;
516 }
517
518 /* Open a new pipe. */
519 usbd_status
motg_open(struct usbd_pipe * pipe)520 motg_open(struct usbd_pipe *pipe)
521 {
522 struct motg_softc *sc = MOTG_PIPE2SC(pipe);
523 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe);
524 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
525 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr;
526
527 MOTGHIST_FUNC(); MOTGHIST_CALLED();
528
529 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe,
530 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr);
531
532 if (sc->sc_dying)
533 return USBD_IOERROR;
534
535 /* toggle state needed for bulk endpoints */
536 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle;
537
538 if (pipe->up_dev->ud_addr == rhaddr) {
539 switch (ed->bEndpointAddress) {
540 case USB_CONTROL_ENDPOINT:
541 pipe->up_methods = &roothub_ctrl_methods;
542 break;
543 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
544 pipe->up_methods = &motg_root_intr_methods;
545 break;
546 default:
547 return USBD_INVAL;
548 }
549 } else {
550 switch (ed->bmAttributes & UE_XFERTYPE) {
551 case UE_CONTROL:
552 pipe->up_methods = &motg_device_ctrl_methods;
553 /* always use sc_in_ep[0] for in and out */
554 otgpipe->hw_ep = &sc->sc_in_ep[0];
555 mutex_enter(&sc->sc_lock);
556 otgpipe->hw_ep->refcount++;
557 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes,
558 otgpipe, ep_pipe_list);
559 mutex_exit(&sc->sc_lock);
560 break;
561 case UE_BULK:
562 case UE_INTERRUPT:
563 DPRINTFN(MD_BULK,
564 "type %jd dir %jd pipe wMaxPacketSize %jd",
565 UE_GET_XFERTYPE(ed->bmAttributes),
566 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress),
567 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0);
568 if (motg_select_ep(sc, pipe) != 0)
569 goto bad;
570 KASSERT(otgpipe->hw_ep != NULL);
571 pipe->up_methods = &motg_device_data_methods;
572 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle;
573 break;
574 default:
575 goto bad;
576 #ifdef notyet
577 case UE_ISOCHRONOUS:
578 ...
579 break;
580 #endif /* notyet */
581 }
582 }
583 return USBD_NORMAL_COMPLETION;
584
585 bad:
586 return USBD_NOMEM;
587 }
588
589 void
motg_softintr(void * v)590 motg_softintr(void *v)
591 {
592 struct usbd_bus *bus = v;
593 struct motg_softc *sc = MOTG_BUS2SC(bus);
594 uint16_t rx_status, tx_status;
595 uint8_t ctrl_status;
596 uint32_t val;
597 int i;
598
599 MOTGHIST_FUNC(); MOTGHIST_CALLED();
600
601 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
602
603 DPRINTFN(MD_ROOT | MD_CTRL, "sc %#jx", (uintptr_t)sc, 0 ,0 ,0);
604
605 mutex_spin_enter(&sc->sc_intr_lock);
606 rx_status = sc->sc_intr_rx_ep;
607 sc->sc_intr_rx_ep = 0;
608 tx_status = sc->sc_intr_tx_ep;
609 sc->sc_intr_tx_ep = 0;
610 ctrl_status = sc->sc_intr_ctrl;
611 sc->sc_intr_ctrl = 0;
612 mutex_spin_exit(&sc->sc_intr_lock);
613
614 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB);
615
616 if (ctrl_status & (MUSB2_MASK_IRESET |
617 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
618 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) {
619 DPRINTFN(MD_ROOT | MD_CTRL, "bus %#jx", ctrl_status, 0, 0, 0);
620
621 if (ctrl_status & MUSB2_MASK_IRESET) {
622 sc->sc_isreset = 1;
623 sc->sc_port_suspended = 0;
624 sc->sc_port_suspended_change = 1;
625 sc->sc_connected_changed = 1;
626 sc->sc_port_enabled = 1;
627
628 val = UREAD1(sc, MUSB2_REG_POWER);
629 if (val & MUSB2_MASK_HSMODE)
630 sc->sc_high_speed = 1;
631 else
632 sc->sc_high_speed = 0;
633 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed,
634 0, 0, 0);
635
636 /* turn off interrupts */
637 val = MUSB2_MASK_IRESET;
638 val &= ~MUSB2_MASK_IRESUME;
639 val |= MUSB2_MASK_ISUSP;
640 UWRITE1(sc, MUSB2_REG_INTUSBE, val);
641 UWRITE2(sc, MUSB2_REG_INTTXE, 0);
642 UWRITE2(sc, MUSB2_REG_INTRXE, 0);
643 }
644 if (ctrl_status & MUSB2_MASK_IRESUME) {
645 if (sc->sc_port_suspended) {
646 sc->sc_port_suspended = 0;
647 sc->sc_port_suspended_change = 1;
648 val = UREAD1(sc, MUSB2_REG_INTUSBE);
649 /* disable resume interrupt */
650 val &= ~MUSB2_MASK_IRESUME;
651 /* enable suspend interrupt */
652 val |= MUSB2_MASK_ISUSP;
653 UWRITE1(sc, MUSB2_REG_INTUSBE, val);
654 }
655 } else if (ctrl_status & MUSB2_MASK_ISUSP) {
656 if (!sc->sc_port_suspended) {
657 sc->sc_port_suspended = 1;
658 sc->sc_port_suspended_change = 1;
659
660 val = UREAD1(sc, MUSB2_REG_INTUSBE);
661 /* disable suspend interrupt */
662 val &= ~MUSB2_MASK_ISUSP;
663 /* enable resume interrupt */
664 val |= MUSB2_MASK_IRESUME;
665 UWRITE1(sc, MUSB2_REG_INTUSBE, val);
666 }
667 }
668 if (ctrl_status & MUSB2_MASK_ICONN) {
669 sc->sc_connected = 1;
670 sc->sc_connected_changed = 1;
671 sc->sc_isreset = 1;
672 sc->sc_port_enabled = 1;
673 } else if (ctrl_status & MUSB2_MASK_IDISC) {
674 sc->sc_connected = 0;
675 sc->sc_connected_changed = 1;
676 sc->sc_isreset = 0;
677 sc->sc_port_enabled = 0;
678 }
679
680 /* complete root HUB interrupt endpoint */
681
682 motg_hub_change(sc);
683 }
684 /*
685 * read in interrupt status and mix with the status we
686 * got from the wrapper
687 */
688 rx_status |= UREAD2(sc, MUSB2_REG_INTRX);
689 tx_status |= UREAD2(sc, MUSB2_REG_INTTX);
690
691 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status);
692 if (tx_status & 0x01)
693 motg_device_ctrl_intr_tx(sc);
694 for (i = 1; i <= sc->sc_ep_max; i++) {
695 if (rx_status & (0x01 << i))
696 motg_device_intr_rx(sc, i);
697 if (tx_status & (0x01 << i))
698 motg_device_intr_tx(sc, i);
699 }
700 return;
701 }
702
703 void
motg_poll(struct usbd_bus * bus)704 motg_poll(struct usbd_bus *bus)
705 {
706 struct motg_softc *sc = MOTG_BUS2SC(bus);
707
708 sc->sc_intr_poll(sc->sc_intr_poll_arg);
709 mutex_enter(&sc->sc_lock);
710 motg_softintr(bus);
711 mutex_exit(&sc->sc_lock);
712 }
713
714 int
motg_intr(struct motg_softc * sc,uint16_t rx_ep,uint16_t tx_ep,uint8_t ctrl)715 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep,
716 uint8_t ctrl)
717 {
718 KASSERT(mutex_owned(&sc->sc_intr_lock));
719 sc->sc_intr_tx_ep = tx_ep;
720 sc->sc_intr_rx_ep = rx_ep;
721 sc->sc_intr_ctrl = ctrl;
722
723 if (!sc->sc_bus.ub_usepolling) {
724 usb_schedsoftintr(&sc->sc_bus);
725 }
726 return 1;
727 }
728
729 int
motg_intr_vbus(struct motg_softc * sc,int vbus)730 motg_intr_vbus(struct motg_softc *sc, int vbus)
731 {
732 uint8_t val;
733 MOTGHIST_FUNC(); MOTGHIST_CALLED();
734
735 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) {
736 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0);
737 /* try to re-enter session for Host mode */
738 val = UREAD1(sc, MUSB2_REG_DEVCTL);
739 val |= MUSB2_MASK_SESS;
740 UWRITE1(sc, MUSB2_REG_DEVCTL, val);
741 }
742 return 1;
743 }
744
745 struct usbd_xfer *
motg_allocx(struct usbd_bus * bus,unsigned int nframes)746 motg_allocx(struct usbd_bus *bus, unsigned int nframes)
747 {
748 struct motg_softc *sc = MOTG_BUS2SC(bus);
749 struct usbd_xfer *xfer;
750
751 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
752 if (xfer != NULL) {
753 memset(xfer, 0, sizeof(struct motg_xfer));
754 #ifdef DIAGNOSTIC
755 xfer->ux_state = XFER_BUSY;
756 #endif
757 }
758 return xfer;
759 }
760
761 void
motg_freex(struct usbd_bus * bus,struct usbd_xfer * xfer)762 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
763 {
764 struct motg_softc *sc = MOTG_BUS2SC(bus);
765
766 #ifdef DIAGNOSTIC
767 if (xfer->ux_state != XFER_BUSY &&
768 xfer->ux_status != USBD_NOT_STARTED) {
769 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer,
770 xfer->ux_state);
771 }
772 xfer->ux_state = XFER_FREE;
773 #endif
774 pool_cache_put(sc->sc_xferpool, xfer);
775 }
776
777 static bool
motg_dying(struct usbd_bus * bus)778 motg_dying(struct usbd_bus *bus)
779 {
780 struct motg_softc *sc = MOTG_BUS2SC(bus);
781
782 return sc->sc_dying;
783 }
784
785 static void
motg_get_lock(struct usbd_bus * bus,kmutex_t ** lock)786 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock)
787 {
788 struct motg_softc *sc = MOTG_BUS2SC(bus);
789
790 *lock = &sc->sc_lock;
791 }
792
793 /*
794 * Routines to emulate the root hub.
795 */
796 Static int
motg_roothub_ctrl(struct usbd_bus * bus,usb_device_request_t * req,void * buf,int buflen)797 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
798 void *buf, int buflen)
799 {
800 struct motg_softc *sc = MOTG_BUS2SC(bus);
801 int status, change, totlen = 0;
802 uint16_t len, value, index;
803 usb_port_status_t ps;
804 usbd_status err;
805 uint32_t val;
806
807 MOTGHIST_FUNC(); MOTGHIST_CALLED();
808
809 if (sc->sc_dying)
810 return -1;
811
812 DPRINTFN(MD_ROOT, "type=0x%02jx request=%02jx", req->bmRequestType,
813 req->bRequest, 0, 0);
814
815 len = UGETW(req->wLength);
816 value = UGETW(req->wValue);
817 index = UGETW(req->wIndex);
818
819 #define C(x,y) ((x) | ((y) << 8))
820 switch (C(req->bRequest, req->bmRequestType)) {
821 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
822 DPRINTFN(MD_ROOT, "wValue=0x%04jx", value, 0, 0, 0);
823 switch (value) {
824 #define sd ((usb_string_descriptor_t *)buf)
825 case C(2, UDESC_STRING):
826 /* Product */
827 totlen = usb_makestrdesc(sd, len, "MOTG root hub");
828 break;
829 #undef sd
830 default:
831 /* default from usbroothub */
832 return buflen;
833 }
834 break;
835 /* Hub requests */
836 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
837 break;
838 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
839 DPRINTFN(MD_ROOT,
840 "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, value,
841 0, 0);
842 if (index != 1) {
843 return -1;
844 }
845 switch (value) {
846 case UHF_PORT_ENABLE:
847 sc->sc_port_enabled = 0;
848 break;
849 case UHF_PORT_SUSPEND:
850 if (sc->sc_port_suspended != 0) {
851 val = UREAD1(sc, MUSB2_REG_POWER);
852 val &= ~MUSB2_MASK_SUSPMODE;
853 val |= MUSB2_MASK_RESUME;
854 UWRITE1(sc, MUSB2_REG_POWER, val);
855 /* wait 20 milliseconds */
856 usb_delay_ms(&sc->sc_bus, 20);
857 val = UREAD1(sc, MUSB2_REG_POWER);
858 val &= ~MUSB2_MASK_RESUME;
859 UWRITE1(sc, MUSB2_REG_POWER, val);
860 sc->sc_port_suspended = 0;
861 sc->sc_port_suspended_change = 1;
862 }
863 break;
864 case UHF_PORT_RESET:
865 break;
866 case UHF_C_PORT_CONNECTION:
867 break;
868 case UHF_C_PORT_ENABLE:
869 break;
870 case UHF_C_PORT_OVER_CURRENT:
871 break;
872 case UHF_C_PORT_RESET:
873 sc->sc_isreset = 0;
874 break;
875 case UHF_PORT_POWER:
876 /* XXX todo */
877 break;
878 case UHF_PORT_CONNECTION:
879 case UHF_PORT_OVER_CURRENT:
880 case UHF_PORT_LOW_SPEED:
881 case UHF_C_PORT_SUSPEND:
882 default:
883 return -1;
884 }
885 break;
886 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
887 return -1;
888 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
889 if (len == 0)
890 break;
891 if ((value & 0xff) != 0) {
892 return -1;
893 }
894 totlen = buflen;
895 break;
896 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
897 if (len != 4) {
898 return -1;
899 }
900 memset(buf, 0, len);
901 totlen = len;
902 break;
903 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
904 if (index != 1) {
905 return -1;
906 }
907 if (len != 4) {
908 return -1;
909 }
910 status = change = 0;
911 if (sc->sc_connected)
912 status |= UPS_CURRENT_CONNECT_STATUS;
913 if (sc->sc_connected_changed) {
914 change |= UPS_C_CONNECT_STATUS;
915 sc->sc_connected_changed = 0;
916 }
917 if (sc->sc_port_enabled)
918 status |= UPS_PORT_ENABLED;
919 if (sc->sc_port_enabled_changed) {
920 change |= UPS_C_PORT_ENABLED;
921 sc->sc_port_enabled_changed = 0;
922 }
923 if (sc->sc_port_suspended)
924 status |= UPS_SUSPEND;
925 if (sc->sc_high_speed)
926 status |= UPS_HIGH_SPEED;
927 status |= UPS_PORT_POWER; /* XXX */
928 if (sc->sc_isreset)
929 change |= UPS_C_PORT_RESET;
930 USETW(ps.wPortStatus, status);
931 USETW(ps.wPortChange, change);
932 totlen = uimin(len, sizeof(ps));
933 memcpy(buf, &ps, totlen);
934 break;
935 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
936 return -1;
937 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
938 break;
939 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
940 if (index != 1) {
941 return -1;
942 }
943 switch(value) {
944 case UHF_PORT_ENABLE:
945 sc->sc_port_enabled = 1;
946 break;
947 case UHF_PORT_SUSPEND:
948 if (sc->sc_port_suspended == 0) {
949 val = UREAD1(sc, MUSB2_REG_POWER);
950 val |= MUSB2_MASK_SUSPMODE;
951 UWRITE1(sc, MUSB2_REG_POWER, val);
952 /* wait 20 milliseconds */
953 usb_delay_ms(&sc->sc_bus, 20);
954 sc->sc_port_suspended = 1;
955 sc->sc_port_suspended_change = 1;
956 }
957 break;
958 case UHF_PORT_RESET:
959 err = motg_portreset(sc);
960 if (err != USBD_NORMAL_COMPLETION)
961 return -1;
962 return 0;
963 case UHF_PORT_POWER:
964 /* XXX todo */
965 return 0;
966 case UHF_C_PORT_CONNECTION:
967 case UHF_C_PORT_ENABLE:
968 case UHF_C_PORT_OVER_CURRENT:
969 case UHF_PORT_CONNECTION:
970 case UHF_PORT_OVER_CURRENT:
971 case UHF_PORT_LOW_SPEED:
972 case UHF_C_PORT_SUSPEND:
973 case UHF_C_PORT_RESET:
974 default:
975 return -1;
976 }
977 break;
978 default:
979 /* default from usbroothub */
980 return buflen;
981 }
982
983 return totlen;
984 }
985
986 /* Abort a root interrupt request. */
987 void
motg_root_intr_abort(struct usbd_xfer * xfer)988 motg_root_intr_abort(struct usbd_xfer *xfer)
989 {
990 struct motg_softc *sc = MOTG_XFER2SC(xfer);
991
992 KASSERT(mutex_owned(&sc->sc_lock));
993 KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
994
995 /* If xfer has already completed, nothing to do here. */
996 if (sc->sc_intr_xfer == NULL)
997 return;
998
999 /*
1000 * Otherwise, sc->sc_intr_xfer had better be this transfer.
1001 * Cancel it.
1002 */
1003 KASSERT(sc->sc_intr_xfer == xfer);
1004 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
1005 xfer->ux_status = USBD_CANCELLED;
1006 usb_transfer_complete(xfer);
1007 }
1008
1009 usbd_status
motg_root_intr_transfer(struct usbd_xfer * xfer)1010 motg_root_intr_transfer(struct usbd_xfer *xfer)
1011 {
1012
1013 /* Pipe isn't running, start first */
1014 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1015 }
1016
1017 /* Start a transfer on the root interrupt pipe */
1018 usbd_status
motg_root_intr_start(struct usbd_xfer * xfer)1019 motg_root_intr_start(struct usbd_xfer *xfer)
1020 {
1021 struct usbd_pipe *pipe = xfer->ux_pipe;
1022 struct motg_softc *sc = MOTG_PIPE2SC(pipe);
1023
1024 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1025
1026 DPRINTFN(MD_ROOT, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer,
1027 xfer->ux_length, xfer->ux_flags, 0);
1028
1029 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1030
1031 if (sc->sc_dying)
1032 return USBD_IOERROR;
1033
1034 KASSERT(sc->sc_intr_xfer == NULL);
1035 sc->sc_intr_xfer = xfer;
1036 xfer->ux_status = USBD_IN_PROGRESS;
1037
1038 return USBD_IN_PROGRESS;
1039 }
1040
1041 /* Close the root interrupt pipe. */
1042 void
motg_root_intr_close(struct usbd_pipe * pipe)1043 motg_root_intr_close(struct usbd_pipe *pipe)
1044 {
1045 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe);
1046 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1047
1048 KASSERT(mutex_owned(&sc->sc_lock));
1049
1050 /*
1051 * Caller must guarantee the xfer has completed first, by
1052 * closing the pipe only after normal completion or an abort.
1053 */
1054 KASSERT(sc->sc_intr_xfer == NULL);
1055 }
1056
1057 void
motg_root_intr_done(struct usbd_xfer * xfer)1058 motg_root_intr_done(struct usbd_xfer *xfer)
1059 {
1060 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1061 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1062
1063 KASSERT(mutex_owned(&sc->sc_lock));
1064
1065 /* Claim the xfer so it doesn't get completed again. */
1066 KASSERT(sc->sc_intr_xfer == xfer);
1067 KASSERT(xfer->ux_status != USBD_IN_PROGRESS);
1068 sc->sc_intr_xfer = NULL;
1069 }
1070
1071 void
motg_noop(struct usbd_pipe * pipe)1072 motg_noop(struct usbd_pipe *pipe)
1073 {
1074 }
1075
1076 static usbd_status
motg_portreset(struct motg_softc * sc)1077 motg_portreset(struct motg_softc *sc)
1078 {
1079 uint32_t val;
1080 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1081
1082 val = UREAD1(sc, MUSB2_REG_POWER);
1083 val |= MUSB2_MASK_RESET;
1084 UWRITE1(sc, MUSB2_REG_POWER, val);
1085 /* Wait for 20 msec */
1086 usb_delay_ms(&sc->sc_bus, 20);
1087
1088 val = UREAD1(sc, MUSB2_REG_POWER);
1089 val &= ~MUSB2_MASK_RESET;
1090 UWRITE1(sc, MUSB2_REG_POWER, val);
1091
1092 /* determine line speed */
1093 val = UREAD1(sc, MUSB2_REG_POWER);
1094 if (val & MUSB2_MASK_HSMODE)
1095 sc->sc_high_speed = 1;
1096 else
1097 sc->sc_high_speed = 0;
1098 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 0, 0, 0);
1099
1100 sc->sc_isreset = 1;
1101 sc->sc_port_enabled = 1;
1102 return USBD_NORMAL_COMPLETION;
1103 }
1104
1105 /*
1106 * This routine is executed when an interrupt on the root hub is detected
1107 */
1108 static void
motg_hub_change(struct motg_softc * sc)1109 motg_hub_change(struct motg_softc *sc)
1110 {
1111 struct usbd_xfer *xfer = sc->sc_intr_xfer;
1112 struct usbd_pipe *pipe;
1113 u_char *p;
1114
1115 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1116
1117 if (xfer == NULL)
1118 return; /* the interrupt pipe is not open */
1119 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
1120
1121 pipe = xfer->ux_pipe;
1122 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)
1123 return; /* device has detached */
1124
1125 p = xfer->ux_buf;
1126 p[0] = 1<<1;
1127 xfer->ux_actlen = 1;
1128 xfer->ux_status = USBD_NORMAL_COMPLETION;
1129 usb_transfer_complete(xfer);
1130 }
1131
1132 static uint8_t
motg_speed(uint8_t speed)1133 motg_speed(uint8_t speed)
1134 {
1135 switch(speed) {
1136 case USB_SPEED_LOW:
1137 return MUSB2_MASK_TI_SPEED_LO;
1138 case USB_SPEED_FULL:
1139 return MUSB2_MASK_TI_SPEED_FS;
1140 case USB_SPEED_HIGH:
1141 return MUSB2_MASK_TI_SPEED_HS;
1142 default:
1143 panic("motg: unknown speed %d", speed);
1144 /* NOTREACHED */
1145 }
1146 }
1147
1148 static uint8_t
motg_type(uint8_t type)1149 motg_type(uint8_t type)
1150 {
1151 switch(type) {
1152 case UE_CONTROL:
1153 return MUSB2_MASK_TI_PROTO_CTRL;
1154 case UE_ISOCHRONOUS:
1155 return MUSB2_MASK_TI_PROTO_ISOC;
1156 case UE_BULK:
1157 return MUSB2_MASK_TI_PROTO_BULK;
1158 case UE_INTERRUPT:
1159 return MUSB2_MASK_TI_PROTO_INTR;
1160 default:
1161 panic("motg: unknown type %d", type);
1162 /* NOTREACHED */
1163 }
1164 }
1165
1166 static void
motg_setup_endpoint_tx(struct usbd_xfer * xfer)1167 motg_setup_endpoint_tx(struct usbd_xfer *xfer)
1168 {
1169 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1170 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1171 struct usbd_device *dev = otgpipe->pipe.up_dev;
1172 int epnumber = otgpipe->hw_ep->ep_number;
1173
1174 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr);
1175 if (dev->ud_myhsport) {
1176 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber),
1177 dev->ud_myhsport->up_parent->ud_addr);
1178 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber),
1179 dev->ud_myhsport->up_portno);
1180 } else {
1181 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0);
1182 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0);
1183 }
1184 UWRITE1(sc, MUSB2_REG_TXTI,
1185 motg_speed(dev->ud_speed) |
1186 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) |
1187 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes))
1188 );
1189 if (epnumber == 0) {
1190 if (sc->sc_high_speed) {
1191 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT,
1192 NAK_TO_CTRL_HIGH);
1193 } else {
1194 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL);
1195 }
1196 } else {
1197 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE)
1198 == UE_BULK) {
1199 if (sc->sc_high_speed) {
1200 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT,
1201 NAK_TO_BULK_HIGH);
1202 } else {
1203 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK);
1204 }
1205 } else {
1206 if (sc->sc_high_speed) {
1207 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH);
1208 } else {
1209 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO);
1210 }
1211 }
1212 }
1213 }
1214
1215 static void
motg_setup_endpoint_rx(struct usbd_xfer * xfer)1216 motg_setup_endpoint_rx(struct usbd_xfer *xfer)
1217 {
1218 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1219 struct usbd_device *dev = xfer->ux_pipe->up_dev;
1220 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1221 int epnumber = otgpipe->hw_ep->ep_number;
1222
1223 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr);
1224 if (dev->ud_myhsport) {
1225 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber),
1226 dev->ud_myhsport->up_parent->ud_addr);
1227 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber),
1228 dev->ud_myhsport->up_portno);
1229 } else {
1230 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0);
1231 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0);
1232 }
1233 UWRITE1(sc, MUSB2_REG_RXTI,
1234 motg_speed(dev->ud_speed) |
1235 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) |
1236 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes))
1237 );
1238 if (epnumber == 0) {
1239 if (sc->sc_high_speed) {
1240 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT,
1241 NAK_TO_CTRL_HIGH);
1242 } else {
1243 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_CTRL);
1244 }
1245 } else {
1246 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE)
1247 == UE_BULK) {
1248 if (sc->sc_high_speed) {
1249 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT,
1250 NAK_TO_BULK_HIGH);
1251 } else {
1252 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK);
1253 }
1254 } else {
1255 if (sc->sc_high_speed) {
1256 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH);
1257 } else {
1258 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO);
1259 }
1260 }
1261 }
1262 }
1263
1264 static usbd_status
motg_device_ctrl_transfer(struct usbd_xfer * xfer)1265 motg_device_ctrl_transfer(struct usbd_xfer *xfer)
1266 {
1267
1268 /* Pipe isn't running, so start it first. */
1269 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1270 }
1271
1272 static usbd_status
motg_device_ctrl_start(struct usbd_xfer * xfer)1273 motg_device_ctrl_start(struct usbd_xfer *xfer)
1274 {
1275 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1276
1277 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1278
1279 return motg_device_ctrl_start1(sc);
1280 }
1281
1282 static usbd_status
motg_device_ctrl_start1(struct motg_softc * sc)1283 motg_device_ctrl_start1(struct motg_softc *sc)
1284 {
1285 struct motg_hw_ep *ep = &sc->sc_in_ep[0];
1286 struct usbd_xfer *xfer = NULL;
1287 struct motg_pipe *otgpipe;
1288 usbd_status err = 0;
1289
1290 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1291
1292 KASSERT(mutex_owned(&sc->sc_lock));
1293 if (sc->sc_dying)
1294 return USBD_IOERROR;
1295
1296 if (!sc->sc_connected)
1297 return USBD_IOERROR;
1298
1299 if (ep->xfer != NULL) {
1300 err = USBD_IN_PROGRESS;
1301 goto end;
1302 }
1303 /* locate the first pipe with work to do */
1304 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) {
1305 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue);
1306 DPRINTFN(MD_CTRL, "pipe %#jx xfer %#jx status %jd",
1307 (uintptr_t)otgpipe, (uintptr_t)xfer,
1308 (xfer != NULL) ? xfer->ux_status : 0, 0);
1309
1310 if (xfer != NULL) {
1311 /* move this pipe to the end of the list */
1312 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe,
1313 motg_pipe, ep_pipe_list);
1314 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes,
1315 otgpipe, ep_pipe_list);
1316 break;
1317 }
1318 }
1319 if (xfer == NULL) {
1320 err = USBD_NOT_STARTED;
1321 goto end;
1322 }
1323 if (xfer->ux_status == USBD_NOT_STARTED) {
1324 xfer->ux_status = USBD_IN_PROGRESS;
1325 usbd_xfer_schedule_timeout(xfer);
1326 } else {
1327 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
1328 }
1329 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe));
1330 KASSERT(otgpipe->hw_ep == ep);
1331 KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1332 // KASSERT(xfer->ux_actlen == 0);
1333 xfer->ux_actlen = 0;
1334
1335 ep->xfer = xfer;
1336 ep->datalen = xfer->ux_length;
1337 if (ep->datalen > 0)
1338 ep->data = xfer->ux_buf;
1339 else
1340 ep->data = NULL;
1341 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) &&
1342 (ep->datalen % 64) == 0)
1343 ep->need_short_xfer = 1;
1344 else
1345 ep->need_short_xfer = 0;
1346 /* now we need send this request */
1347 DPRINTFN(MD_CTRL,
1348 "xfer %#jx send data %#jx len %jd short %jd",
1349 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen,
1350 ep->need_short_xfer);
1351 DPRINTFN(MD_CTRL,
1352 "xfer %#jx ... speed %jd to %jd", (uintptr_t)xfer,
1353 xfer->ux_pipe->up_dev->ud_speed,
1354 xfer->ux_pipe->up_dev->ud_addr, 0);
1355 KASSERT(ep->phase == IDLE);
1356 ep->phase = SETUP;
1357 /* select endpoint 0 */
1358 UWRITE1(sc, MUSB2_REG_EPINDEX, 0);
1359 /* fifo should be empty at this point */
1360 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0);
1361 /* send data */
1362 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0);
1363 KASSERT(sizeof(xfer->ux_request) == 8);
1364 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0),
1365 (void *)&xfer->ux_request, sizeof(xfer->ux_request));
1366
1367 motg_setup_endpoint_tx(xfer);
1368 /* start transaction */
1369 UWRITE1(sc, MUSB2_REG_TXCSRL,
1370 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT);
1371
1372 end:
1373 if (err)
1374 return err;
1375
1376 return USBD_IN_PROGRESS;
1377 }
1378
1379 static void
motg_device_ctrl_read(struct usbd_xfer * xfer)1380 motg_device_ctrl_read(struct usbd_xfer *xfer)
1381 {
1382 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1383 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1384 /* assume endpoint already selected */
1385 motg_setup_endpoint_rx(xfer);
1386 /* start transaction */
1387 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT);
1388 otgpipe->hw_ep->phase = DATA_IN;
1389 }
1390
1391 static void
motg_device_ctrl_intr_rx(struct motg_softc * sc)1392 motg_device_ctrl_intr_rx(struct motg_softc *sc)
1393 {
1394 struct motg_hw_ep *ep = &sc->sc_in_ep[0];
1395 struct usbd_xfer *xfer = ep->xfer;
1396 uint8_t csr;
1397 int datalen, max_datalen;
1398 char *data;
1399 bool got_short;
1400 usbd_status new_status = USBD_IN_PROGRESS;
1401
1402 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1403
1404 KASSERT(mutex_owned(&sc->sc_lock));
1405 KASSERT(ep->phase == DATA_IN || ep->phase == STATUS_IN);
1406
1407 /* select endpoint 0 */
1408 UWRITE1(sc, MUSB2_REG_EPINDEX, 0);
1409
1410 /* read out FIFO status */
1411 csr = UREAD1(sc, MUSB2_REG_TXCSRL);
1412 DPRINTFN(MD_CTRL, "phase %jd csr %#jx xfer %#jx status %jd",
1413 ep->phase, csr, (uintptr_t)xfer,
1414 (xfer != NULL) ? xfer->ux_status : 0);
1415
1416 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1417 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
1418 UWRITE1(sc, MUSB2_REG_TXCSRL, csr);
1419
1420 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1421 UWRITE1(sc, MUSB2_REG_TXCSRL, csr);
1422 new_status = USBD_TIMEOUT; /* XXX */
1423 goto complete;
1424 }
1425 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) {
1426 if (csr & MUSB2_MASK_CSR0L_RXSTALL)
1427 new_status = USBD_STALLED;
1428 else
1429 new_status = USBD_IOERROR;
1430 /* clear status */
1431 UWRITE1(sc, MUSB2_REG_TXCSRL, 0);
1432 goto complete;
1433 }
1434 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0)
1435 return; /* no data yet */
1436
1437 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS)
1438 goto complete;
1439
1440 if (ep->phase == STATUS_IN) {
1441 new_status = USBD_NORMAL_COMPLETION;
1442 UWRITE1(sc, MUSB2_REG_TXCSRL, 0);
1443 goto complete;
1444 }
1445 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT);
1446 DPRINTFN(MD_CTRL, "phase %jd datalen %jd", ep->phase, datalen, 0, 0);
1447 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0);
1448 max_datalen = uimin(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize),
1449 ep->datalen);
1450 if (datalen > max_datalen) {
1451 new_status = USBD_IOERROR;
1452 UWRITE1(sc, MUSB2_REG_TXCSRL, 0);
1453 goto complete;
1454 }
1455 got_short = (datalen < max_datalen);
1456 if (datalen > 0) {
1457 KASSERT(ep->phase == DATA_IN);
1458 data = ep->data;
1459 ep->data += datalen;
1460 ep->datalen -= datalen;
1461 xfer->ux_actlen += datalen;
1462 if (((vaddr_t)data & 0x3) == 0 &&
1463 (datalen >> 2) > 0) {
1464 DPRINTFN(MD_CTRL, "r4 data %#jx len %jd",
1465 (uintptr_t)data, datalen, 0, 0);
1466 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh,
1467 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2);
1468 data += (datalen & ~0x3);
1469 datalen -= (datalen & ~0x3);
1470 }
1471 DPRINTFN(MD_CTRL, "r1 data %#jx len %jd", (uintptr_t)data,
1472 datalen, 0, 0);
1473 if (datalen) {
1474 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh,
1475 MUSB2_REG_EPFIFO(0), data, datalen);
1476 }
1477 }
1478 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY);
1479 KASSERT(ep->phase == DATA_IN);
1480 if (got_short || (ep->datalen == 0)) {
1481 if (ep->need_short_xfer == 0) {
1482 ep->phase = STATUS_OUT;
1483 UWRITE1(sc, MUSB2_REG_TXCSRH,
1484 UREAD1(sc, MUSB2_REG_TXCSRH) |
1485 MUSB2_MASK_CSR0H_PING_DIS);
1486 motg_setup_endpoint_tx(xfer);
1487 UWRITE1(sc, MUSB2_REG_TXCSRL,
1488 MUSB2_MASK_CSR0L_STATUSPKT |
1489 MUSB2_MASK_CSR0L_TXPKTRDY);
1490 return;
1491 }
1492 ep->need_short_xfer = 0;
1493 }
1494 motg_device_ctrl_read(xfer);
1495 return;
1496 complete:
1497 ep->phase = IDLE;
1498 ep->xfer = NULL;
1499 /*
1500 * Try to claim this xfer for completion. If it has already
1501 * completed or aborted, drop it on the floor.
1502 */
1503 if (xfer && usbd_xfer_trycomplete(xfer)) {
1504 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
1505 KASSERT(new_status != USBD_IN_PROGRESS);
1506 xfer->ux_status = new_status;
1507 usb_transfer_complete(xfer);
1508 }
1509 motg_device_ctrl_start1(sc);
1510 }
1511
1512 static void
motg_device_ctrl_intr_tx(struct motg_softc * sc)1513 motg_device_ctrl_intr_tx(struct motg_softc *sc)
1514 {
1515 struct motg_hw_ep *ep = &sc->sc_in_ep[0];
1516 struct usbd_xfer *xfer = ep->xfer;
1517 uint8_t csr;
1518 int datalen;
1519 char *data;
1520 usbd_status new_status = USBD_IN_PROGRESS;
1521
1522 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1523
1524 KASSERT(mutex_owned(&sc->sc_lock));
1525
1526 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) {
1527 motg_device_ctrl_intr_rx(sc);
1528 return;
1529 }
1530
1531 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT ||
1532 ep->phase == STATUS_OUT);
1533
1534 /* select endpoint 0 */
1535 UWRITE1(sc, MUSB2_REG_EPINDEX, 0);
1536
1537 csr = UREAD1(sc, MUSB2_REG_TXCSRL);
1538 DPRINTFN(MD_CTRL, "phase %jd csr %#jx xfer %#jx status %jd",
1539 ep->phase, csr, (uintptr_t)xfer,
1540 (xfer != NULL) ? xfer->ux_status : 0);
1541
1542 if (csr & MUSB2_MASK_CSR0L_RXSTALL) {
1543 /* command not accepted */
1544 new_status = USBD_STALLED;
1545 /* clear status */
1546 UWRITE1(sc, MUSB2_REG_TXCSRL, 0);
1547 goto complete;
1548 }
1549 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1550 new_status = USBD_TIMEOUT; /* XXX */
1551 /* flush fifo */
1552 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1553 UWRITE1(sc, MUSB2_REG_TXCSRH,
1554 UREAD1(sc, MUSB2_REG_TXCSRH) |
1555 MUSB2_MASK_CSR0H_FFLUSH);
1556 csr = UREAD1(sc, MUSB2_REG_TXCSRL);
1557 }
1558 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1559 UWRITE1(sc, MUSB2_REG_TXCSRL, csr);
1560 goto complete;
1561 }
1562 if (csr & MUSB2_MASK_CSR0L_ERROR) {
1563 new_status = USBD_IOERROR;
1564 /* clear status */
1565 UWRITE1(sc, MUSB2_REG_TXCSRL, 0);
1566 goto complete;
1567 }
1568 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1569 /* data still not sent */
1570 return;
1571 }
1572 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS)
1573 goto complete;
1574 if (ep->phase == STATUS_OUT) {
1575 /*
1576 * we have sent status and got no error;
1577 * declare transfer complete
1578 */
1579 DPRINTFN(MD_CTRL, "xfer %#jx status %jd complete",
1580 (uintptr_t)xfer, xfer->ux_status, 0, 0);
1581 new_status = USBD_NORMAL_COMPLETION;
1582 goto complete;
1583 }
1584 if (ep->datalen == 0) {
1585 if (ep->need_short_xfer) {
1586 ep->need_short_xfer = 0;
1587 /* one more data phase */
1588 if (xfer->ux_request.bmRequestType & UT_READ) {
1589 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_IN",
1590 (uintptr_t)xfer, 0, 0, 0);
1591 motg_device_ctrl_read(xfer);
1592 return;
1593 } /* else fall back to DATA_OUT */
1594 } else {
1595 DPRINTFN(MD_CTRL, "xfer %#jx to STATUS_IN, csrh %#jx",
1596 (uintptr_t)xfer, UREAD1(sc, MUSB2_REG_TXCSRH),
1597 0, 0);
1598 ep->phase = STATUS_IN;
1599 UWRITE1(sc, MUSB2_REG_RXCSRH,
1600 UREAD1(sc, MUSB2_REG_RXCSRH) |
1601 MUSB2_MASK_CSR0H_PING_DIS);
1602 motg_setup_endpoint_rx(xfer);
1603 UWRITE1(sc, MUSB2_REG_TXCSRL,
1604 MUSB2_MASK_CSR0L_STATUSPKT |
1605 MUSB2_MASK_CSR0L_REQPKT);
1606 return;
1607 }
1608 }
1609 if (xfer->ux_request.bmRequestType & UT_READ) {
1610 motg_device_ctrl_read(xfer);
1611 return;
1612 }
1613 /* setup a dataout phase */
1614 datalen = uimin(ep->datalen,
1615 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize));
1616 ep->phase = DATA_OUT;
1617 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_OUT, csrh %#jx", (uintptr_t)xfer,
1618 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0);
1619 if (datalen) {
1620 data = ep->data;
1621 ep->data += datalen;
1622 ep->datalen -= datalen;
1623 xfer->ux_actlen += datalen;
1624 if (((vaddr_t)data & 0x3) == 0 &&
1625 (datalen >> 2) > 0) {
1626 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh,
1627 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2);
1628 data += (datalen & ~0x3);
1629 datalen -= (datalen & ~0x3);
1630 }
1631 if (datalen) {
1632 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh,
1633 MUSB2_REG_EPFIFO(0), data, datalen);
1634 }
1635 }
1636 /* send data */
1637 motg_setup_endpoint_tx(xfer);
1638 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY);
1639 return;
1640
1641 complete:
1642 ep->phase = IDLE;
1643 ep->xfer = NULL;
1644 /*
1645 * Try to claim this xfer for completion. If it has already
1646 * completed or aborted, drop it on the floor.
1647 */
1648 if (xfer && usbd_xfer_trycomplete(xfer)) {
1649 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
1650 KASSERT(new_status != USBD_IN_PROGRESS);
1651 xfer->ux_status = new_status;
1652 usb_transfer_complete(xfer);
1653 }
1654 motg_device_ctrl_start1(sc);
1655 }
1656
1657 /* Abort a device control request. */
1658 void
motg_device_ctrl_abort(struct usbd_xfer * xfer)1659 motg_device_ctrl_abort(struct usbd_xfer *xfer)
1660 {
1661 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1662
1663 usbd_xfer_abort(xfer);
1664 }
1665
1666 /* Close a device control pipe */
1667 void
motg_device_ctrl_close(struct usbd_pipe * pipe)1668 motg_device_ctrl_close(struct usbd_pipe *pipe)
1669 {
1670 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe);
1671 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe);
1672 struct motg_pipe *otgpipeiter;
1673
1674 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1675
1676 KASSERT(mutex_owned(&sc->sc_lock));
1677 KASSERT(otgpipe->hw_ep->xfer == NULL ||
1678 otgpipe->hw_ep->xfer->ux_pipe != pipe);
1679
1680 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) {
1681 if (otgpipeiter == otgpipe) {
1682 /* remove from list */
1683 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe,
1684 motg_pipe, ep_pipe_list);
1685 otgpipe->hw_ep->refcount--;
1686 /* we're done */
1687 return;
1688 }
1689 }
1690 panic("motg_device_ctrl_close: not found");
1691 }
1692
1693 void
motg_device_ctrl_done(struct usbd_xfer * xfer)1694 motg_device_ctrl_done(struct usbd_xfer *xfer)
1695 {
1696 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1697 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1698
1699 KASSERT(otgpipe->hw_ep->xfer != xfer);
1700 }
1701
1702 static usbd_status
motg_device_data_transfer(struct usbd_xfer * xfer)1703 motg_device_data_transfer(struct usbd_xfer *xfer)
1704 {
1705 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1706
1707 /* Pipe isn't running, so start it first. */
1708 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
1709 }
1710
1711 static usbd_status
motg_device_data_start(struct usbd_xfer * xfer)1712 motg_device_data_start(struct usbd_xfer *xfer)
1713 {
1714 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1715 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1716
1717 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1718
1719 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0);
1720
1721 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1722
1723 return motg_device_data_start1(sc, otgpipe->hw_ep);
1724 }
1725
1726 static usbd_status
motg_device_data_start1(struct motg_softc * sc,struct motg_hw_ep * ep)1727 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep)
1728 {
1729 struct usbd_xfer *xfer = NULL;
1730 struct motg_pipe *otgpipe;
1731 usbd_status err = 0;
1732 uint32_t val __diagused;
1733
1734 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1735
1736 KASSERT(mutex_owned(&sc->sc_lock));
1737 if (sc->sc_dying)
1738 return USBD_IOERROR;
1739
1740 if (!sc->sc_connected)
1741 return USBD_IOERROR;
1742
1743 if (ep->xfer != NULL) {
1744 err = USBD_IN_PROGRESS;
1745 goto end;
1746 }
1747 /* locate the first pipe with work to do */
1748 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) {
1749 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue);
1750 DPRINTFN(MD_BULK, "pipe %#jx xfer %#jx status %jd",
1751 (uintptr_t)otgpipe, (uintptr_t)xfer,
1752 (xfer != NULL) ? xfer->ux_status : 0, 0);
1753 if (xfer != NULL) {
1754 /* move this pipe to the end of the list */
1755 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe,
1756 motg_pipe, ep_pipe_list);
1757 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes,
1758 otgpipe, ep_pipe_list);
1759 break;
1760 }
1761 }
1762 if (xfer == NULL) {
1763 err = USBD_NOT_STARTED;
1764 goto end;
1765 }
1766 if (xfer->ux_status == USBD_NOT_STARTED) {
1767 xfer->ux_status = USBD_IN_PROGRESS;
1768 usbd_xfer_schedule_timeout(xfer);
1769 } else {
1770 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
1771 }
1772 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe));
1773 KASSERT(otgpipe->hw_ep == ep);
1774 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
1775 // KASSERT(xfer->ux_actlen == 0);
1776 xfer->ux_actlen = 0;
1777
1778 ep->xfer = xfer;
1779 ep->datalen = xfer->ux_length;
1780 KASSERT(ep->datalen > 0);
1781 ep->data = xfer->ux_buf;
1782 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) &&
1783 (ep->datalen % 64) == 0)
1784 ep->need_short_xfer = 1;
1785 else
1786 ep->need_short_xfer = 0;
1787 /* now we need send this request */
1788 DPRINTFN(MD_BULK,
1789 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ?
1790 "xfer %#jx in data %#jx len %jd short %jd" :
1791 "xfer %#jx out data %#jx len %jd short %jd",
1792 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen,
1793 ep->need_short_xfer);
1794 DPRINTFN(MD_BULK, "... speed %jd to %jd",
1795 xfer->ux_pipe->up_dev->ud_speed,
1796 xfer->ux_pipe->up_dev->ud_addr, 0, 0);
1797 KASSERT(ep->phase == IDLE);
1798 /* select endpoint */
1799 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number);
1800 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress)
1801 == UE_DIR_IN) {
1802 val = UREAD1(sc, MUSB2_REG_RXCSRL);
1803 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0);
1804 motg_device_data_read(xfer);
1805 } else {
1806 ep->phase = DATA_OUT;
1807 val = UREAD1(sc, MUSB2_REG_TXCSRL);
1808 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0);
1809 motg_device_data_write(xfer);
1810 }
1811 end:
1812 if (err)
1813 return err;
1814
1815 return USBD_IN_PROGRESS;
1816 }
1817
1818 static void
motg_device_data_read(struct usbd_xfer * xfer)1819 motg_device_data_read(struct usbd_xfer *xfer)
1820 {
1821 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1822 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1823 uint32_t val;
1824
1825 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1826
1827 KASSERT(mutex_owned(&sc->sc_lock));
1828 /* assume endpoint already selected */
1829 motg_setup_endpoint_rx(xfer);
1830 /* Max packet size */
1831 UWRITE2(sc, MUSB2_REG_RXMAXP,
1832 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize));
1833 /* Data Toggle */
1834 val = UREAD1(sc, MUSB2_REG_RXCSRH);
1835 val |= MUSB2_MASK_CSRH_RXDT_WREN;
1836 if (otgpipe->nexttoggle)
1837 val |= MUSB2_MASK_CSRH_RXDT_VAL;
1838 else
1839 val &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1840 UWRITE1(sc, MUSB2_REG_RXCSRH, val);
1841
1842 DPRINTFN(MD_BULK, "%#jx to DATA_IN on ep %jd, csrh %#jx",
1843 (uintptr_t)xfer, otgpipe->hw_ep->ep_number,
1844 UREAD1(sc, MUSB2_REG_RXCSRH), 0);
1845 /* start transaction */
1846 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT);
1847 otgpipe->hw_ep->phase = DATA_IN;
1848 }
1849
1850 static void
motg_device_data_write(struct usbd_xfer * xfer)1851 motg_device_data_write(struct usbd_xfer *xfer)
1852 {
1853 struct motg_softc *sc = MOTG_XFER2SC(xfer);
1854 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1855 struct motg_hw_ep *ep = otgpipe->hw_ep;
1856 int datalen;
1857 char *data;
1858 uint32_t val;
1859
1860 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1861
1862 KASSERT(xfer!=NULL);
1863 KASSERT(mutex_owned(&sc->sc_lock));
1864
1865 datalen = uimin(ep->datalen,
1866 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize));
1867 ep->phase = DATA_OUT;
1868 DPRINTFN(MD_BULK, "%#jx to DATA_OUT on ep %jd, len %jd csrh %#jx",
1869 (uintptr_t)xfer, ep->ep_number, datalen,
1870 UREAD1(sc, MUSB2_REG_TXCSRH));
1871
1872 /* assume endpoint already selected */
1873 /* write data to fifo */
1874 data = ep->data;
1875 ep->data += datalen;
1876 ep->datalen -= datalen;
1877 xfer->ux_actlen += datalen;
1878 if (((vaddr_t)data & 0x3) == 0 &&
1879 (datalen >> 2) > 0) {
1880 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh,
1881 MUSB2_REG_EPFIFO(ep->ep_number),
1882 (void *)data, datalen >> 2);
1883 data += (datalen & ~0x3);
1884 datalen -= (datalen & ~0x3);
1885 }
1886 if (datalen) {
1887 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh,
1888 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen);
1889 }
1890
1891 motg_setup_endpoint_tx(xfer);
1892 /* Max packet size */
1893 UWRITE2(sc, MUSB2_REG_TXMAXP,
1894 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize));
1895 /* Data Toggle */
1896 val = UREAD1(sc, MUSB2_REG_TXCSRH);
1897 val |= MUSB2_MASK_CSRH_TXDT_WREN;
1898 if (otgpipe->nexttoggle)
1899 val |= MUSB2_MASK_CSRH_TXDT_VAL;
1900 else
1901 val &= ~MUSB2_MASK_CSRH_TXDT_VAL;
1902 UWRITE1(sc, MUSB2_REG_TXCSRH, val);
1903
1904 /* start transaction */
1905 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY);
1906 }
1907
1908 static void
motg_device_intr_rx(struct motg_softc * sc,int epnumber)1909 motg_device_intr_rx(struct motg_softc *sc, int epnumber)
1910 {
1911 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber];
1912 struct usbd_xfer *xfer = ep->xfer;
1913 uint8_t csr;
1914 int datalen, max_datalen;
1915 char *data;
1916 bool got_short;
1917 usbd_status new_status = USBD_IN_PROGRESS;
1918
1919 MOTGHIST_FUNC(); MOTGHIST_CALLED();
1920
1921 KASSERT(mutex_owned(&sc->sc_lock));
1922 KASSERT(ep->ep_number == epnumber);
1923
1924 DPRINTFN(MD_BULK, "on ep %jd", epnumber, 0, 0, 0);
1925 /* select endpoint */
1926 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber);
1927
1928 /* read out FIFO status */
1929 csr = UREAD1(sc, MUSB2_REG_RXCSRL);
1930 DPRINTFN(MD_BULK, "phase %jd csr %#jx", ep->phase, csr ,0 ,0);
1931
1932 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL |
1933 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0)
1934 return;
1935
1936 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase);
1937 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1938 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1939 UWRITE1(sc, MUSB2_REG_RXCSRL, csr);
1940
1941 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1942 UWRITE1(sc, MUSB2_REG_RXCSRL, csr);
1943 new_status = USBD_TIMEOUT; /* XXX */
1944 goto complete;
1945 }
1946 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) {
1947 if (csr & MUSB2_MASK_CSRL_RXSTALL)
1948 new_status = USBD_STALLED;
1949 else
1950 new_status = USBD_IOERROR;
1951 /* clear status */
1952 UWRITE1(sc, MUSB2_REG_RXCSRL, 0);
1953 goto complete;
1954 }
1955 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY);
1956
1957 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) {
1958 UWRITE1(sc, MUSB2_REG_RXCSRL, 0);
1959 goto complete;
1960 }
1961
1962 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
1963 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1;
1964
1965 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT);
1966 DPRINTFN(MD_BULK, "phase %jd datalen %jd", ep->phase, datalen ,0 ,0);
1967 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0);
1968 max_datalen = uimin(
1969 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)),
1970 ep->datalen);
1971 if (datalen > max_datalen) {
1972 new_status = USBD_IOERROR;
1973 UWRITE1(sc, MUSB2_REG_RXCSRL, 0);
1974 goto complete;
1975 }
1976 got_short = (datalen < max_datalen);
1977 if (datalen > 0) {
1978 KASSERT(ep->phase == DATA_IN);
1979 data = ep->data;
1980 ep->data += datalen;
1981 ep->datalen -= datalen;
1982 xfer->ux_actlen += datalen;
1983 if (((vaddr_t)data & 0x3) == 0 &&
1984 (datalen >> 2) > 0) {
1985 DPRINTFN(MD_BULK, "r4 data %#jx len %jd",
1986 (uintptr_t)data, datalen, 0, 0);
1987 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh,
1988 MUSB2_REG_EPFIFO(ep->ep_number),
1989 (void *)data, datalen >> 2);
1990 data += (datalen & ~0x3);
1991 datalen -= (datalen & ~0x3);
1992 }
1993 DPRINTFN(MD_BULK, "r1 data %#jx len %jd", (uintptr_t)data,
1994 datalen ,0 ,0);
1995 if (datalen) {
1996 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh,
1997 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen);
1998 }
1999 }
2000 UWRITE1(sc, MUSB2_REG_RXCSRL, 0);
2001 KASSERT(ep->phase == DATA_IN);
2002 if (got_short || (ep->datalen == 0)) {
2003 if (ep->need_short_xfer == 0) {
2004 new_status = USBD_NORMAL_COMPLETION;
2005 goto complete;
2006 }
2007 ep->need_short_xfer = 0;
2008 }
2009 motg_device_data_read(xfer);
2010 return;
2011 complete:
2012 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer,
2013 (xfer != NULL) ? xfer->ux_status : 0, 0, 0);
2014 ep->phase = IDLE;
2015 ep->xfer = NULL;
2016 /*
2017 * Try to claim this xfer for completion. If it has already
2018 * completed or aborted, drop it on the floor.
2019 */
2020 if (xfer && usbd_xfer_trycomplete(xfer)) {
2021 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
2022 KASSERT(new_status != USBD_IN_PROGRESS);
2023 xfer->ux_status = new_status;
2024 usb_transfer_complete(xfer);
2025 }
2026 motg_device_data_start1(sc, ep);
2027 }
2028
2029 static void
motg_device_intr_tx(struct motg_softc * sc,int epnumber)2030 motg_device_intr_tx(struct motg_softc *sc, int epnumber)
2031 {
2032 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber];
2033 struct usbd_xfer *xfer = ep->xfer;
2034 uint8_t csr;
2035 struct motg_pipe *otgpipe;
2036 usbd_status new_status = USBD_IN_PROGRESS;
2037
2038 MOTGHIST_FUNC(); MOTGHIST_CALLED();
2039
2040 KASSERT(mutex_owned(&sc->sc_lock));
2041 KASSERT(ep->ep_number == epnumber);
2042
2043 DPRINTFN(MD_BULK, " on ep %jd", epnumber, 0, 0, 0);
2044 /* select endpoint */
2045 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber);
2046
2047 csr = UREAD1(sc, MUSB2_REG_TXCSRL);
2048 DPRINTFN(MD_BULK, "phase %jd csr %#jx", ep->phase, csr, 0, 0);
2049
2050 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) {
2051 /* command not accepted */
2052 if (csr & MUSB2_MASK_CSRL_TXSTALLED)
2053 new_status = USBD_STALLED;
2054 else
2055 new_status = USBD_IOERROR;
2056 /* clear status */
2057 UWRITE1(sc, MUSB2_REG_TXCSRL, 0);
2058 goto complete;
2059 }
2060 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
2061 new_status = USBD_TIMEOUT; /* XXX */
2062 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
2063 UWRITE1(sc, MUSB2_REG_TXCSRL, csr);
2064 /* flush fifo */
2065 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2066 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
2067 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
2068 UWRITE1(sc, MUSB2_REG_TXCSRL, csr);
2069 delay(1000);
2070 csr = UREAD1(sc, MUSB2_REG_TXCSRL);
2071 DPRINTFN(MD_BULK, "TX fifo flush ep %jd CSR %#jx",
2072 epnumber, csr, 0, 0);
2073 }
2074 goto complete;
2075 }
2076 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) {
2077 /* data still not sent */
2078 return;
2079 }
2080 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS)
2081 goto complete;
2082 KASSERT(ep->phase == DATA_OUT);
2083
2084 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
2085 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1;
2086
2087 if (ep->datalen == 0) {
2088 if (ep->need_short_xfer) {
2089 ep->need_short_xfer = 0;
2090 /* one more data phase */
2091 } else {
2092 new_status = USBD_NORMAL_COMPLETION;
2093 goto complete;
2094 }
2095 }
2096 motg_device_data_write(xfer);
2097 return;
2098
2099 complete:
2100 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer,
2101 (xfer != NULL) ? xfer->ux_status : 0, 0, 0);
2102 ep->phase = IDLE;
2103 ep->xfer = NULL;
2104 /*
2105 * Try to claim this xfer for completion. If it has already
2106 * completed or aborted, drop it on the floor.
2107 */
2108 if (xfer && usbd_xfer_trycomplete(xfer)) {
2109 KASSERT(xfer->ux_status == USBD_IN_PROGRESS);
2110 KASSERT(new_status != USBD_IN_PROGRESS);
2111 xfer->ux_status = new_status;
2112 usb_transfer_complete(xfer);
2113 }
2114 motg_device_data_start1(sc, ep);
2115 }
2116
2117 /* Abort a device control request. */
2118 void
motg_device_data_abort(struct usbd_xfer * xfer)2119 motg_device_data_abort(struct usbd_xfer *xfer)
2120 {
2121 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer);
2122 KASSERT(mutex_owned(&sc->sc_lock));
2123
2124 MOTGHIST_FUNC(); MOTGHIST_CALLED();
2125
2126 usbd_xfer_abort(xfer);
2127 }
2128
2129 /* Close a device control pipe */
2130 void
motg_device_data_close(struct usbd_pipe * pipe)2131 motg_device_data_close(struct usbd_pipe *pipe)
2132 {
2133 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe);
2134 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe);
2135 struct motg_pipe *otgpipeiter;
2136
2137 MOTGHIST_FUNC(); MOTGHIST_CALLED();
2138
2139 KASSERT(mutex_owned(&sc->sc_lock));
2140 KASSERT(otgpipe->hw_ep->xfer == NULL ||
2141 otgpipe->hw_ep->xfer->ux_pipe != pipe);
2142
2143 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle;
2144 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) {
2145 if (otgpipeiter == otgpipe) {
2146 /* remove from list */
2147 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe,
2148 motg_pipe, ep_pipe_list);
2149 otgpipe->hw_ep->refcount--;
2150 /* we're done */
2151 return;
2152 }
2153 }
2154 panic("motg_device_data_close: not found");
2155 }
2156
2157 void
motg_device_data_done(struct usbd_xfer * xfer)2158 motg_device_data_done(struct usbd_xfer *xfer)
2159 {
2160 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe);
2161 MOTGHIST_FUNC(); MOTGHIST_CALLED();
2162
2163 KASSERT(otgpipe->hw_ep->xfer != xfer);
2164 }
2165
2166 void
motg_device_clear_toggle(struct usbd_pipe * pipe)2167 motg_device_clear_toggle(struct usbd_pipe *pipe)
2168 {
2169 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe);
2170 otgpipe->nexttoggle = 0;
2171 }
2172
2173 /* Abort a device control request. */
2174 static void
motg_abortx(struct usbd_xfer * xfer)2175 motg_abortx(struct usbd_xfer *xfer)
2176 {
2177 MOTGHIST_FUNC(); MOTGHIST_CALLED();
2178 uint8_t csr;
2179 struct motg_softc *sc = MOTG_XFER2SC(xfer);
2180 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe);
2181
2182 KASSERT(mutex_owned(&sc->sc_lock));
2183 ASSERT_SLEEPABLE();
2184
2185 /*
2186 * If we're dying, skip the hardware action and just notify the
2187 * software that we're done.
2188 */
2189 if (sc->sc_dying) {
2190 goto dying;
2191 }
2192
2193 if (otgpipe->hw_ep->xfer == xfer) {
2194 otgpipe->hw_ep->xfer = NULL;
2195 if (otgpipe->hw_ep->ep_number > 0) {
2196 /* select endpoint */
2197 UWRITE1(sc, MUSB2_REG_EPINDEX,
2198 otgpipe->hw_ep->ep_number);
2199 if (otgpipe->hw_ep->phase == DATA_OUT) {
2200 csr = UREAD1(sc, MUSB2_REG_TXCSRL);
2201 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2202 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
2203 UWRITE1(sc, MUSB2_REG_TXCSRL, csr);
2204 csr = UREAD1(sc, MUSB2_REG_TXCSRL);
2205 }
2206 UWRITE1(sc, MUSB2_REG_TXCSRL, 0);
2207 } else if (otgpipe->hw_ep->phase == DATA_IN) {
2208 csr = UREAD1(sc, MUSB2_REG_RXCSRL);
2209 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2210 csr |= MUSB2_MASK_CSRL_RXFFLUSH;
2211 UWRITE1(sc, MUSB2_REG_RXCSRL, csr);
2212 csr = UREAD1(sc, MUSB2_REG_RXCSRL);
2213 }
2214 UWRITE1(sc, MUSB2_REG_RXCSRL, 0);
2215 }
2216 otgpipe->hw_ep->phase = IDLE;
2217 }
2218 }
2219 dying:
2220 KASSERT(mutex_owned(&sc->sc_lock));
2221 }
2222