1 /* $NetBSD: uhci_pci.c,v 1.58 2014/09/21 14:30:22 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: uhci_pci.c,v 1.58 2014/09/21 14:30:22 christos Exp $"); 35 36 #include "ehci.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/proc.h> 43 #include <sys/queue.h> 44 45 #include <sys/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/usb_pci.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 #include <dev/usb/usbdivar.h> 53 #include <dev/usb/usb_mem.h> 54 55 #include <dev/usb/uhcireg.h> 56 #include <dev/usb/uhcivar.h> 57 58 static bool uhci_pci_resume(device_t, const pmf_qual_t *); 59 60 struct uhci_pci_softc { 61 uhci_softc_t sc; 62 #if NEHCI > 0 63 struct usb_pci sc_pci; 64 #endif 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_tag; 67 void *sc_ih; /* interrupt vectoring */ 68 unsigned sc_initialized; 69 #define SC_INIT_UHCI 1 70 #define SC_INIT_PMF 2 71 }; 72 73 static int 74 uhci_pci_match(device_t parent, cfdata_t match, void *aux) 75 { 76 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 77 78 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 79 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 80 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_UHCI) 81 return (1); 82 83 return (0); 84 } 85 86 static void 87 uhci_pci_attach(device_t parent, device_t self, void *aux) 88 { 89 struct uhci_pci_softc *sc = device_private(self); 90 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 91 pci_chipset_tag_t pc = pa->pa_pc; 92 pcitag_t tag = pa->pa_tag; 93 char const *intrstr; 94 pci_intr_handle_t ih; 95 pcireg_t csr; 96 usbd_status r; 97 int s; 98 char intrbuf[PCI_INTRSTR_LEN]; 99 100 sc->sc.sc_dev = self; 101 sc->sc.sc_bus.hci_private = sc; 102 103 pci_aprint_devinfo(pa, NULL); 104 105 /* Map I/O registers */ 106 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 107 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 108 aprint_error_dev(self, "can't map i/o space\n"); 109 return; 110 } 111 112 /* 113 * Disable interrupts, so we don't get any spurious ones. 114 * Acknowledge all pending interrupts. 115 */ 116 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 117 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 118 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 119 120 sc->sc_pc = pc; 121 sc->sc_tag = tag; 122 sc->sc.sc_bus.dmatag = pa->pa_dmat; 123 124 /* Enable the device. */ 125 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 126 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 127 csr | PCI_COMMAND_MASTER_ENABLE); 128 129 /* Map and establish the interrupt. */ 130 if (pci_intr_map(pa, &ih)) { 131 aprint_error_dev(self, "couldn't map interrupt\n"); 132 return; 133 } 134 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 135 sc->sc_ih = pci_intr_establish(pc, ih, IPL_SCHED, uhci_intr, sc); 136 if (sc->sc_ih == NULL) { 137 aprint_error_dev(self, "couldn't establish interrupt"); 138 if (intrstr != NULL) 139 aprint_error(" at %s", intrstr); 140 aprint_error("\n"); 141 return; 142 } 143 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 144 145 /* 146 * Set LEGSUP register to its default value. 147 * This can re-enable or trigger interrupts, so protect against 148 * them and explicitly disable and ACK them afterwards. 149 */ 150 s = splhardusb(); 151 pci_conf_write(pc, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN); 152 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 153 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 154 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 155 splx(s); 156 157 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 158 case PCI_USBREV_PRE_1_0: 159 sc->sc.sc_bus.usbrev = USBREV_PRE_1_0; 160 break; 161 case PCI_USBREV_1_0: 162 sc->sc.sc_bus.usbrev = USBREV_1_0; 163 break; 164 case PCI_USBREV_1_1: 165 sc->sc.sc_bus.usbrev = USBREV_1_1; 166 break; 167 default: 168 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 169 break; 170 } 171 172 /* Figure out vendor for root hub descriptor. */ 173 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 174 pci_findvendor(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 175 sc->sc.sc_id_vendor); 176 r = uhci_init(&sc->sc); 177 if (r != USBD_NORMAL_COMPLETION) { 178 aprint_error_dev(self, "init failed, error=%d\n", r); 179 return; 180 } 181 sc->sc_initialized = SC_INIT_UHCI; 182 183 #if NEHCI > 0 184 usb_pci_add(&sc->sc_pci, pa, self); 185 #endif 186 187 if (!pmf_device_register(self, uhci_suspend, uhci_pci_resume)) 188 aprint_error_dev(self, "couldn't establish power handler\n"); 189 else 190 sc->sc_initialized |= SC_INIT_PMF; 191 192 /* Attach usb device. */ 193 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 194 } 195 196 static int 197 uhci_pci_detach(device_t self, int flags) 198 { 199 struct uhci_pci_softc *sc = device_private(self); 200 int rv; 201 202 if (sc->sc_initialized & SC_INIT_UHCI) { 203 rv = uhci_detach(&sc->sc, flags); 204 if (rv) 205 return (rv); 206 } 207 208 if (sc->sc_initialized & SC_INIT_PMF) 209 pmf_device_deregister(self); 210 211 /* disable interrupts and acknowledge any pending */ 212 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 213 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 214 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 215 216 if (sc->sc_ih != NULL) { 217 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 218 sc->sc_ih = NULL; 219 } 220 if (sc->sc.sc_size) { 221 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 222 sc->sc.sc_size = 0; 223 } 224 #if NEHCI > 0 225 usb_pci_rem(&sc->sc_pci); 226 #endif 227 return (0); 228 } 229 230 static bool 231 uhci_pci_resume(device_t dv, const pmf_qual_t *qual) 232 { 233 struct uhci_pci_softc *sc = device_private(dv); 234 235 /* Set LEGSUP register to its default value. */ 236 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGSUP, 237 PCI_LEGSUP_USBPIRQDEN); 238 239 return uhci_resume(dv, qual); 240 } 241 242 CFATTACH_DECL3_NEW(uhci_pci, sizeof(struct uhci_pci_softc), 243 uhci_pci_match, uhci_pci_attach, uhci_pci_detach, uhci_activate, 244 NULL, uhci_childdet, DVF_DETACH_SHUTDOWN); 245