1 /* $NetBSD: uhci_pci.c,v 1.67 2022/06/29 15:37:25 mlelstv Exp $ */
2
3 /*
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net) at
9 * Carlstedt Research & Technology.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: uhci_pci.c,v 1.67 2022/06/29 15:37:25 mlelstv Exp $");
35
36 #include "ehci.h"
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/device.h>
42 #include <sys/proc.h>
43 #include <sys/queue.h>
44
45 #include <sys/bus.h>
46
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/usb_pci.h>
49
50 #include <dev/usb/usb.h>
51 #include <dev/usb/usbdi.h>
52 #include <dev/usb/usbdivar.h>
53 #include <dev/usb/usb_mem.h>
54
55 #include <dev/usb/uhcireg.h>
56 #include <dev/usb/uhcivar.h>
57
58 static bool uhci_pci_resume(device_t, const pmf_qual_t *);
59
60 struct uhci_pci_softc {
61 uhci_softc_t sc;
62 #if NEHCI > 0
63 struct usb_pci sc_pci;
64 #endif
65 pci_chipset_tag_t sc_pc;
66 pcitag_t sc_tag;
67 void *sc_ih; /* interrupt vectoring */
68 unsigned sc_initialized;
69 #define SC_INIT_UHCI 1
70 #define SC_INIT_PMF 2
71 #define SC_INIT_MAPPED 4
72 };
73
74 static int
uhci_pci_match(device_t parent,cfdata_t match,void * aux)75 uhci_pci_match(device_t parent, cfdata_t match, void *aux)
76 {
77 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
78
79 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
80 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
81 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_UHCI)
82 return 1;
83
84 return 0;
85 }
86
87 static void
uhci_pci_attach(device_t parent,device_t self,void * aux)88 uhci_pci_attach(device_t parent, device_t self, void *aux)
89 {
90 struct uhci_pci_softc *sc = device_private(self);
91 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
92 pci_chipset_tag_t pc = pa->pa_pc;
93 pcitag_t tag = pa->pa_tag;
94 char const *intrstr;
95 pci_intr_handle_t *ih;
96 pcireg_t csr;
97 int s;
98 char intrbuf[PCI_INTRSTR_LEN];
99
100 sc->sc.sc_dev = self;
101 sc->sc.sc_bus.ub_hcpriv = sc;
102
103 pci_aprint_devinfo(pa, NULL);
104
105 /* Map I/O registers */
106 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
107 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
108 aprint_error_dev(self, "can't map i/o space\n");
109 return;
110 }
111 sc->sc_initialized = SC_INIT_MAPPED;
112
113 /*
114 * Disable interrupts, so we don't get any spurious ones.
115 * Acknowledge all pending interrupts.
116 */
117 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0);
118 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS,
119 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS));
120
121 sc->sc_pc = pc;
122 sc->sc_tag = tag;
123 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
124
125 /* Enable the device. */
126 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
127 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
128 csr | PCI_COMMAND_MASTER_ENABLE);
129
130 /* Map and establish the interrupt. */
131 if (pci_intr_alloc(pa, &ih, NULL, 0) != 0) {
132 aprint_error_dev(self, "couldn't map interrupt\n");
133 return;
134 }
135 intrstr = pci_intr_string(pc, ih[0], intrbuf, sizeof(intrbuf));
136 sc->sc_ih = pci_intr_establish_xname(pc, ih[0], IPL_USB, uhci_intr, sc,
137 device_xname(self));
138 if (sc->sc_ih == NULL) {
139 aprint_error_dev(self, "couldn't establish interrupt");
140 if (intrstr != NULL)
141 aprint_error(" at %s", intrstr);
142 aprint_error("\n");
143 return;
144 }
145 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
146
147 /*
148 * Set LEGSUP register to its default value.
149 * This can re-enable or trigger interrupts, so protect against
150 * them and explicitly disable and ACK them afterwards.
151 */
152 s = splhardusb();
153 pci_conf_write(pc, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN);
154 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0);
155 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS,
156 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS));
157 splx(s);
158
159 switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
160 case PCI_USBREV_PRE_1_0:
161 sc->sc.sc_bus.ub_revision = USBREV_PRE_1_0;
162 break;
163 case PCI_USBREV_1_0:
164 sc->sc.sc_bus.ub_revision = USBREV_1_0;
165 break;
166 case PCI_USBREV_1_1:
167 sc->sc.sc_bus.ub_revision = USBREV_1_1;
168 break;
169 default:
170 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
171 break;
172 }
173
174 int err = uhci_init(&sc->sc);
175 if (err) {
176 aprint_error_dev(self, "init failed, error=%d\n", err);
177 return;
178 }
179 sc->sc_initialized |= SC_INIT_UHCI;
180
181 #if NEHCI > 0
182 usb_pci_add(&sc->sc_pci, pa, self);
183 #endif
184
185 if (!pmf_device_register(self, uhci_suspend, uhci_pci_resume))
186 aprint_error_dev(self, "couldn't establish power handler\n");
187 else
188 sc->sc_initialized |= SC_INIT_PMF;
189
190 /* Attach usb device. */
191 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint,
192 CFARGS_NONE);
193 }
194
195 static int
uhci_pci_detach(device_t self,int flags)196 uhci_pci_detach(device_t self, int flags)
197 {
198 struct uhci_pci_softc *sc = device_private(self);
199 int rv;
200
201 if (sc->sc_initialized & SC_INIT_UHCI) {
202 rv = uhci_detach(&sc->sc, flags);
203 if (rv)
204 return rv;
205 }
206
207 if (sc->sc_initialized & SC_INIT_PMF)
208 pmf_device_deregister(self);
209
210 /* disable interrupts and acknowledge any pending */
211 if (sc->sc_initialized & SC_INIT_MAPPED) {
212 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0);
213 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS,
214 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS));
215 }
216 sc->sc_initialized = 0;
217
218 if (sc->sc_ih != NULL) {
219 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
220 sc->sc_ih = NULL;
221 }
222 if (sc->sc.sc_size) {
223 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
224 sc->sc.sc_size = 0;
225 }
226 #if NEHCI > 0
227 usb_pci_rem(&sc->sc_pci);
228 #endif
229 return 0;
230 }
231
232 static bool
uhci_pci_resume(device_t dv,const pmf_qual_t * qual)233 uhci_pci_resume(device_t dv, const pmf_qual_t *qual)
234 {
235 struct uhci_pci_softc *sc = device_private(dv);
236
237 /* Set LEGSUP register to its default value. */
238 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGSUP,
239 PCI_LEGSUP_USBPIRQDEN);
240
241 return uhci_resume(dv, qual);
242 }
243
244 CFATTACH_DECL3_NEW(uhci_pci, sizeof(struct uhci_pci_softc),
245 uhci_pci_match, uhci_pci_attach, uhci_pci_detach, uhci_activate,
246 NULL, uhci_childdet, DVF_DETACH_SHUTDOWN);
247