1 /* $NetBSD: uhci_pci.c,v 1.55 2012/06/10 06:15:53 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart@augustsson.net) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: uhci_pci.c,v 1.55 2012/06/10 06:15:53 mrg Exp $"); 35 36 #include "ehci.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/proc.h> 43 #include <sys/queue.h> 44 45 #include <sys/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/usb_pci.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 #include <dev/usb/usbdivar.h> 53 #include <dev/usb/usb_mem.h> 54 55 #include <dev/usb/uhcireg.h> 56 #include <dev/usb/uhcivar.h> 57 58 static bool uhci_pci_resume(device_t, const pmf_qual_t *); 59 60 struct uhci_pci_softc { 61 uhci_softc_t sc; 62 #if NEHCI > 0 63 struct usb_pci sc_pci; 64 #endif 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_tag; 67 void *sc_ih; /* interrupt vectoring */ 68 }; 69 70 static int 71 uhci_pci_match(device_t parent, cfdata_t match, void *aux) 72 { 73 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 74 75 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 76 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 77 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_UHCI) 78 return (1); 79 80 return (0); 81 } 82 83 static void 84 uhci_pci_attach(device_t parent, device_t self, void *aux) 85 { 86 struct uhci_pci_softc *sc = device_private(self); 87 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 88 pci_chipset_tag_t pc = pa->pa_pc; 89 pcitag_t tag = pa->pa_tag; 90 char const *intrstr; 91 pci_intr_handle_t ih; 92 pcireg_t csr; 93 const char *vendor; 94 usbd_status r; 95 int s; 96 97 sc->sc.sc_dev = self; 98 sc->sc.sc_bus.hci_private = sc; 99 100 pci_aprint_devinfo(pa, NULL); 101 102 /* Map I/O registers */ 103 if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 104 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 105 aprint_error_dev(self, "can't map i/o space\n"); 106 return; 107 } 108 109 /* 110 * Disable interrupts, so we don't get any spurious ones. 111 * Acknowledge all pending interrupts. 112 */ 113 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 114 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 115 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 116 117 sc->sc_pc = pc; 118 sc->sc_tag = tag; 119 sc->sc.sc_bus.dmatag = pa->pa_dmat; 120 121 /* Enable the device. */ 122 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 123 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 124 csr | PCI_COMMAND_MASTER_ENABLE); 125 126 /* Map and establish the interrupt. */ 127 if (pci_intr_map(pa, &ih)) { 128 aprint_error_dev(self, "couldn't map interrupt\n"); 129 return; 130 } 131 intrstr = pci_intr_string(pc, ih); 132 sc->sc_ih = pci_intr_establish(pc, ih, IPL_SCHED, uhci_intr, sc); 133 if (sc->sc_ih == NULL) { 134 aprint_error_dev(self, "couldn't establish interrupt"); 135 if (intrstr != NULL) 136 aprint_error(" at %s", intrstr); 137 aprint_error("\n"); 138 return; 139 } 140 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 141 142 /* 143 * Set LEGSUP register to its default value. 144 * This can re-enable or trigger interrupts, so protect against 145 * them and explicitly disable and ACK them afterwards. 146 */ 147 s = splhardusb(); 148 pci_conf_write(pc, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN); 149 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 150 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 151 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 152 splx(s); 153 154 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 155 case PCI_USBREV_PRE_1_0: 156 sc->sc.sc_bus.usbrev = USBREV_PRE_1_0; 157 break; 158 case PCI_USBREV_1_0: 159 sc->sc.sc_bus.usbrev = USBREV_1_0; 160 break; 161 case PCI_USBREV_1_1: 162 sc->sc.sc_bus.usbrev = USBREV_1_1; 163 break; 164 default: 165 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 166 break; 167 } 168 169 /* Figure out vendor for root hub descriptor. */ 170 vendor = pci_findvendor(pa->pa_id); 171 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 172 if (vendor) 173 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 174 else 175 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 176 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 177 178 r = uhci_init(&sc->sc); 179 if (r != USBD_NORMAL_COMPLETION) { 180 aprint_error_dev(self, "init failed, error=%d\n", r); 181 return; 182 } 183 184 #if NEHCI > 0 185 usb_pci_add(&sc->sc_pci, pa, self); 186 #endif 187 188 if (!pmf_device_register(self, uhci_suspend, uhci_pci_resume)) 189 aprint_error_dev(self, "couldn't establish power handler\n"); 190 191 /* Attach usb device. */ 192 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 193 } 194 195 static int 196 uhci_pci_detach(device_t self, int flags) 197 { 198 struct uhci_pci_softc *sc = device_private(self); 199 int rv; 200 201 rv = uhci_detach(&sc->sc, flags); 202 if (rv) 203 return (rv); 204 205 pmf_device_deregister(self); 206 207 /* disable interrupts and acknowledge any pending */ 208 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); 209 bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_STS, 210 bus_space_read_2(sc->sc.iot, sc->sc.ioh, UHCI_STS)); 211 212 if (sc->sc_ih != NULL) { 213 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 214 sc->sc_ih = NULL; 215 } 216 if (sc->sc.sc_size) { 217 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 218 sc->sc.sc_size = 0; 219 } 220 #if NEHCI > 0 221 usb_pci_rem(&sc->sc_pci); 222 #endif 223 return (0); 224 } 225 226 static bool 227 uhci_pci_resume(device_t dv, const pmf_qual_t *qual) 228 { 229 struct uhci_pci_softc *sc = device_private(dv); 230 231 /* Set LEGSUP register to its default value. */ 232 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_LEGSUP, 233 PCI_LEGSUP_USBPIRQDEN); 234 235 return uhci_resume(dv, qual); 236 } 237 238 CFATTACH_DECL3_NEW(uhci_pci, sizeof(struct uhci_pci_softc), 239 uhci_pci_match, uhci_pci_attach, uhci_pci_detach, uhci_activate, 240 NULL, uhci_childdet, DVF_DETACH_SHUTDOWN); 241