1 /* $NetBSD: mvpex.c,v 1.22 2021/08/07 16:19:13 thorpej Exp $ */
2 /*
3 * Copyright (c) 2008 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: mvpex.c,v 1.22 2021/08/07 16:19:13 thorpej Exp $");
30
31 #include "opt_pci.h"
32 #include "pci.h"
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/errno.h>
38 #include <sys/evcnt.h>
39 #include <sys/malloc.h>
40 #include <sys/systm.h>
41
42 #include <prop/proplib.h>
43
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pciconf.h>
47
48 #include <dev/marvell/mvpexreg.h>
49 #include <dev/marvell/mvpexvar.h>
50 #include <dev/marvell/marvellreg.h>
51 #include <dev/marvell/marvellvar.h>
52
53 #include <machine/pci_machdep.h>
54
55 #include "locators.h"
56
57
58 static int mvpex_match(device_t, struct cfdata *, void *);
59 static void mvpex_attach(device_t, device_t, void *);
60
61 static int mvpex_intr(void *);
62
63 static void mvpex_init(struct mvpex_softc *, enum marvell_tags *);
64 #if 0 /* shall move to pchb(4)? */
65 static void mvpex_barinit(struct mvpex_softc *);
66 static int mvpex_wininit(struct mvpex_softc *, int, int, int, int, uint32_t *,
67 uint32_t *);
68 #else
69 static void mvpex_wininit(struct mvpex_softc *, enum marvell_tags *);
70 #endif
71 #if NPCI > 0
72 static void mvpex_pci_config(struct mvpex_softc *, bus_space_tag_t,
73 bus_space_tag_t, bus_dma_tag_t, pci_chipset_tag_t,
74 u_long, u_long, u_long, u_long, int);
75 #endif
76
77 enum marvell_tags *mvpex_bar2_tags;
78
79 CFATTACH_DECL_NEW(mvpex_gt, sizeof(struct mvpex_softc),
80 mvpex_match, mvpex_attach, NULL, NULL);
81 CFATTACH_DECL_NEW(mvpex_mbus, sizeof(struct mvpex_softc),
82 mvpex_match, mvpex_attach, NULL, NULL);
83
84
85 /* ARGSUSED */
86 static int
mvpex_match(device_t parent,struct cfdata * match,void * aux)87 mvpex_match(device_t parent, struct cfdata *match, void *aux)
88 {
89 struct marvell_attach_args *mva = aux;
90
91 if (strcmp(mva->mva_name, match->cf_name) != 0)
92 return 0;
93 if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
94 mva->mva_irq == MVA_IRQ_DEFAULT)
95 return 0;
96
97 mva->mva_size = MVPEX_SIZE;
98 return 1;
99 }
100
101 /* ARGSUSED */
102 static void
mvpex_attach(device_t parent,device_t self,void * aux)103 mvpex_attach(device_t parent, device_t self, void *aux)
104 {
105 struct mvpex_softc *sc = device_private(self);
106 struct marvell_attach_args *mva = aux;
107 #if NPCI > 0
108 prop_dictionary_t dict = device_properties(self);
109 prop_object_t pc, iot, memt;
110 pci_chipset_tag_t mvpex_chipset;
111 bus_space_tag_t mvpex_io_bs_tag, mvpex_mem_bs_tag;
112 uint64_t iostart = 0, ioend = 0, memstart = 0, memend = 0;
113 uint32_t cl_size = 0;
114 int i;
115 #endif
116
117 aprint_normal(": Marvell PCI Express Interface\n");
118 aprint_naive("\n");
119
120 #if NPCI > 0
121 iot = prop_dictionary_get(dict, "io-bus-tag");
122 if (iot == NULL) {
123 aprint_error_dev(self, "no io-bus-tag property\n");
124 return;
125 }
126 KASSERT(prop_object_type(iot) == PROP_TYPE_DATA);
127 mvpex_io_bs_tag = __UNCONST(prop_data_data_nocopy(iot));
128 memt = prop_dictionary_get(dict, "mem-bus-tag");
129 if (memt == NULL) {
130 aprint_error_dev(self, "no mem-bus-tag property\n");
131 return;
132 }
133 KASSERT(prop_object_type(memt) == PROP_TYPE_DATA);
134 mvpex_mem_bs_tag = __UNCONST(prop_data_data_nocopy(memt));
135 pc = prop_dictionary_get(dict, "pci-chipset");
136 if (pc == NULL) {
137 aprint_error_dev(self, "no pci-chipset property\n");
138 return;
139 }
140 KASSERT(prop_object_type(pc) == PROP_TYPE_DATA);
141 mvpex_chipset = __UNCONST(prop_data_data_nocopy(pc));
142 #ifdef PCI_NETBSD_CONFIGURE
143 if (!prop_dictionary_get_uint64(dict, "iostart", &iostart)) {
144 aprint_error_dev(self, "no iostart property\n");
145 return;
146 }
147 if (!prop_dictionary_get_uint64(dict, "ioend", &ioend)) {
148 aprint_error_dev(self, "no ioend property\n");
149 return;
150 }
151 if (!prop_dictionary_get_uint64(dict, "memstart", &memstart)) {
152 aprint_error_dev(self, "no memstart property\n");
153 return;
154 }
155 if (!prop_dictionary_get_uint64(dict, "memend", &memend)) {
156 aprint_error_dev(self, "no memend property\n");
157 return;
158 }
159 if (!prop_dictionary_get_uint32(dict, "cache-line-size", &cl_size)) {
160 aprint_error_dev(self, "no cache-line-size property\n");
161 return;
162 }
163 #endif
164 #endif
165
166 sc->sc_dev = self;
167 sc->sc_model = mva->mva_model;
168 sc->sc_rev = mva->mva_revision;
169 sc->sc_offset = mva->mva_offset;
170 sc->sc_iot = mva->mva_iot;
171
172 /* Map I/O registers for mvpex */
173 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
174 mva->mva_size, &sc->sc_ioh)) {
175 aprint_error_dev(self, "can't map registers\n");
176 return;
177 }
178 mvpex_init(sc, mva->mva_tags);
179
180 /* XXX: looks seem good to specify level IPL_VM. */
181 marvell_intr_establish(mva->mva_irq, IPL_VM, mvpex_intr, sc);
182
183 #if NPCI > 0
184 for (i = 0; i < PCI_INTERRUPT_PIN_MAX; i++) {
185 sc->sc_intrtab[i].intr_pin = PCI_INTERRUPT_PIN_A + i;
186 sc->sc_intrtab[i].intr_refcnt = 0;
187 LIST_INIT(&sc->sc_intrtab[i].intr_list);
188 }
189
190 mvpex_pci_config(sc, mvpex_io_bs_tag, mvpex_mem_bs_tag, mva->mva_dmat,
191 mvpex_chipset, iostart, ioend, memstart, memend, cl_size);
192 #endif
193 }
194
195 static int
mvpex_intr(void * arg)196 mvpex_intr(void *arg)
197 {
198 struct mvpex_softc *sc = (struct mvpex_softc *)arg;
199 struct mvpex_intrhand *ih;
200 struct mvpex_intrtab *intrtab;
201 uint32_t ic, im;
202 int handled = 0, pin, rv, i, s;
203
204 for (;;) {
205 ic = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC);
206 im = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM);
207 ic &= im;
208
209 if (!ic)
210 break;
211
212 for (i = 0, pin = PCI_INTERRUPT_PIN_A;
213 i < PCI_INTERRUPT_PIN_MAX; pin++, i++) {
214 if ((ic & MVPEX_I_PIN(pin)) == 0)
215 continue;
216
217 intrtab = &sc->sc_intrtab[i];
218 LIST_FOREACH(ih, &intrtab->intr_list, ih_q) {
219 s = _splraise(ih->ih_type);
220 rv = (*ih->ih_func)(ih->ih_arg);
221 splx(s);
222 if (rv) {
223 ih->ih_evcnt.ev_count++;
224 handled++;
225 }
226 }
227 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC,
228 ~MVPEX_I_PIN(pin));
229 }
230 }
231
232 return handled;
233 }
234
235
236 static void
mvpex_init(struct mvpex_softc * sc,enum marvell_tags * tags)237 mvpex_init(struct mvpex_softc *sc, enum marvell_tags *tags)
238 {
239 uint32_t reg;
240 int window;
241
242 /*
243 * First implement Guideline (GL# PCI Express-2) Wrong Default Value
244 * to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1
245 * and 88F5281-B0
246 */
247 /* Write the read command */
248 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, 0x80820000);
249 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0x1b00);
250 /* Prepare new data for write */
251 reg &= ~0x7; /* Clear bits [2:0] */
252 reg |= 0x4; /* Set the new value */
253 reg &= ~0x80000000; /* Set "write" command */
254 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, reg);
255
256 for (window = 0; window < MVPEX_NWINDOW; window++)
257 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0);
258
259 #if 0 /* shall move to pchb(4)? */
260 mvpex_barinit(sc);
261 #else
262 mvpex_wininit(sc, tags);
263 #endif
264
265 /* Clear Interrupt Cause and Mask registers */
266 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IC, 0);
267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, 0);
268
269 /* now wait 60 ns to be sure the link is valid (spec compliant) */
270 delay(1);
271 }
272
273 #if 0
274 static int
275 mvpex_wininit(struct mvpex_softc *sc, int window, int tbegin, int tend,
276 int barmap, uint32_t *barbase, uint32_t *barsize)
277 {
278 uint32_t target, attr, base, size;
279 int targetid;
280
281 for (targetid = tbegin; targetid <= tend && window < MVPEX_NWINDOW;
282 targetid++) {
283 if (orion_target(targetid, &target, &attr, &base, &size) == -1)
284 continue;
285 if (size == 0)
286 continue;
287
288 if (base < *barbase)
289 *barbase = base;
290 *barsize += size;
291
292 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window),
293 MVPEX_WC_WINEN |
294 barmap |
295 MVPEX_WC_TARGET(target) |
296 MVPEX_WC_ATTR(attr) |
297 MVPEX_WC_SIZE(size));
298 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window),
299 MVPEX_WB_BASE(base));
300 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0);
301 window++;
302 }
303
304 return window;
305 }
306
307 /* shall move to pchb(4)? */
308 static void
309 mvpex_barinit(struct mvpex_softc *sc)
310 {
311 const uint32_t barflag =
312 PCI_MAPREG_MEM_PREFETCHABLE_MASK | PCI_MAPREG_MEM_TYPE_64BIT;
313 uint32_t base, size;
314 int window = 0;
315
316 marvell_winparams_by_tag(device_parent(sc->sc_dev),
317 ORION_TARGETID_INTERNALREG, NULL, NULL, &base, &size);
318 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNAL,
319 barflag | (base & MVPEX_BAR0INTERNAL_MASK));
320 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR0INTERNALH, 0);
321
322 base = size = 0;
323 window = mvpex_wininit(sc, window, ORION_TARGETID_SDRAM_CS0,
324 ORION_TARGETID_SDRAM_CS3, MVPEX_WC_BARMAP_BAR1, &base, &size);
325 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1,
326 barflag | (base & MVPEX_BAR_MASK));
327 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1H, 0);
328 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR1C,
329 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN);
330
331 #if 0
332 base = size = 0;
333 if (sc->sc_model == MARVELL_ORION_1_88F1181)
334 window = mvpex_wininit(sc, window, ORION_TARGETID_FLASH_CS,
335 ORION_TARGETID_DEVICE_BOOTCS,
336 MVPEX_WC_BARMAP_BAR2, &base, &size);
337 else {
338 window = mvpex_wininit(sc, window,
339 ORION_TARGETID_DEVICE_CS0, ORION_TARGETID_DEVICE_CS2,
340 MVPEX_WC_BARMAP_BAR2, &base, &size);
341 window = mvpex_wininit(sc, window,
342 ORION_TARGETID_DEVICE_BOOTCS, ORION_TARGETID_DEVICE_BOOTCS,
343 MVPEX_WC_BARMAP_BAR2, &base, &size);
344 }
345 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2,
346 barflag | (base & MVPEX_BAR_MASK));
347 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2H, 0);
348 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C,
349 MVPEX_BARC_BARSIZE(size) | MVPEX_BARC_BAREN);
350 #else
351 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_BAR2C, 0);
352 #endif
353 }
354 #else
355 static void
mvpex_wininit(struct mvpex_softc * sc,enum marvell_tags * tags)356 mvpex_wininit(struct mvpex_softc *sc, enum marvell_tags *tags)
357 {
358 device_t pdev = device_parent(sc->sc_dev);
359 uint64_t base;
360 uint32_t size, bar;
361 int target, attr, window, rv, i, j;
362
363 for (window = 0, i = 0;
364 tags[i] != MARVELL_TAG_UNDEFINED && window < MVPEX_NWINDOW; i++) {
365 rv = marvell_winparams_by_tag(pdev, tags[i],
366 &target, &attr, &base, &size);
367 if (rv != 0 || size == 0)
368 continue;
369
370 if (base > 0xffffffffULL) {
371 aprint_error_dev(sc->sc_dev,
372 "tag %d address 0x%llx not support\n",
373 tags[i], base);
374 continue;
375 }
376
377 bar = MVPEX_WC_BARMAP_BAR1;
378 if (mvpex_bar2_tags != NULL)
379 for (j = 0; mvpex_bar2_tags[j] != MARVELL_TAG_UNDEFINED;
380 j++) {
381 if (mvpex_bar2_tags[j] != tags[i])
382 continue;
383 bar = MVPEX_WC_BARMAP_BAR2;
384 break;
385 }
386
387 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window),
388 MVPEX_WC_WINEN |
389 bar |
390 MVPEX_WC_TARGET(target) |
391 MVPEX_WC_ATTR(attr) |
392 MVPEX_WC_SIZE(size));
393 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WB(window),
394 MVPEX_WB_BASE(base));
395 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WR(window), 0);
396 window++;
397 }
398 for ( ; window < MVPEX_NWINDOW; window++)
399 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_WC(window), 0);
400 }
401 #endif
402
403 #if NPCI > 0
404 static void
mvpex_pci_config(struct mvpex_softc * sc,bus_space_tag_t iot,bus_space_tag_t memt,bus_dma_tag_t dmat,pci_chipset_tag_t pc,u_long iostart,u_long ioend,u_long memstart,u_long memend,int cacheline_size)405 mvpex_pci_config(struct mvpex_softc *sc, bus_space_tag_t iot,
406 bus_space_tag_t memt, bus_dma_tag_t dmat, pci_chipset_tag_t pc,
407 u_long iostart, u_long ioend, u_long memstart, u_long memend,
408 int cacheline_size)
409 {
410 struct pcibus_attach_args pba;
411 uint32_t stat;
412
413 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT);
414
415 #ifdef PCI_NETBSD_CONFIGURE
416 struct pciconf_resources *pcires = pciconf_resource_init();
417
418 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
419 iostart, (ioend - iostart) + 1);
420 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
421 memstart, (memend - memstart) + 1);
422
423 pci_configure_bus(pc, pcires,
424 MVPEX_STAT_PEXBUSNUM(stat), cacheline_size);
425
426 pciconf_resource_fini(pcires);
427 #endif
428
429 pba.pba_iot = iot;
430 pba.pba_memt = memt;
431 pba.pba_dmat = dmat;
432 pba.pba_dmat64 = NULL;
433 pba.pba_pc = pc;
434 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
435 pba.pba_bus = MVPEX_STAT_PEXBUSNUM(stat);
436 pba.pba_bridgetag = NULL;
437 config_found(sc->sc_dev, &pba, NULL, CFARGS_NONE);
438 }
439
440
441 /*
442 * PCI-Express CPU dependent code
443 */
444
445 /* ARGSUSED */
446 void
mvpex_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)447 mvpex_attach_hook(device_t parent, device_t self,
448 struct pcibus_attach_args *pba)
449 {
450
451 /* Nothing */
452 }
453
454 /*
455 * Bit map for configuration register:
456 * [31] ConfigEn
457 * [30:28] Reserved
458 * [27:24] ExtRegNum (PCI Express only)
459 * [23:16] BusNum
460 * [15:11] DevNum
461 * [10: 8] FunctNum
462 * [ 7: 2] RegNum
463 * [ 1: 0] reserved
464 */
465
466 /* ARGSUSED */
467 int
mvpex_bus_maxdevs(void * v,int busno)468 mvpex_bus_maxdevs(void *v, int busno)
469 {
470
471 return 32; /* 32 device/bus */
472 }
473
474 /* ARGSUSED */
475 pcitag_t
mvpex_make_tag(void * v,int bus,int dev,int func)476 mvpex_make_tag(void *v, int bus, int dev, int func)
477 {
478
479 return (bus << 16) | (dev << 11) | (func << 8);
480 }
481
482 /* ARGSUSED */
483 void
mvpex_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)484 mvpex_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
485 {
486
487 if (bp != NULL)
488 *bp = (tag >> 16) & 0xff;
489 if (dp != NULL)
490 *dp = (tag >> 11) & 0x1f;
491 if (fp != NULL)
492 *fp = (tag >> 8) & 0x07;
493 }
494
495 pcireg_t
mvpex_conf_read(void * v,pcitag_t tag,int reg)496 mvpex_conf_read(void *v, pcitag_t tag, int reg)
497 {
498 struct mvpex_softc *sc = v;
499 pcireg_t addr, pci_cs;
500 uint32_t stat;
501 int bus, dev, func, pexbus, pexdev;
502
503 if ((unsigned int)reg >= PCI_EXTCONF_SIZE)
504 return -1;
505
506 mvpex_decompose_tag(v, tag, &bus, &dev, &func);
507
508 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT);
509 pexbus = MVPEX_STAT_PEXBUSNUM(stat);
510 pexdev = MVPEX_STAT_PEXDEVNUM(stat);
511 if (bus != pexbus || dev != pexdev)
512 if (stat & MVPEX_STAT_DLDOWN)
513 return -1;
514
515 if (bus == pexbus) {
516 if (pexdev == 0) {
517 if (dev != 1 && dev != pexdev)
518 return -1;
519 } else {
520 if (dev != 0 && dev != pexdev)
521 return -1;
522 }
523 if (func != 0)
524 return -1;
525 }
526
527 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc);
528
529 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA,
530 addr | MVPEX_CA_CONFIGEN);
531 if ((addr | MVPEX_CA_CONFIGEN) !=
532 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA))
533 return -1;
534
535 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
536 PCI_COMMAND_STATUS_REG);
537 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
538 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT);
539
540 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD);
541 }
542
543 void
mvpex_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)544 mvpex_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
545 {
546 struct mvpex_softc *sc = v;
547 pcireg_t addr;
548 uint32_t stat;
549 int bus, dev, func, pexbus, pexdev;
550
551 if ((unsigned int)reg >= PCI_EXTCONF_SIZE)
552 return;
553
554 mvpex_decompose_tag(v, tag, &bus, &dev, &func);
555
556 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT);
557 pexbus = MVPEX_STAT_PEXBUSNUM(stat);
558 pexdev = MVPEX_STAT_PEXDEVNUM(stat);
559 if (bus != pexbus || dev != pexdev)
560 if (stat & MVPEX_STAT_DLDOWN)
561 return;
562
563 if (bus == pexbus) {
564 if (pexdev == 0) {
565 if (dev != 1 && dev != pexdev)
566 return;
567 } else {
568 if (dev != 0 && dev != pexdev)
569 return;
570 }
571 if (func != 0)
572 return;
573 }
574
575 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc);
576
577 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA,
578 addr | MVPEX_CA_CONFIGEN);
579 if ((addr | MVPEX_CA_CONFIGEN) !=
580 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA))
581 return;
582
583 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD, data);
584 }
585
586 /* ARGSUSED */
587 int
mvpex_conf_hook(void * v,int bus,int dev,int func,pcireg_t id)588 mvpex_conf_hook(void *v, int bus, int dev, int func, pcireg_t id)
589 {
590
591 if (bus == 0 && dev == 0) /* don't configure GT */
592 return 0;
593
594 /*
595 * Do not configure PCI Express root complex on MV78460 - avoid
596 * setting up IO and memory windows.
597 * XXX: should also avoid that other Aramadas.
598 */
599 else if ((dev == 0) && (PCI_PRODUCT(id) == MARVELL_ARMADAXP_MV78460))
600 return 0;
601
602 return PCI_CONF_DEFAULT;
603 }
604
605 int
mvpex_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)606 mvpex_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
607 {
608
609 switch (pa->pa_intrpin) {
610 case PCI_INTERRUPT_PIN_A:
611 case PCI_INTERRUPT_PIN_B:
612 case PCI_INTERRUPT_PIN_C:
613 case PCI_INTERRUPT_PIN_D:
614 *ihp = pa->pa_intrpin;
615 return 0;
616 }
617 return -1;
618 }
619
620 /* ARGSUSED */
621 const char *
mvpex_intr_string(void * v,pci_intr_handle_t pin,char * buf,size_t len)622 mvpex_intr_string(void *v, pci_intr_handle_t pin, char *buf, size_t len)
623 {
624 switch (pin) {
625 case PCI_INTERRUPT_PIN_A:
626 case PCI_INTERRUPT_PIN_B:
627 case PCI_INTERRUPT_PIN_C:
628 case PCI_INTERRUPT_PIN_D:
629 break;
630
631 default:
632 return NULL;
633 }
634 snprintf(buf, len, "interrupt pin INT%c#", (char)('A' - 1 + pin));
635
636 return buf;
637 }
638
639 /* ARGSUSED */
640 const struct evcnt *
mvpex_intr_evcnt(void * v,pci_intr_handle_t pin)641 mvpex_intr_evcnt(void *v, pci_intr_handle_t pin)
642 {
643
644 return NULL;
645 }
646
647 /*
648 * XXXX: Shall these functions use mutex(9) instead of spl(9)?
649 * MV78200 and MV64360 and after supports SMP.
650 */
651
652 /* ARGSUSED */
653 void *
mvpex_intr_establish(void * v,pci_intr_handle_t pin,int ipl,int (* intrhand)(void *),void * intrarg,const char * xname)654 mvpex_intr_establish(void *v, pci_intr_handle_t pin, int ipl,
655 int (*intrhand)(void *), void *intrarg, const char *xname)
656 {
657 struct mvpex_softc *sc = (struct mvpex_softc *)v;
658 struct mvpex_intrtab *intrtab;
659 struct mvpex_intrhand *pexih;
660 uint32_t mask;
661 int ih = pin - 1, s;
662
663 intrtab = &sc->sc_intrtab[ih];
664
665 KASSERT(pin == intrtab->intr_pin);
666
667 pexih = malloc(sizeof(*pexih), M_DEVBUF, M_WAITOK);
668 pexih->ih_func = intrhand;
669 pexih->ih_arg = intrarg;
670 pexih->ih_type = ipl;
671 pexih->ih_intrtab = intrtab;
672 mvpex_intr_string(v, pin, pexih->ih_evname, sizeof(pexih->ih_evname));
673 evcnt_attach_dynamic(&pexih->ih_evcnt, EVCNT_TYPE_INTR, NULL,
674 device_xname(sc->sc_dev), pexih->ih_evname);
675
676 s = splhigh();
677
678 /* First, link it into the tables. */
679 LIST_INSERT_HEAD(&intrtab->intr_list, pexih, ih_q);
680
681 /* Now enable it. */
682 if (intrtab->intr_refcnt++ == 0) {
683 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM);
684 mask |= MVPEX_I_PIN(intrtab->intr_pin);
685 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask);
686 }
687
688 splx(s);
689
690 return pexih;
691 }
692
693 void
mvpex_intr_disestablish(void * v,void * ih)694 mvpex_intr_disestablish(void *v, void *ih)
695 {
696 struct mvpex_softc *sc = (struct mvpex_softc *)v;
697 struct mvpex_intrtab *intrtab;
698 struct mvpex_intrhand *pexih = ih;
699 uint32_t mask;
700 int s;
701
702 evcnt_detach(&pexih->ih_evcnt);
703
704 intrtab = pexih->ih_intrtab;
705
706 s = splhigh();
707
708 /*
709 * First, remove it from the table.
710 */
711 LIST_REMOVE(pexih, ih_q);
712
713 /* Now, disable it, if there is nothing remaining on the list. */
714 if (intrtab->intr_refcnt-- == 1) {
715 mask = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM);
716 mask &= ~MVPEX_I_PIN(intrtab->intr_pin);
717 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_IM, mask);
718 }
719 splx(s);
720
721 free(pexih, M_DEVBUF);
722 }
723 #endif /* NPCI > 0 */
724