1 /* $NetBSD: rkpmic.c,v 1.14 2021/08/07 16:19:11 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: rkpmic.c,v 1.14 2021/08/07 16:19:11 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/device.h>
36 #include <sys/conf.h>
37 #include <sys/bus.h>
38 #include <sys/kmem.h>
39
40 #include <dev/clock_subr.h>
41
42 #include <dev/i2c/i2cvar.h>
43
44 #include <dev/clk/clk_backend.h>
45
46 #include <dev/fdt/fdtvar.h>
47
48 #define SECONDS_REG 0x00
49 #define MINUTES_REG 0x01
50 #define HOURS_REG 0x02
51 #define DAYS_REG 0x03
52 #define MONTHS_REG 0x04
53 #define YEARS_REG 0x05
54 #define WEEKS_REG 0x06
55
56 #define RTC_CTRL_REG 0x10
57 #define RTC_CTRL_READSEL __BIT(7)
58 #define RTC_CTRL_GET_TIME __BIT(6)
59 #define RTC_CTRL_SET_32_COUNTER __BIT(5)
60 #define RTC_CTRL_TEST_MODE __BIT(4)
61 #define RTC_CTRL_AMPM_MODE __BIT(3)
62 #define RTC_CTRL_AUTO_COMP __BIT(2)
63 #define RTC_CTRL_ROUND_30S __BIT(1)
64 #define RTC_CTRL_STOP_RTC __BIT(0)
65
66 #define RTC_INT_REG 0x12
67 #define RTC_COMP_LSB_REG 0x13
68 #define RTC_COMP_MSB_REG 0x14
69 #define CHIP_NAME_REG 0x17
70 #define CHIP_VER_REG 0x18
71
72 #define CLK32OUT_REG 0x20
73 #define CLK32OUT_CLKOUT2_EN __BIT(0)
74
75 #define DEVCTRL_REG 0x4b
76 #define DEVCTRL_DEV_OFF_RST __BIT(3)
77
78 struct rkpmic_ctrl {
79 const char * name;
80 uint8_t enable_reg;
81 uint8_t enable_mask;
82 uint8_t vsel_reg;
83 uint8_t vsel_mask;
84 u_int base;
85 u_int step;
86 u_int flags;
87 #define F_ENABLE_WRITE_MASK 0x00
88 };
89
90 struct rkpmic_config {
91 const char * name;
92 const struct rkpmic_ctrl *ctrl;
93 u_int nctrl;
94
95 u_int poweroff_reg;
96 u_int poweroff_mask;
97 };
98
99 static const struct rkpmic_ctrl rk805_ctrls[] = {
100 /* DCDC */
101 { .name = "DCDC_REG1", .flags = F_ENABLE_WRITE_MASK,
102 .enable_reg = 0x23, .enable_mask = __BIT(0),
103 .vsel_reg = 0x2f, .vsel_mask = __BITS(5,0),
104 .base = 712500, .step = 12500 },
105 { .name = "DCDC_REG2", .flags = F_ENABLE_WRITE_MASK,
106 .enable_reg = 0x23, .enable_mask = __BIT(1),
107 .vsel_reg = 0x33, .vsel_mask = __BITS(5,0),
108 .base = 712500, .step = 12500 },
109 { .name = "DCDC_REG3", .flags = F_ENABLE_WRITE_MASK,
110 .enable_reg = 0x23, .enable_mask = __BIT(2) },
111 { .name = "DCDC_REG4", .flags = F_ENABLE_WRITE_MASK,
112 .enable_reg = 0x23, .enable_mask = __BIT(3),
113 .vsel_reg = 0x38, .vsel_mask = __BITS(3,0),
114 .base = 800000, .step = 100000 },
115
116 /* LDO */
117 { .name = "LDO_REG1", .flags = F_ENABLE_WRITE_MASK,
118 .enable_reg = 0x27, .enable_mask = __BIT(0),
119 .vsel_reg = 0x3b, .vsel_mask = __BITS(4,0),
120 .base = 800000, .step = 100000 },
121 { .name = "LDO_REG2", .flags = F_ENABLE_WRITE_MASK,
122 .enable_reg = 0x27, .enable_mask = __BIT(1),
123 .vsel_reg = 0x3d, .vsel_mask = __BITS(4,0),
124 .base = 800000, .step = 100000 },
125 { .name = "LDO_REG3", .flags = F_ENABLE_WRITE_MASK,
126 .enable_reg = 0x27, .enable_mask = __BIT(2),
127 .vsel_reg = 0x3f, .vsel_mask = __BITS(4,0),
128 .base = 800000, .step = 100000 },
129 };
130
131 static const struct rkpmic_config rk805_config = {
132 .name = "RK805",
133 .ctrl = rk805_ctrls,
134 .nctrl = __arraycount(rk805_ctrls),
135 };
136
137 static const struct rkpmic_ctrl rk808_ctrls[] = {
138 /* DCDC */
139 { .name = "DCDC_REG1",
140 .enable_reg = 0x23, .enable_mask = __BIT(0),
141 .vsel_reg = 0x2f, .vsel_mask = __BITS(5,0),
142 .base = 712500, .step = 12500 },
143 { .name = "DCDC_REG2",
144 .enable_reg = 0x23, .enable_mask = __BIT(1),
145 .vsel_reg = 0x33, .vsel_mask = __BITS(5,0),
146 .base = 712500, .step = 12500 },
147 { .name = "DCDC_REG3",
148 .enable_reg = 0x23, .enable_mask = __BIT(2) },
149 { .name = "DCDC_REG4",
150 .enable_reg = 0x23, .enable_mask = __BIT(3),
151 .vsel_reg = 0x38, .vsel_mask = __BITS(3,0),
152 .base = 1800000, .step = 100000 },
153
154 /* LDO */
155 { .name = "LDO_REG1",
156 .enable_reg = 0x24, .enable_mask = __BIT(0),
157 .vsel_reg = 0x3b, .vsel_mask = __BITS(4,0),
158 .base = 1800000, .step = 100000 },
159 { .name = "LDO_REG2",
160 .enable_reg = 0x24, .enable_mask = __BIT(1),
161 .vsel_reg = 0x3d, .vsel_mask = __BITS(4,0),
162 .base = 1800000, .step = 100000 },
163 { .name = "LDO_REG3",
164 .enable_reg = 0x24, .enable_mask = __BIT(2),
165 .vsel_reg = 0x3f, .vsel_mask = __BITS(3,0),
166 .base = 800000, .step = 100000 },
167 { .name = "LDO_REG4",
168 .enable_reg = 0x24, .enable_mask = __BIT(3),
169 .vsel_reg = 0x41, .vsel_mask = __BITS(4,0),
170 .base = 1800000, .step = 100000 },
171 { .name = "LDO_REG5",
172 .enable_reg = 0x24, .enable_mask = __BIT(4),
173 .vsel_reg = 0x43, .vsel_mask = __BITS(4,0),
174 .base = 1800000, .step = 100000 },
175 { .name = "LDO_REG6",
176 .enable_reg = 0x24, .enable_mask = __BIT(5),
177 .vsel_reg = 0x45, .vsel_mask = __BITS(4,0),
178 .base = 800000, .step = 100000 },
179 { .name = "LDO_REG7",
180 .enable_reg = 0x24, .enable_mask = __BIT(6),
181 .vsel_reg = 0x47, .vsel_mask = __BITS(4,0),
182 .base = 800000, .step = 100000 },
183 { .name = "LDO_REG8",
184 .enable_reg = 0x24, .enable_mask = __BIT(7),
185 .vsel_reg = 0x49, .vsel_mask = __BITS(4,0),
186 .base = 1800000, .step = 100000 },
187
188 /* SWITCH */
189 { .name = "SWITCH_REG1",
190 .enable_reg = 0x23, .enable_mask = __BIT(5) },
191 { .name = "SWITCH_REG2",
192 .enable_reg = 0x23, .enable_mask = __BIT(6) },
193 };
194
195 static const struct rkpmic_config rk808_config = {
196 .name = "RK808",
197 .ctrl = rk808_ctrls,
198 .nctrl = __arraycount(rk808_ctrls),
199 .poweroff_reg = DEVCTRL_REG,
200 .poweroff_mask = DEVCTRL_DEV_OFF_RST,
201 };
202
203 struct rkpmic_softc;
204
205 struct rkpmic_clk {
206 struct clk base;
207 };
208
209 struct rkpmic_softc {
210 device_t sc_dev;
211 i2c_tag_t sc_i2c;
212 i2c_addr_t sc_addr;
213 int sc_phandle;
214 struct todr_chip_handle sc_todr;
215 const struct rkpmic_config *sc_conf;
216 struct clk_domain sc_clkdom;
217 struct rkpmic_clk sc_clk[2];
218 };
219
220 struct rkreg_softc {
221 device_t sc_dev;
222 struct rkpmic_softc *sc_pmic;
223 const struct rkpmic_ctrl *sc_ctrl;
224 };
225
226 struct rkreg_attach_args {
227 const struct rkpmic_ctrl *reg_ctrl;
228 int reg_phandle;
229 };
230
231 static const struct device_compatible_entry compat_data[] = {
232 { .compat = "rockchip,rk805", .data = &rk805_config },
233 { .compat = "rockchip,rk808", .data = &rk808_config },
234 DEVICE_COMPAT_EOL
235 };
236
237 static uint8_t
rkpmic_read(struct rkpmic_softc * sc,uint8_t reg,int flags)238 rkpmic_read(struct rkpmic_softc *sc, uint8_t reg, int flags)
239 {
240 uint8_t val = 0;
241 int error;
242
243 error = iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, &val, flags);
244 if (error != 0)
245 device_printf(sc->sc_dev, "error reading reg %#x: %d\n", reg, error);
246
247 return val;
248 }
249
250 static void
rkpmic_write(struct rkpmic_softc * sc,uint8_t reg,uint8_t val,int flags)251 rkpmic_write(struct rkpmic_softc *sc, uint8_t reg, uint8_t val, int flags)
252 {
253 int error;
254
255 error = iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, flags);
256 if (error != 0)
257 device_printf(sc->sc_dev, "error writing reg %#x: %d\n", reg, error);
258 }
259
260 #define I2C_READ(sc, reg) rkpmic_read((sc), (reg), 0)
261 #define I2C_WRITE(sc, reg, val) rkpmic_write((sc), (reg), (val), 0)
262 #define I2C_LOCK(sc) iic_acquire_bus((sc)->sc_i2c, 0)
263 #define I2C_UNLOCK(sc) iic_release_bus((sc)->sc_i2c, 0)
264
265 static int
rkpmic_todr_settime(todr_chip_handle_t ch,struct clock_ymdhms * dt)266 rkpmic_todr_settime(todr_chip_handle_t ch, struct clock_ymdhms *dt)
267 {
268 struct rkpmic_softc * const sc = ch->cookie;
269 uint8_t val;
270 int error;
271
272 if (dt->dt_year < 2000 || dt->dt_year >= 2100) {
273 device_printf(sc->sc_dev, "year out of range\n");
274 return EINVAL;
275 }
276
277 if ((error = I2C_LOCK(sc)) != 0)
278 return error;
279
280 /* XXX Fix error reporting. */
281
282 val = I2C_READ(sc, RTC_CTRL_REG);
283 I2C_WRITE(sc, RTC_CTRL_REG, val | RTC_CTRL_STOP_RTC);
284 I2C_WRITE(sc, SECONDS_REG, bintobcd(dt->dt_sec));
285 I2C_WRITE(sc, MINUTES_REG, bintobcd(dt->dt_min));
286 I2C_WRITE(sc, HOURS_REG, bintobcd(dt->dt_hour));
287 I2C_WRITE(sc, DAYS_REG, bintobcd(dt->dt_day));
288 I2C_WRITE(sc, MONTHS_REG, bintobcd(dt->dt_mon));
289 I2C_WRITE(sc, YEARS_REG, bintobcd(dt->dt_year % 100));
290 I2C_WRITE(sc, WEEKS_REG, bintobcd(dt->dt_wday == 0 ? 7 : dt->dt_wday));
291 I2C_WRITE(sc, RTC_CTRL_REG, val);
292 I2C_UNLOCK(sc);
293
294 return 0;
295 }
296
297 static int
rkpmic_todr_gettime(todr_chip_handle_t ch,struct clock_ymdhms * dt)298 rkpmic_todr_gettime(todr_chip_handle_t ch, struct clock_ymdhms *dt)
299 {
300 struct rkpmic_softc * const sc = ch->cookie;
301 uint8_t val;
302 int error;
303
304 if ((error = I2C_LOCK(sc)) != 0)
305 return error;
306
307 /* XXX Fix error reporting. */
308
309 val = I2C_READ(sc, RTC_CTRL_REG);
310 I2C_WRITE(sc, RTC_CTRL_REG, val | RTC_CTRL_GET_TIME | RTC_CTRL_READSEL);
311 delay(1000000 / 32768); /* wait one cycle for shadow regs to latch */
312 I2C_WRITE(sc, RTC_CTRL_REG, val | RTC_CTRL_READSEL);
313 dt->dt_sec = bcdtobin(I2C_READ(sc, SECONDS_REG));
314 dt->dt_min = bcdtobin(I2C_READ(sc, MINUTES_REG));
315 dt->dt_hour = bcdtobin(I2C_READ(sc, HOURS_REG));
316 dt->dt_day = bcdtobin(I2C_READ(sc, DAYS_REG));
317 dt->dt_mon = bcdtobin(I2C_READ(sc, MONTHS_REG));
318 dt->dt_year = 2000 + bcdtobin(I2C_READ(sc, YEARS_REG));
319 dt->dt_wday = bcdtobin(I2C_READ(sc, WEEKS_REG));
320 if (dt->dt_wday == 7)
321 dt->dt_wday = 0;
322 I2C_WRITE(sc, RTC_CTRL_REG, val);
323 I2C_UNLOCK(sc);
324
325 /*
326 * RK808 has a hw bug which makes the 31st of November a valid day.
327 * If we detect the 31st of November we skip ahead one day.
328 * If the system has been turned off during the crossover the clock
329 * will have lost a day. No easy way to detect this. Oh well.
330 */
331 if (dt->dt_mon == 11 && dt->dt_day == 31) {
332 dt->dt_day--;
333 clock_secs_to_ymdhms(clock_ymdhms_to_secs(dt) + 86400, dt);
334 rkpmic_todr_settime(ch, dt);
335 }
336
337 #if 0
338 device_printf(sc->sc_dev, "%04" PRIu64 "-%02u-%02u (%u) %02u:%02u:%02u\n",
339 dt->dt_year, dt->dt_mon, dt->dt_day, dt->dt_wday,
340 dt->dt_hour, dt->dt_min, dt->dt_sec);
341 #endif
342
343 return 0;
344 }
345
346 static struct clk *
rkpmic_clk_decode(device_t dev,int cc_phandle,const void * data,size_t len)347 rkpmic_clk_decode(device_t dev, int cc_phandle, const void *data, size_t len)
348 {
349 struct rkpmic_softc * const sc = device_private(dev);
350
351 if (len != 4)
352 return NULL;
353
354 const u_int id = be32dec(data);
355 if (id >= __arraycount(sc->sc_clk))
356 return NULL;
357
358 return &sc->sc_clk[id].base;
359 }
360
361 static const struct fdtbus_clock_controller_func rkpmic_clk_fdt_funcs = {
362 .decode = rkpmic_clk_decode
363 };
364
365 static struct clk *
rkpmic_clk_get(void * priv,const char * name)366 rkpmic_clk_get(void *priv, const char *name)
367 {
368 struct rkpmic_softc * const sc = priv;
369 u_int n;
370
371 for (n = 0; n < __arraycount(sc->sc_clk); n++) {
372 if (strcmp(name, sc->sc_clk[n].base.name) == 0)
373 return &sc->sc_clk[n].base;
374 }
375
376 return NULL;
377 }
378
379 static u_int
rkpmic_clk_get_rate(void * priv,struct clk * clk)380 rkpmic_clk_get_rate(void *priv, struct clk *clk)
381 {
382 return 32768;
383 }
384
385 static int
rkpmic_clk_enable(void * priv,struct clk * clk)386 rkpmic_clk_enable(void *priv, struct clk *clk)
387 {
388 struct rkpmic_softc * const sc = priv;
389 uint8_t val;
390
391 if (clk != &sc->sc_clk[1].base)
392 return 0;
393
394 I2C_LOCK(sc);
395 val = I2C_READ(sc, CLK32OUT_REG);
396 val |= CLK32OUT_CLKOUT2_EN;
397 I2C_WRITE(sc, CLK32OUT_REG, val);
398 I2C_UNLOCK(sc);
399
400 return 0;
401 }
402
403 static int
rkpmic_clk_disable(void * priv,struct clk * clk)404 rkpmic_clk_disable(void *priv, struct clk *clk)
405 {
406 struct rkpmic_softc * const sc = priv;
407 uint8_t val;
408
409 if (clk != &sc->sc_clk[1].base)
410 return EIO;
411
412 I2C_LOCK(sc);
413 val = I2C_READ(sc, CLK32OUT_REG);
414 val &= ~CLK32OUT_CLKOUT2_EN;
415 I2C_WRITE(sc, CLK32OUT_REG, val);
416 I2C_UNLOCK(sc);
417
418 return 0;
419 }
420
421 static const struct clk_funcs rkpmic_clk_funcs = {
422 .get = rkpmic_clk_get,
423 .get_rate = rkpmic_clk_get_rate,
424 .enable = rkpmic_clk_enable,
425 .disable = rkpmic_clk_disable,
426 };
427
428 static void
rkpmic_power_poweroff(device_t dev)429 rkpmic_power_poweroff(device_t dev)
430 {
431 struct rkpmic_softc * const sc = device_private(dev);
432 uint8_t val;
433
434 delay(1000000);
435
436 I2C_LOCK(sc);
437 val = I2C_READ(sc, sc->sc_conf->poweroff_reg);
438 val |= sc->sc_conf->poweroff_mask;
439 I2C_WRITE(sc, sc->sc_conf->poweroff_reg, val);
440 I2C_UNLOCK(sc);
441 }
442
443 static struct fdtbus_power_controller_func rkpmic_power_funcs = {
444 .poweroff = rkpmic_power_poweroff,
445 };
446
447 static int
rkpmic_match(device_t parent,cfdata_t match,void * aux)448 rkpmic_match(device_t parent, cfdata_t match, void *aux)
449 {
450 struct i2c_attach_args *ia = aux;
451 int match_result;
452
453 if (iic_use_direct_match(ia, match, compat_data, &match_result))
454 return match_result;
455
456 return 0;
457 }
458
459 static void
rkpmic_attach(device_t parent,device_t self,void * aux)460 rkpmic_attach(device_t parent, device_t self, void *aux)
461 {
462 struct rkpmic_softc * const sc = device_private(self);
463 struct i2c_attach_args *ia = aux;
464 struct rkreg_attach_args raa;
465 const struct device_compatible_entry *entry;
466 int child, regulators;
467 u_int chipid, n;
468
469 entry = iic_compatible_lookup(ia, compat_data);
470 KASSERT(entry != NULL);
471
472 sc->sc_dev = self;
473 sc->sc_i2c = ia->ia_tag;
474 sc->sc_addr = ia->ia_addr;
475 sc->sc_phandle = ia->ia_cookie;
476 sc->sc_conf = entry->data;
477
478 memset(&sc->sc_todr, 0, sizeof(sc->sc_todr));
479 sc->sc_todr.cookie = sc;
480 sc->sc_todr.todr_gettime_ymdhms = rkpmic_todr_gettime;
481 sc->sc_todr.todr_settime_ymdhms = rkpmic_todr_settime;
482
483 aprint_naive("\n");
484 aprint_normal(": %s Power Management and Real Time Clock IC\n", sc->sc_conf->name);
485
486 I2C_LOCK(sc);
487 chipid = I2C_READ(sc, CHIP_NAME_REG) << 8;
488 chipid |= I2C_READ(sc, CHIP_VER_REG);
489 aprint_debug_dev(self, "Chip ID 0x%04x\n", chipid);
490 I2C_WRITE(sc, RTC_CTRL_REG, 0x0);
491 I2C_WRITE(sc, RTC_INT_REG, 0);
492 I2C_WRITE(sc, RTC_COMP_LSB_REG, 0);
493 I2C_WRITE(sc, RTC_COMP_MSB_REG, 0);
494 I2C_UNLOCK(sc);
495
496 fdtbus_todr_attach(self, sc->sc_phandle, &sc->sc_todr);
497
498 sc->sc_clkdom.name = device_xname(self);
499 sc->sc_clkdom.funcs = &rkpmic_clk_funcs;
500 sc->sc_clkdom.priv = sc;
501
502 sc->sc_clk[0].base.domain = &sc->sc_clkdom;
503 sc->sc_clk[0].base.name = "xin32k";
504 clk_attach(&sc->sc_clk[0].base);
505
506 sc->sc_clk[1].base.domain = &sc->sc_clkdom;
507 sc->sc_clk[1].base.name = "clkout2";
508 clk_attach(&sc->sc_clk[1].base);
509
510 fdtbus_register_clock_controller(self, sc->sc_phandle,
511 &rkpmic_clk_fdt_funcs);
512
513 if (of_hasprop(sc->sc_phandle, "rockchip,system-power-controller") &&
514 sc->sc_conf->poweroff_mask != 0)
515 fdtbus_register_power_controller(self, sc->sc_phandle,
516 &rkpmic_power_funcs);
517
518 regulators = of_find_firstchild_byname(sc->sc_phandle, "regulators");
519 if (regulators < 0)
520 return;
521
522 for (n = 0; n < sc->sc_conf->nctrl; n++) {
523 child = of_find_firstchild_byname(regulators, sc->sc_conf->ctrl[n].name);
524 if (child < 0)
525 continue;
526 raa.reg_ctrl = &sc->sc_conf->ctrl[n];
527 raa.reg_phandle = child;
528 config_found(self, &raa, NULL, CFARGS_NONE);
529 }
530 }
531
532 static int
rkreg_acquire(device_t dev)533 rkreg_acquire(device_t dev)
534 {
535 return 0;
536 }
537
538 static void
rkreg_release(device_t dev)539 rkreg_release(device_t dev)
540 {
541 }
542
543 static int
rkreg_enable(device_t dev,bool enable)544 rkreg_enable(device_t dev, bool enable)
545 {
546 struct rkreg_softc * const sc = device_private(dev);
547 const struct rkpmic_ctrl *c = sc->sc_ctrl;
548 uint8_t val;
549
550 if (!c->enable_mask)
551 return EINVAL;
552
553 I2C_LOCK(sc->sc_pmic);
554 if (c->flags & F_ENABLE_WRITE_MASK)
555 val |= c->enable_mask << 4;
556 else
557 val = I2C_READ(sc->sc_pmic, c->enable_reg);
558 if (enable)
559 val |= c->enable_mask;
560 else
561 val &= ~c->enable_mask;
562 I2C_WRITE(sc->sc_pmic, c->enable_reg, val);
563 I2C_UNLOCK(sc->sc_pmic);
564
565 return 0;
566 }
567
568 static int
rkreg_set_voltage(device_t dev,u_int min_uvol,u_int max_uvol)569 rkreg_set_voltage(device_t dev, u_int min_uvol, u_int max_uvol)
570 {
571 struct rkreg_softc * const sc = device_private(dev);
572 const struct rkpmic_ctrl *c = sc->sc_ctrl;
573 uint8_t val;
574 u_int vsel;
575
576 if (!c->vsel_mask)
577 return EINVAL;
578
579 if (min_uvol < c->base)
580 return ERANGE;
581
582 vsel = (min_uvol - c->base) / c->step;
583 if (vsel > __SHIFTOUT_MASK(c->vsel_mask))
584 return ERANGE;
585
586 I2C_LOCK(sc->sc_pmic);
587 val = I2C_READ(sc->sc_pmic, c->vsel_reg);
588 val &= ~c->vsel_mask;
589 val |= __SHIFTIN(vsel, c->vsel_mask);
590 I2C_WRITE(sc->sc_pmic, c->vsel_reg, val);
591 I2C_UNLOCK(sc->sc_pmic);
592
593 return 0;
594 }
595
596 static int
rkreg_get_voltage(device_t dev,u_int * puvol)597 rkreg_get_voltage(device_t dev, u_int *puvol)
598 {
599 struct rkreg_softc * const sc = device_private(dev);
600 const struct rkpmic_ctrl *c = sc->sc_ctrl;
601 uint8_t val;
602
603 if (!c->vsel_mask)
604 return EINVAL;
605
606 I2C_LOCK(sc->sc_pmic);
607 val = I2C_READ(sc->sc_pmic, c->vsel_reg);
608 I2C_UNLOCK(sc->sc_pmic);
609
610 *puvol = __SHIFTOUT(val, c->vsel_mask) * c->step + c->base;
611
612 return 0;
613 }
614
615 static struct fdtbus_regulator_controller_func rkreg_funcs = {
616 .acquire = rkreg_acquire,
617 .release = rkreg_release,
618 .enable = rkreg_enable,
619 .set_voltage = rkreg_set_voltage,
620 .get_voltage = rkreg_get_voltage,
621 };
622
623 static int
rkreg_match(device_t parent,cfdata_t match,void * aux)624 rkreg_match(device_t parent, cfdata_t match, void *aux)
625 {
626 return 1;
627 }
628
629 static void
rkreg_attach(device_t parent,device_t self,void * aux)630 rkreg_attach(device_t parent, device_t self, void *aux)
631 {
632 struct rkreg_softc * const sc = device_private(self);
633 struct rkreg_attach_args *raa = aux;
634 const int phandle = raa->reg_phandle;
635 const char *name;
636
637 sc->sc_dev = self;
638 sc->sc_pmic = device_private(parent);
639 sc->sc_ctrl = raa->reg_ctrl;
640
641 fdtbus_register_regulator_controller(self, phandle,
642 &rkreg_funcs);
643
644 aprint_naive("\n");
645 name = fdtbus_get_string(phandle, "regulator-name");
646 if (!name)
647 name = fdtbus_get_string(phandle, "name");
648 aprint_normal(": %s\n", name);
649 }
650
651 CFATTACH_DECL_NEW(rkpmic, sizeof(struct rkpmic_softc),
652 rkpmic_match, rkpmic_attach, NULL, NULL);
653
654 CFATTACH_DECL_NEW(rkreg, sizeof(struct rkreg_softc),
655 rkreg_match, rkreg_attach, NULL, NULL);
656