1 /* $NetBSD: dbcool.c,v 1.65 2024/05/18 00:02:04 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Goyette
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * a driver for the dbCool(tm) family of environmental controllers
34 *
35 * Data sheets for the various supported chips are available at
36 *
37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF
38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF
39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF
40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF
41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF
42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF
43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF
44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF
45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF
46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF
47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf
48 *
49 * (URLs are correct as of October 5, 2008)
50 */
51
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.65 2024/05/18 00:02:04 thorpej Exp $");
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/kernel.h>
58 #include <sys/device.h>
59 #include <sys/sysctl.h>
60 #include <sys/module.h>
61
62 #include <dev/i2c/dbcool_var.h>
63 #include <dev/i2c/dbcool_reg.h>
64
65 /* Config interface */
66 static int dbcool_match(device_t, cfdata_t, void *);
67 static void dbcool_attach(device_t, device_t, void *);
68 static int dbcool_detach(device_t, int);
69
70 /* Device attributes */
71 static int dbcool_supply_voltage(struct dbcool_softc *);
72 static bool dbcool_islocked(struct dbcool_softc *);
73
74 /* Sensor read functions */
75 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *);
76 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t);
77 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool);
78 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool);
79
80 /* Sensor get/set limit functions */
81 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *,
82 sysmon_envsys_lim_t *, uint32_t *);
83 static void dbcool_get_temp_limits(struct dbcool_softc *, int,
84 sysmon_envsys_lim_t *, uint32_t *);
85 static void dbcool_get_volt_limits(struct dbcool_softc *, int,
86 sysmon_envsys_lim_t *, uint32_t *);
87 static void dbcool_get_fan_limits(struct dbcool_softc *, int,
88 sysmon_envsys_lim_t *, uint32_t *);
89
90 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *,
91 sysmon_envsys_lim_t *, uint32_t *);
92 static void dbcool_set_temp_limits(struct dbcool_softc *, int,
93 sysmon_envsys_lim_t *, uint32_t *);
94 static void dbcool_set_volt_limits(struct dbcool_softc *, int,
95 sysmon_envsys_lim_t *, uint32_t *);
96 static void dbcool_set_fan_limits(struct dbcool_softc *, int,
97 sysmon_envsys_lim_t *, uint32_t *);
98
99 /* SYSCTL Helpers */
100 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup);
101 static int sysctl_dbcool_temp(SYSCTLFN_PROTO);
102 static int sysctl_adm1030_temp(SYSCTLFN_PROTO);
103 static int sysctl_adm1030_trange(SYSCTLFN_PROTO);
104 static int sysctl_dbcool_duty(SYSCTLFN_PROTO);
105 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO);
106 static int sysctl_dbcool_slope(SYSCTLFN_PROTO);
107 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO);
108
109 /* Set-up subroutines */
110 static void dbcool_setup_controllers(struct dbcool_softc *);
111 static int dbcool_setup_sensors(struct dbcool_softc *);
112 static int dbcool_attach_sensor(struct dbcool_softc *, int);
113 static int dbcool_attach_temp_control(struct dbcool_softc *, int,
114 struct chip_id *);
115
116 #ifdef DBCOOL_DEBUG
117 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO);
118 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO);
119 #endif /* DBCOOL_DEBUG */
120
121 /*
122 * Descriptions for SYSCTL entries
123 */
124 struct dbc_sysctl_info {
125 const char *name;
126 const char *desc;
127 bool lockable;
128 int (*helper)(SYSCTLFN_PROTO);
129 };
130
131 static struct dbc_sysctl_info dbc_sysctl_table[] = {
132 /*
133 * The first several entries must remain in the same order as the
134 * corresponding entries in enum dbc_pwm_params
135 */
136 { "behavior", "operating behavior and temp selector",
137 true, sysctl_dbcool_behavior },
138 { "min_duty", "minimum fan controller PWM duty cycle",
139 true, sysctl_dbcool_duty },
140 { "max_duty", "maximum fan controller PWM duty cycle",
141 true, sysctl_dbcool_duty },
142 { "cur_duty", "current fan controller PWM duty cycle",
143 false, sysctl_dbcool_duty },
144
145 /*
146 * The rest of these should be in the order in which they
147 * are to be stored in the sysctl tree; the table index is
148 * used as the high-order bits of the sysctl_num to maintain
149 * the sequence.
150 *
151 * If you rearrange the order of these items, be sure to
152 * update the sysctl_index in the XXX_sensor_table[] for
153 * the various chips!
154 */
155 { "Trange", "temp slope/range to reach 100% duty cycle",
156 true, sysctl_dbcool_slope },
157 { "Tmin", "temp at which to start fan controller",
158 true, sysctl_dbcool_temp },
159 { "Ttherm", "temp at which THERM is asserted",
160 true, sysctl_dbcool_temp },
161 { "Thyst", "temp hysteresis for stopping fan controller",
162 true, sysctl_dbcool_thyst },
163 { "Tmin", "temp at which to start fan controller",
164 true, sysctl_adm1030_temp },
165 { "Trange", "temp slope/range to reach 100% duty cycle",
166 true, sysctl_adm1030_trange },
167 };
168
169 static const char *dbc_sensor_names[] = {
170 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1",
171 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5",
172 "V5", "V12", "Vtt", "Imon", "VID"
173 };
174
175 /*
176 * Following table derived from product data-sheets
177 */
178 static int64_t nominal_voltages[] = {
179 -1, /* Vcc can be either 3.3 or 5.0V
180 at 3/4 scale */
181 2249939, /* Vccp 2.25V 3/4 scale */
182 2497436, /* 2.5VIN 2.5V 3/4 scale */
183 5002466, /* 5VIN 5V 3/4 scale */
184 12000000, /* 12VIN 12V 3/4 scale */
185 1690809, /* Vtt, Imon 2.25V full scale */
186 1689600, /* AIN1, AIN2 2.25V full scale */
187 0
188 };
189
190 /*
191 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx,
192 * nom-voltage-index
193 */
194 struct dbcool_sensor ADT7490_sensor_table[] = {
195 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
196 DBCOOL_LOCAL_HIGHLIM,
197 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
198 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
199 DBCOOL_REMOTE1_HIGHLIM,
200 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
201 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
202 DBCOOL_REMOTE2_HIGHLIM,
203 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
204 { DBC_VOLT, { DBCOOL_VCCP,
205 DBCOOL_VCCP_HIGHLIM,
206 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
207 { DBC_VOLT, { DBCOOL_VCC,
208 DBCOOL_VCC_HIGHLIM,
209 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
210 { DBC_VOLT, { DBCOOL_25VIN,
211 DBCOOL_25VIN_HIGHLIM,
212 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
213 { DBC_VOLT, { DBCOOL_5VIN,
214 DBCOOL_5VIN_HIGHLIM,
215 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
216 { DBC_VOLT, { DBCOOL_12VIN,
217 DBCOOL_12VIN_HIGHLIM,
218 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
219 { DBC_VOLT, { DBCOOL_VTT,
220 DBCOOL_VTT_HIGHLIM,
221 DBCOOL_VTT_LOWLIM }, 14, 0, 5 },
222 { DBC_VOLT, { DBCOOL_IMON,
223 DBCOOL_IMON_HIGHLIM,
224 DBCOOL_IMON_LOWLIM }, 15, 0, 5 },
225 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
226 DBCOOL_NO_REG,
227 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
228 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
229 DBCOOL_NO_REG,
230 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
231 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
232 DBCOOL_NO_REG,
233 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
234 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
235 DBCOOL_NO_REG,
236 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
237 { DBC_VID, { DBCOOL_VID_REG,
238 DBCOOL_NO_REG,
239 DBCOOL_NO_REG }, 16, 0, 0 },
240 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
241 DBCOOL_NO_REG,
242 DBCOOL_NO_REG }, 0, 5, 0 },
243 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
244 DBCOOL_NO_REG,
245 DBCOOL_NO_REG }, 0, 6, 0 },
246 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
247 DBCOOL_NO_REG,
248 DBCOOL_NO_REG }, 0, 7, 0 },
249 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
250 DBCOOL_NO_REG,
251 DBCOOL_NO_REG }, 1, 5, 0 },
252 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
253 DBCOOL_NO_REG,
254 DBCOOL_NO_REG }, 1, 6, 0 },
255 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
256 DBCOOL_NO_REG,
257 DBCOOL_NO_REG }, 1, 7, 0 },
258 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
259 DBCOOL_NO_REG,
260 DBCOOL_NO_REG }, 2, 5, 0 },
261 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
262 DBCOOL_NO_REG,
263 DBCOOL_NO_REG }, 2, 6, 0 },
264 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
265 DBCOOL_NO_REG,
266 DBCOOL_NO_REG }, 2, 7, 0 },
267 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
268 };
269
270 struct dbcool_sensor ADT7476_sensor_table[] = {
271 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
272 DBCOOL_LOCAL_HIGHLIM,
273 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
274 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
275 DBCOOL_REMOTE1_HIGHLIM,
276 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
277 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
278 DBCOOL_REMOTE2_HIGHLIM,
279 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
280 { DBC_VOLT, { DBCOOL_VCCP,
281 DBCOOL_VCCP_HIGHLIM,
282 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
283 { DBC_VOLT, { DBCOOL_VCC,
284 DBCOOL_VCC_HIGHLIM,
285 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
286 { DBC_VOLT, { DBCOOL_25VIN,
287 DBCOOL_25VIN_HIGHLIM,
288 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
289 { DBC_VOLT, { DBCOOL_5VIN,
290 DBCOOL_5VIN_HIGHLIM,
291 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
292 { DBC_VOLT, { DBCOOL_12VIN,
293 DBCOOL_12VIN_HIGHLIM,
294 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
295 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
296 DBCOOL_NO_REG,
297 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
298 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
299 DBCOOL_NO_REG,
300 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
301 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
302 DBCOOL_NO_REG,
303 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
304 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
305 DBCOOL_NO_REG,
306 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
307 { DBC_VID, { DBCOOL_VID_REG,
308 DBCOOL_NO_REG,
309 DBCOOL_NO_REG }, 16, 0, 0 },
310 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
311 DBCOOL_NO_REG,
312 DBCOOL_NO_REG }, 0, 5, 0 },
313 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
314 DBCOOL_NO_REG,
315 DBCOOL_NO_REG }, 0, 6, 0 },
316 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
317 DBCOOL_NO_REG,
318 DBCOOL_NO_REG }, 0, 7, 0 },
319 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
320 DBCOOL_NO_REG,
321 DBCOOL_NO_REG }, 1, 5, 0 },
322 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
323 DBCOOL_NO_REG,
324 DBCOOL_NO_REG }, 1, 6, 0 },
325 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
326 DBCOOL_NO_REG,
327 DBCOOL_NO_REG }, 1, 7, 0 },
328 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
329 DBCOOL_NO_REG,
330 DBCOOL_NO_REG }, 2, 5, 0 },
331 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
332 DBCOOL_NO_REG,
333 DBCOOL_NO_REG }, 2, 6, 0 },
334 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
335 DBCOOL_NO_REG,
336 DBCOOL_NO_REG }, 2, 7, 0 },
337 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
338 };
339
340 struct dbcool_sensor ADT7475_sensor_table[] = {
341 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
342 DBCOOL_LOCAL_HIGHLIM,
343 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
344 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
345 DBCOOL_REMOTE1_HIGHLIM,
346 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
347 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
348 DBCOOL_REMOTE2_HIGHLIM,
349 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
350 { DBC_VOLT, { DBCOOL_VCCP,
351 DBCOOL_VCCP_HIGHLIM,
352 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
353 { DBC_VOLT, { DBCOOL_VCC,
354 DBCOOL_VCC_HIGHLIM,
355 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
356 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
357 DBCOOL_NO_REG,
358 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
359 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
360 DBCOOL_NO_REG,
361 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
362 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
363 DBCOOL_NO_REG,
364 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
365 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
366 DBCOOL_NO_REG,
367 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
368 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
369 DBCOOL_NO_REG,
370 DBCOOL_NO_REG }, 0, 5, 0 },
371 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
372 DBCOOL_NO_REG,
373 DBCOOL_NO_REG }, 0, 6, 0 },
374 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
375 DBCOOL_NO_REG,
376 DBCOOL_NO_REG }, 0, 7, 0 },
377 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
378 DBCOOL_NO_REG,
379 DBCOOL_NO_REG }, 1, 5, 0 },
380 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
381 DBCOOL_NO_REG,
382 DBCOOL_NO_REG }, 1, 6, 0 },
383 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
384 DBCOOL_NO_REG,
385 DBCOOL_NO_REG }, 1, 7, 0 },
386 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
387 DBCOOL_NO_REG,
388 DBCOOL_NO_REG }, 2, 5, 0 },
389 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
390 DBCOOL_NO_REG,
391 DBCOOL_NO_REG }, 2, 6, 0 },
392 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
393 DBCOOL_NO_REG,
394 DBCOOL_NO_REG }, 2, 7, 0 },
395 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
396 };
397
398 /*
399 * The registers of dbcool_power_control must be in the same order as
400 * in enum dbc_pwm_params
401 */
402 struct dbcool_power_control ADT7475_power_table[] = {
403 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY,
404 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY },
405 "fan_control_1" },
406 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY,
407 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY },
408 "fan_control_2" },
409 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY,
410 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY },
411 "fan_control_3" },
412 { { 0, 0, 0, 0 }, NULL }
413 };
414
415 struct dbcool_sensor ADT7466_sensor_table[] = {
416 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB,
417 DBCOOL_ADT7466_LCL_TEMP_HILIM,
418 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 },
419 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB,
420 DBCOOL_ADT7466_REM_TEMP_HILIM,
421 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 },
422 { DBC_VOLT, { DBCOOL_ADT7466_VCC,
423 DBCOOL_ADT7466_VCC_HILIM,
424 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 },
425 { DBC_VOLT, { DBCOOL_ADT7466_AIN1,
426 DBCOOL_ADT7466_AIN1_HILIM,
427 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 },
428 { DBC_VOLT, { DBCOOL_ADT7466_AIN2,
429 DBCOOL_ADT7466_AIN2_HILIM,
430 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 },
431 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB,
432 DBCOOL_NO_REG,
433 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 },
434 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB,
435 DBCOOL_NO_REG,
436 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 },
437 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
438 };
439
440 struct dbcool_sensor ADM1027_sensor_table[] = {
441 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
442 DBCOOL_LOCAL_HIGHLIM,
443 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
444 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
445 DBCOOL_REMOTE1_HIGHLIM,
446 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
447 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
448 DBCOOL_REMOTE2_HIGHLIM,
449 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
450 { DBC_VOLT, { DBCOOL_VCCP,
451 DBCOOL_VCCP_HIGHLIM,
452 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
453 { DBC_VOLT, { DBCOOL_VCC,
454 DBCOOL_VCC_HIGHLIM,
455 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
456 { DBC_VOLT, { DBCOOL_25VIN,
457 DBCOOL_25VIN_HIGHLIM,
458 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
459 { DBC_VOLT, { DBCOOL_5VIN,
460 DBCOOL_5VIN_HIGHLIM,
461 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
462 { DBC_VOLT, { DBCOOL_12VIN,
463 DBCOOL_12VIN_HIGHLIM,
464 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
465 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
466 DBCOOL_NO_REG,
467 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
468 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
469 DBCOOL_NO_REG,
470 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
471 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
472 DBCOOL_NO_REG,
473 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
474 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
475 DBCOOL_NO_REG,
476 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
477 { DBC_VID, { DBCOOL_VID_REG,
478 DBCOOL_NO_REG,
479 DBCOOL_NO_REG }, 16, 0, 0 },
480 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
481 DBCOOL_NO_REG,
482 DBCOOL_NO_REG }, 0, 5, 0 },
483 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
484 DBCOOL_NO_REG,
485 DBCOOL_NO_REG }, 0, 6, 0 },
486 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
487 DBCOOL_NO_REG,
488 DBCOOL_NO_REG }, 0, 7, 0 },
489 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
490 DBCOOL_NO_REG,
491 DBCOOL_NO_REG }, 1, 5, 0 },
492 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
493 DBCOOL_NO_REG,
494 DBCOOL_NO_REG }, 1, 6, 0 },
495 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
496 DBCOOL_NO_REG,
497 DBCOOL_NO_REG }, 1, 7, 0 },
498 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
499 DBCOOL_NO_REG,
500 DBCOOL_NO_REG }, 2, 5, 0 },
501 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
502 DBCOOL_NO_REG,
503 DBCOOL_NO_REG }, 2, 6, 0 },
504 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
505 DBCOOL_NO_REG,
506 DBCOOL_NO_REG }, 2, 7, 0 },
507 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
508 };
509
510 struct dbcool_sensor ADM1030_sensor_table[] = {
511 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP,
512 DBCOOL_ADM1030_L_HI_LIM,
513 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 },
514 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP,
515 DBCOOL_ADM1030_R_HI_LIM,
516 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 },
517 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH,
518 DBCOOL_NO_REG,
519 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 },
520 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN,
521 DBCOOL_NO_REG,
522 DBCOOL_NO_REG }, 0, 8, 0 },
523 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
524 DBCOOL_NO_REG,
525 DBCOOL_NO_REG }, 0, 9, 0 },
526 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
527 DBCOOL_NO_REG,
528 DBCOOL_NO_REG }, 0, 6, 0 },
529 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN,
530 DBCOOL_NO_REG,
531 DBCOOL_NO_REG }, 1, 8, 0 },
532 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
533 DBCOOL_NO_REG,
534 DBCOOL_NO_REG }, 1, 9, 0 },
535 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
536 DBCOOL_NO_REG,
537 DBCOOL_NO_REG }, 1, 6, 0 },
538 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 }
539 };
540
541 struct dbcool_power_control ADM1030_power_table[] = {
542 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG,
543 DBCOOL_ADM1030_FAN_SPEED_CFG },
544 "fan_control_1" },
545 { { 0, 0, 0, 0 }, NULL }
546 };
547
548 struct dbcool_sensor ADM1031_sensor_table[] = {
549 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP,
550 DBCOOL_ADM1030_L_HI_LIM,
551 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 },
552 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP,
553 DBCOOL_ADM1030_R_HI_LIM,
554 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 },
555 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP,
556 DBCOOL_ADM1031_R2_HI_LIM,
557 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 },
558 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH,
559 DBCOOL_NO_REG,
560 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 },
561 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH,
562 DBCOOL_NO_REG,
563 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 },
564 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN,
565 DBCOOL_NO_REG,
566 DBCOOL_NO_REG }, 0, 8, 0 },
567 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
568 DBCOOL_NO_REG,
569 DBCOOL_NO_REG }, 0, 9, 0 },
570 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
571 DBCOOL_NO_REG,
572 DBCOOL_NO_REG }, 0, 6, 0 },
573 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN,
574 DBCOOL_NO_REG,
575 DBCOOL_NO_REG }, 1, 8, 0 },
576 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
577 DBCOOL_NO_REG,
578 DBCOOL_NO_REG }, 1, 9, 0 },
579 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
580 DBCOOL_NO_REG,
581 DBCOOL_NO_REG }, 1, 6, 0 },
582 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN,
583 DBCOOL_NO_REG,
584 DBCOOL_NO_REG }, 2, 8, 0 },
585 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH,
586 DBCOOL_NO_REG,
587 DBCOOL_NO_REG }, 2, 9, 0 },
588 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH,
589 DBCOOL_NO_REG,
590 DBCOOL_NO_REG }, 2, 6, 0 },
591 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 }
592 };
593
594 struct dbcool_power_control ADM1031_power_table[] = {
595 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG,
596 DBCOOL_ADM1030_FAN_SPEED_CFG },
597 "fan_control_1" },
598 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG,
599 DBCOOL_ADM1030_FAN_SPEED_CFG },
600 "fan_control_2" },
601 { { 0, 0, 0, 0 }, NULL }
602 };
603
604 struct dbcool_sensor EMC6D103S_sensor_table[] = {
605 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
606 DBCOOL_LOCAL_HIGHLIM,
607 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
608 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
609 DBCOOL_REMOTE1_HIGHLIM,
610 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
611 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
612 DBCOOL_REMOTE2_HIGHLIM,
613 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
614 { DBC_VOLT, { DBCOOL_VCCP,
615 DBCOOL_VCCP_HIGHLIM,
616 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
617 { DBC_VOLT, { DBCOOL_VCC,
618 DBCOOL_VCC_HIGHLIM,
619 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
620 { DBC_VOLT, { DBCOOL_25VIN,
621 DBCOOL_25VIN_HIGHLIM,
622 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
623 { DBC_VOLT, { DBCOOL_5VIN,
624 DBCOOL_5VIN_HIGHLIM,
625 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
626 { DBC_VOLT, { DBCOOL_12VIN,
627 DBCOOL_12VIN_HIGHLIM,
628 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
629 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
630 DBCOOL_NO_REG,
631 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
632 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
633 DBCOOL_NO_REG,
634 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
635 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
636 DBCOOL_NO_REG,
637 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
638 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
639 DBCOOL_NO_REG,
640 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
641 { DBC_VID, { DBCOOL_VID_REG,
642 DBCOOL_NO_REG,
643 DBCOOL_NO_REG }, 16, 0, 0 },
644 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
645 DBCOOL_NO_REG,
646 DBCOOL_NO_REG }, 0, 5, 0 },
647 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
648 DBCOOL_NO_REG,
649 DBCOOL_NO_REG }, 0, 6, 0 },
650 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
651 DBCOOL_NO_REG,
652 DBCOOL_NO_REG }, 1, 5, 0 },
653 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
654 DBCOOL_NO_REG,
655 DBCOOL_NO_REG }, 1, 6, 0 },
656 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
657 DBCOOL_NO_REG,
658 DBCOOL_NO_REG }, 2, 5, 0 },
659 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
660 DBCOOL_NO_REG,
661 DBCOOL_NO_REG }, 2, 6, 0 },
662 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
663 };
664
665 struct chip_id chip_table[] = {
666 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID,
667 ADT7490_sensor_table, ADT7475_power_table,
668 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI,
669 90000 * 60, "ADT7490" },
670 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff,
671 ADT7476_sensor_table, ADT7475_power_table,
672 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY,
673 90000 * 60, "ADT7476" },
674 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff,
675 ADT7475_sensor_table, ADT7475_power_table,
676 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN,
677 90000 * 60, "ADT7475" },
678 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1,
679 ADT7475_sensor_table, ADT7475_power_table,
680 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN,
681 90000 * 60, "ADT7460/ADT7463" },
682 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2,
683 ADT7475_sensor_table, ADT7475_power_table,
684 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN,
685 90000 * 60, "ADT7463-1" },
686 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff,
687 ADT7476_sensor_table, ADT7475_power_table,
688 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY |
689 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN,
690 90000 * 60, "ADT7467/ADT7468" },
691 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff,
692 ADT7466_sensor_table, NULL,
693 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN,
694 82000 * 60, "ADT7466" },
695 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1,
696 ADM1027_sensor_table, ADT7475_power_table,
697 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN,
698 90000 * 60, "ADT7463" },
699 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2,
700 ADM1027_sensor_table, ADT7475_power_table,
701 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN |
702 DBCFLAG_HAS_VID_SEL,
703 90000 * 60, "ADT7463" },
704 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID,
705 ADM1027_sensor_table, ADT7475_power_table,
706 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER,
707 90000 * 60, "ADM1027" },
708 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff,
709 ADM1030_sensor_table, ADM1030_power_table,
710 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE,
711 11250 * 60, "ADM1030" },
712 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff,
713 ADM1031_sensor_table, ADM1030_power_table,
714 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE,
715 11250 * 60, "ADM1031" },
716 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID,
717 EMC6D103S_sensor_table, ADT7475_power_table,
718 DBCFLAG_4BIT_VER,
719 90000 * 60, "EMC6D103S" },
720 { 0, 0, 0, NULL, NULL, 0, 0, NULL }
721 };
722
723 static const char *behavior[] = {
724 "remote1", "local", "remote2", "full-speed",
725 "disabled", "local+remote2","all-temps", "manual"
726 };
727
728 static char dbcool_cur_behav[16];
729
730 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc),
731 dbcool_match, dbcool_attach, dbcool_detach, NULL);
732
733 static const struct device_compatible_entry compat_data[] = {
734 { .compat = "i2c-adm1031" },
735 { .compat = "adt7467" },
736 { .compat = "adt7460" },
737 { .compat = "adm1030" },
738 DEVICE_COMPAT_EOL
739 };
740
741 int
dbcool_match(device_t parent,cfdata_t cf,void * aux)742 dbcool_match(device_t parent, cfdata_t cf, void *aux)
743 {
744 struct i2c_attach_args *ia = aux;
745 struct dbcool_chipset dc;
746 dc.dc_tag = ia->ia_tag;
747 dc.dc_addr = ia->ia_addr;
748 dc.dc_chip = NULL;
749 dc.dc_readreg = dbcool_readreg;
750 dc.dc_writereg = dbcool_writereg;
751 int match_result;
752
753 if (iic_use_direct_match(ia, cf, compat_data, &match_result))
754 return match_result;
755
756 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR)
757 return 0;
758 if (dbcool_chip_ident(&dc) >= 0)
759 return I2C_MATCH_ADDRESS_AND_PROBE;
760
761 return 0;
762 }
763
764 void
dbcool_attach(device_t parent,device_t self,void * aux)765 dbcool_attach(device_t parent, device_t self, void *aux)
766 {
767 struct dbcool_softc *sc = device_private(self);
768 struct i2c_attach_args *args = aux;
769 uint8_t ver;
770
771 sc->sc_dc.dc_addr = args->ia_addr;
772 sc->sc_dc.dc_tag = args->ia_tag;
773 sc->sc_dc.dc_chip = NULL;
774 sc->sc_dc.dc_readreg = dbcool_readreg;
775 sc->sc_dc.dc_writereg = dbcool_writereg;
776 sc->sc_dev = self;
777 sc->sc_prop = args->ia_prop;
778 prop_object_retain(sc->sc_prop);
779
780 if (dbcool_chip_ident(&sc->sc_dc) < 0 || sc->sc_dc.dc_chip == NULL)
781 panic("could not identify chip at addr %d", args->ia_addr);
782
783 aprint_naive("\n");
784 aprint_normal("\n");
785
786 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG);
787 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER)
788 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID)
789 {
790 aprint_normal_dev(self, "SMSC %s Controller "
791 "(rev 0x%02x, stepping 0x%02x)\n",
792 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f);
793 } else {
794 aprint_normal_dev(self, "%s dBCool(tm) Controller "
795 "(rev 0x%02x, stepping 0x%02x)\n",
796 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f);
797 }
798 else
799 aprint_normal_dev(self, "%s dBCool(tm) Controller "
800 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver);
801
802 sc->sc_sysctl_log = NULL;
803
804 #ifdef _MODULE
805 sysctl_dbcoolsetup(&sc->sc_sysctl_log);
806 #endif
807
808 dbcool_setup(self);
809
810 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume))
811 aprint_error_dev(self, "couldn't establish power handler\n");
812 }
813
814 static int
dbcool_detach(device_t self,int flags)815 dbcool_detach(device_t self, int flags)
816 {
817 struct dbcool_softc *sc = device_private(self);
818
819 pmf_device_deregister(self);
820
821 if (sc->sc_sme != NULL)
822 sysmon_envsys_unregister(sc->sc_sme);
823
824 sysctl_teardown(&sc->sc_sysctl_log);
825
826 return 0;
827 }
828
829 /*
830 * On suspend, we save the state of the SHDN bit, then set it
831 * On resume, we restore the previous state of the SHDN bit (which
832 * we saved in sc_suspend)
833 */
834 static bool
dbcool_do_pmf(device_t dev,const pmf_qual_t * qual,bool suspend)835 dbcool_do_pmf(device_t dev, const pmf_qual_t *qual, bool suspend)
836 {
837 struct dbcool_softc *sc = device_private(dev);
838 uint8_t reg, bit, cfg;
839
840 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0)
841 return true;
842
843 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
844 reg = DBCOOL_ADT7466_CONFIG2;
845 bit = DBCOOL_ADT7466_CFG2_SHDN;
846 } else {
847 reg = DBCOOL_CONFIG2_REG;
848 bit = DBCOOL_CFG2_SHDN;
849 }
850 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
851 if (suspend) {
852 sc->sc_suspend = (cfg & bit) != 0;
853 cfg |= bit;
854 } else {
855 cfg &= sc->sc_suspend ? bit : 0;
856 }
857 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg);
858
859 return true;
860 }
861
862 bool
dbcool_pmf_suspend(device_t dev,const pmf_qual_t * qual)863 dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual)
864 {
865
866 return dbcool_do_pmf(dev, qual, true);
867 }
868
869 bool
dbcool_pmf_resume(device_t dev,const pmf_qual_t * qual)870 dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual)
871 {
872
873 return dbcool_do_pmf(dev, qual, false);
874 }
875
876 uint8_t
dbcool_readreg(struct dbcool_chipset * dc,uint8_t reg)877 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg)
878 {
879 uint8_t data = 0;
880
881 if (iic_acquire_bus(dc->dc_tag, 0) != 0)
882 return data;
883
884 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) {
885 /* ADM1027 doesn't support i2c read_byte protocol */
886 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0)
887 goto bad;
888 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0);
889 } else
890 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data,
891 0);
892
893 bad:
894 iic_release_bus(dc->dc_tag, 0);
895 return data;
896 }
897
898 void
dbcool_writereg(struct dbcool_chipset * dc,uint8_t reg,uint8_t val)899 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val)
900 {
901 if (iic_acquire_bus(dc->dc_tag, 0) != 0)
902 return;
903
904 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0);
905
906 iic_release_bus(dc->dc_tag, 0);
907 }
908
909 static bool
dbcool_islocked(struct dbcool_softc * sc)910 dbcool_islocked(struct dbcool_softc *sc)
911 {
912 uint8_t cfg_reg;
913
914 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
915 return 0;
916
917 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466)
918 cfg_reg = DBCOOL_ADT7466_CONFIG1;
919 else
920 cfg_reg = DBCOOL_CONFIG1_REG;
921
922 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK)
923 return 1;
924 else
925 return 0;
926 }
927
928 static int
dbcool_read_temp(struct dbcool_softc * sc,uint8_t reg,bool extres)929 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres)
930 {
931 uint8_t t1, t2, t3, val, ext = 0;
932 int temp;
933
934 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
935 /*
936 * ADT7466 temps are in strange location
937 */
938 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1);
939 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
940 if (extres)
941 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1);
942 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
943 /*
944 * ADM1030 temps are in their own special place, too
945 */
946 if (extres) {
947 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES);
948 if (reg == DBCOOL_ADM1030_L_TEMP)
949 ext >>= 6;
950 else if (reg == DBCOOL_ADM1031_R2_TEMP)
951 ext >>= 4;
952 else
953 ext >>= 1;
954 ext &= 0x03;
955 }
956 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
957 } else if (extres) {
958 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG);
959
960 /* Read all msb regs to unlatch them */
961 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN);
962 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP);
963 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP);
964 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP);
965 switch (reg) {
966 case DBCOOL_REMOTE1_TEMP:
967 val = t1;
968 ext >>= 2;
969 break;
970 case DBCOOL_LOCAL_TEMP:
971 val = t3;
972 ext >>= 4;
973 break;
974 case DBCOOL_REMOTE2_TEMP:
975 val = t2;
976 ext >>= 6;
977 break;
978 default:
979 val = 0;
980 break;
981 }
982 ext &= 0x03;
983 }
984 else
985 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
986
987 /* Check for invalid temp values */
988 if ((sc->sc_temp_offset == 0 && val == 0x80) ||
989 (sc->sc_temp_offset != 0 && val == 0))
990 return 0;
991
992 /* If using offset mode, adjust, else treat as signed */
993 if (sc->sc_temp_offset) {
994 temp = val;
995 temp -= sc->sc_temp_offset;
996 } else
997 temp = (int8_t)val;
998
999 /* Convert degC to uK and include extended precision bits */
1000 temp *= 1000000;
1001 temp += 250000 * (int)ext;
1002 temp += 273150000U;
1003
1004 return temp;
1005 }
1006
1007 static int
dbcool_read_rpm(struct dbcool_softc * sc,uint8_t reg)1008 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg)
1009 {
1010 int rpm;
1011 uint8_t rpm_lo, rpm_hi;
1012
1013 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1014 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
1015 rpm_hi = (rpm_lo == 0xff)?0xff:0x0;
1016 else
1017 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1);
1018
1019 rpm = (rpm_hi << 8) | rpm_lo;
1020 if (rpm == 0xffff)
1021 return 0; /* 0xffff indicates stalled/failed fan */
1022
1023 /* don't divide by zero */
1024 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm);
1025 }
1026
1027 /* Provide chip's supply voltage, in microvolts */
1028 static int
dbcool_supply_voltage(struct dbcool_softc * sc)1029 dbcool_supply_voltage(struct dbcool_softc *sc)
1030 {
1031 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) {
1032 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc)
1033 return 5002500;
1034 else
1035 return 3300000;
1036 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
1037 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) &
1038 DBCOOL_ADT7466_CFG1_Vcc)
1039 return 5000000;
1040 else
1041 return 3300000;
1042 } else
1043 return 3300000;
1044 }
1045
1046 /*
1047 * Nominal voltages are calculated in microvolts
1048 */
1049 static int
dbcool_read_volt(struct dbcool_softc * sc,uint8_t reg,int nom_idx,bool extres)1050 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres)
1051 {
1052 uint8_t ext = 0, v1, v2, v3, v4, val;
1053 int64_t ret;
1054 int64_t nom;
1055
1056 nom = nominal_voltages[nom_idx];
1057 if (nom < 0)
1058 nom = sc->sc_supply_voltage;
1059
1060 /* ADT7466 voltages are in strange locations with only 8-bits */
1061 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466)
1062 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1063 else
1064 /*
1065 * It's a "normal" dbCool chip - check for regs that
1066 * share extended resolution bits since we have to
1067 * read all the MSB registers to unlatch them.
1068 */
1069 if (!extres)
1070 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1071 else if (reg == DBCOOL_12VIN) {
1072 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03;
1073 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1074 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true);
1075 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) {
1076 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON);
1077 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON);
1078 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT);
1079 if (reg == DBCOOL_IMON) {
1080 val = v1;
1081 ext >>= 6;
1082 } else {
1083 val = v2;
1084 ext >>= 4;
1085 }
1086 ext &= 0x0f;
1087 } else {
1088 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG);
1089 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN);
1090 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP);
1091 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC);
1092 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN);
1093
1094 switch (reg) {
1095 case DBCOOL_25VIN:
1096 val = v1;
1097 break;
1098 case DBCOOL_VCCP:
1099 val = v2;
1100 ext >>= 2;
1101 break;
1102 case DBCOOL_VCC:
1103 val = v3;
1104 ext >>= 4;
1105 break;
1106 case DBCOOL_5VIN:
1107 val = v4;
1108 ext >>= 6;
1109 break;
1110 default:
1111 val = nom = 0;
1112 }
1113 ext &= 0x03;
1114 }
1115
1116 /*
1117 * Scale the nominal value by the 10-bit fraction
1118 *
1119 * Returned value is in microvolts.
1120 */
1121 ret = val;
1122 ret <<= 2;
1123 ret |= ext;
1124 ret = (ret * nom) / 0x300;
1125
1126 return ret;
1127 }
1128
1129 static int
sysctl_dbcool_temp(SYSCTLFN_ARGS)1130 sysctl_dbcool_temp(SYSCTLFN_ARGS)
1131 {
1132 struct sysctlnode node;
1133 struct dbcool_softc *sc;
1134 int reg, error;
1135 uint8_t chipreg;
1136 uint8_t newreg;
1137
1138 node = *rnode;
1139 sc = (struct dbcool_softc *)node.sysctl_data;
1140 chipreg = node.sysctl_num & 0xff;
1141
1142 if (sc->sc_temp_offset) {
1143 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1144 reg -= sc->sc_temp_offset;
1145 } else
1146 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1147
1148 node.sysctl_data = ®
1149 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1150
1151 if (error || newp == NULL)
1152 return error;
1153
1154 /* We were asked to update the value - sanity check before writing */
1155 if (*(int *)node.sysctl_data < -64 ||
1156 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset)
1157 return EINVAL;
1158
1159 newreg = *(int *)node.sysctl_data;
1160 newreg += sc->sc_temp_offset;
1161 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1162 return 0;
1163 }
1164
1165 static int
sysctl_adm1030_temp(SYSCTLFN_ARGS)1166 sysctl_adm1030_temp(SYSCTLFN_ARGS)
1167 {
1168 struct sysctlnode node;
1169 struct dbcool_softc *sc;
1170 int reg, error;
1171 uint8_t chipreg, oldreg, newreg;
1172
1173 node = *rnode;
1174 sc = (struct dbcool_softc *)node.sysctl_data;
1175 chipreg = node.sysctl_num & 0xff;
1176
1177 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1178 reg = (oldreg >> 1) & ~0x03;
1179
1180 node.sysctl_data = ®
1181 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1182
1183 if (error || newp == NULL)
1184 return error;
1185
1186 /* We were asked to update the value - sanity check before writing */
1187 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127)
1188 return EINVAL;
1189
1190 newreg = *(int *)node.sysctl_data;
1191 newreg &= ~0x03;
1192 newreg <<= 1;
1193 newreg |= (oldreg & 0x07);
1194 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1195 return 0;
1196 }
1197
1198 static int
sysctl_adm1030_trange(SYSCTLFN_ARGS)1199 sysctl_adm1030_trange(SYSCTLFN_ARGS)
1200 {
1201 struct sysctlnode node;
1202 struct dbcool_softc *sc;
1203 int reg, error, newval;
1204 uint8_t chipreg, oldreg, newreg;
1205
1206 node = *rnode;
1207 sc = (struct dbcool_softc *)node.sysctl_data;
1208 chipreg = node.sysctl_num & 0xff;
1209
1210 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1211 reg = oldreg & 0x07;
1212
1213 node.sysctl_data = ®
1214 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1215
1216 if (error || newp == NULL)
1217 return error;
1218
1219 /* We were asked to update the value - sanity check before writing */
1220 newval = *(int *)node.sysctl_data;
1221
1222 if (newval == 5)
1223 newreg = 0;
1224 else if (newval == 10)
1225 newreg = 1;
1226 else if (newval == 20)
1227 newreg = 2;
1228 else if (newval == 40)
1229 newreg = 3;
1230 else if (newval == 80)
1231 newreg = 4;
1232 else
1233 return EINVAL;
1234
1235 newreg |= (oldreg & ~0x07);
1236 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1237 return 0;
1238 }
1239
1240 static int
sysctl_dbcool_duty(SYSCTLFN_ARGS)1241 sysctl_dbcool_duty(SYSCTLFN_ARGS)
1242 {
1243 struct sysctlnode node;
1244 struct dbcool_softc *sc;
1245 int reg, error;
1246 uint8_t chipreg, oldreg, newreg;
1247
1248 node = *rnode;
1249 sc = (struct dbcool_softc *)node.sysctl_data;
1250 chipreg = node.sysctl_num & 0xff;
1251
1252 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1253 reg = (uint32_t)oldreg;
1254 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
1255 reg = ((reg & 0x0f) * 100) / 15;
1256 else
1257 reg = (reg * 100) / 255;
1258 node.sysctl_data = ®
1259 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1260
1261 if (error || newp == NULL)
1262 return error;
1263
1264 /* We were asked to update the value - sanity check before writing */
1265 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100)
1266 return EINVAL;
1267
1268 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
1269 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100;
1270 newreg |= oldreg & 0xf0;
1271 } else
1272 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100;
1273 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1274 return 0;
1275 }
1276
1277 static int
sysctl_dbcool_behavior(SYSCTLFN_ARGS)1278 sysctl_dbcool_behavior(SYSCTLFN_ARGS)
1279 {
1280 struct sysctlnode node;
1281 struct dbcool_softc *sc;
1282 int i, reg, error;
1283 uint8_t chipreg, oldreg, newreg;
1284
1285 node = *rnode;
1286 sc = (struct dbcool_softc *)node.sysctl_data;
1287 chipreg = node.sysctl_num & 0xff;
1288
1289 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1290
1291 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
1292 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0)
1293 reg = 4;
1294 else if ((oldreg & 0x80) == 0)
1295 reg = 7;
1296 else if ((oldreg & 0x60) == 0)
1297 reg = 4;
1298 else
1299 reg = 6;
1300 } else
1301 reg = (oldreg >> 5) & 0x07;
1302
1303 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav));
1304 node.sysctl_data = dbcool_cur_behav;
1305 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1306
1307 if (error || newp == NULL)
1308 return error;
1309
1310 /* We were asked to update the value - convert string to value */
1311 newreg = __arraycount(behavior);
1312 for (i = 0; i < __arraycount(behavior); i++)
1313 if (strcmp(node.sysctl_data, behavior[i]) == 0)
1314 break;
1315 if (i >= __arraycount(behavior))
1316 return EINVAL;
1317 newreg = i;
1318 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
1319 /*
1320 * ADM1030 splits fan controller behavior across two
1321 * registers. We also do not support Auto-Filter mode
1322 * nor do we support Manual-RPM-feedback.
1323 */
1324 if (newreg == 4) {
1325 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2);
1326 oldreg &= ~0x01;
1327 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg);
1328 } else {
1329 if (newreg == 0)
1330 newreg = 4;
1331 else if (newreg == 6)
1332 newreg = 7;
1333 else if (newreg == 7)
1334 newreg = 0;
1335 else
1336 return EINVAL;
1337 newreg <<= 5;
1338 newreg |= (oldreg & 0x1f);
1339 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1340 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1;
1341 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg);
1342 }
1343 } else {
1344 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5);
1345 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1346 }
1347 return 0;
1348 }
1349
1350 static int
sysctl_dbcool_slope(SYSCTLFN_ARGS)1351 sysctl_dbcool_slope(SYSCTLFN_ARGS)
1352 {
1353 struct sysctlnode node;
1354 struct dbcool_softc *sc;
1355 int reg, error;
1356 uint8_t chipreg;
1357 uint8_t newreg;
1358
1359 node = *rnode;
1360 sc = (struct dbcool_softc *)node.sysctl_data;
1361 chipreg = node.sysctl_num & 0xff;
1362
1363 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f;
1364 node.sysctl_data = ®
1365 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1366
1367 if (error || newp == NULL)
1368 return error;
1369
1370 /* We were asked to update the value - sanity check before writing */
1371 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f)
1372 return EINVAL;
1373
1374 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) |
1375 (*(int *)node.sysctl_data << 4);
1376 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1377 return 0;
1378 }
1379
1380 static int
sysctl_dbcool_thyst(SYSCTLFN_ARGS)1381 sysctl_dbcool_thyst(SYSCTLFN_ARGS)
1382 {
1383 struct sysctlnode node;
1384 struct dbcool_softc *sc;
1385 int reg, error;
1386 uint8_t chipreg;
1387 uint8_t newreg, newhyst;
1388
1389 node = *rnode;
1390 sc = (struct dbcool_softc *)node.sysctl_data;
1391 chipreg = node.sysctl_num & 0x7f;
1392
1393 /* retrieve 4-bit value */
1394 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1395 if ((node.sysctl_num & 0x80) == 0)
1396 reg = newreg >> 4;
1397 else
1398 reg = newreg;
1399 reg = reg & 0x0f;
1400
1401 node.sysctl_data = ®
1402 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1403
1404 if (error || newp == NULL)
1405 return error;
1406
1407 /* We were asked to update the value - sanity check before writing */
1408 newhyst = *(int *)node.sysctl_data;
1409 if (newhyst > 0x0f)
1410 return EINVAL;
1411
1412 /* Insert new value into field and update register */
1413 if ((node.sysctl_num & 0x80) == 0) {
1414 newreg &= 0x0f;
1415 newreg |= (newhyst << 4);
1416 } else {
1417 newreg &= 0xf0;
1418 newreg |= newhyst;
1419 }
1420 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1421 return 0;
1422 }
1423
1424 #ifdef DBCOOL_DEBUG
1425
1426 /*
1427 * These routines can be used for debugging. reg_select is used to
1428 * select any arbitrary register in the device. reg_access is used
1429 * to read (and optionally update) the selected register.
1430 *
1431 * No attempt is made to validate the data passed. If you use these
1432 * routines, you are assumed to know what you're doing!
1433 *
1434 * Caveat user
1435 */
1436 static int
sysctl_dbcool_reg_select(SYSCTLFN_ARGS)1437 sysctl_dbcool_reg_select(SYSCTLFN_ARGS)
1438 {
1439 struct sysctlnode node;
1440 struct dbcool_softc *sc;
1441 int reg, error;
1442
1443 node = *rnode;
1444 sc = (struct dbcool_softc *)node.sysctl_data;
1445
1446 reg = sc->sc_user_reg;
1447 node.sysctl_data = ®
1448 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1449
1450 if (error || newp == NULL)
1451 return error;
1452
1453 sc->sc_user_reg = *(int *)node.sysctl_data;
1454 return 0;
1455 }
1456
1457 static int
sysctl_dbcool_reg_access(SYSCTLFN_ARGS)1458 sysctl_dbcool_reg_access(SYSCTLFN_ARGS)
1459 {
1460 struct sysctlnode node;
1461 struct dbcool_softc *sc;
1462 int reg, error;
1463 uint8_t chipreg;
1464 uint8_t newreg;
1465
1466 node = *rnode;
1467 sc = (struct dbcool_softc *)node.sysctl_data;
1468 chipreg = sc->sc_user_reg;
1469
1470 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1471 node.sysctl_data = ®
1472 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1473
1474 if (error || newp == NULL)
1475 return error;
1476
1477 newreg = *(int *)node.sysctl_data;
1478 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1479 return 0;
1480 }
1481 #endif /* DBCOOL_DEBUG */
1482
1483 /*
1484 * Encode an index number and register number for use as a sysctl_num
1485 * so we can select the correct device register later.
1486 */
1487 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg)
1488
1489 void
dbcool_setup(device_t self)1490 dbcool_setup(device_t self)
1491 {
1492 struct dbcool_softc *sc = device_private(self);
1493 const struct sysctlnode *me = NULL;
1494 #ifdef DBCOOL_DEBUG
1495 struct sysctlnode *node = NULL;
1496 #endif
1497 uint8_t cfg_val, cfg_reg;
1498 int ret, error;
1499
1500 /*
1501 * Some chips are capable of reporting an extended temperature range
1502 * by default. On these models, config register 5 bit 0 can be set
1503 * to 1 for compatibility with other chips that report 2s complement.
1504 */
1505 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
1506 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80)
1507 sc->sc_temp_offset = 64;
1508 else
1509 sc->sc_temp_offset = 0;
1510 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) {
1511 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) &
1512 DBCOOL_CFG5_TWOSCOMP)
1513 sc->sc_temp_offset = 0;
1514 else
1515 sc->sc_temp_offset = 64;
1516 } else
1517 sc->sc_temp_offset = 0;
1518
1519 /* Determine Vcc for this chip */
1520 sc->sc_supply_voltage = dbcool_supply_voltage(sc);
1521
1522 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me,
1523 CTLFLAG_READWRITE,
1524 CTLTYPE_NODE, device_xname(self), NULL,
1525 NULL, 0, NULL, 0,
1526 CTL_HW, CTL_CREATE, CTL_EOL);
1527 if (ret == 0)
1528 sc->sc_root_sysctl_num = me->sysctl_num;
1529 else
1530 sc->sc_root_sysctl_num = 0;
1531
1532 aprint_debug_dev(self,
1533 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n",
1534 sc->sc_supply_voltage / 1000000,
1535 sc->sc_supply_voltage % 1000000,
1536 sc->sc_temp_offset ? "extended" : "normal");
1537
1538 /* Create the sensors for this device */
1539 sc->sc_sme = sysmon_envsys_create();
1540 if (dbcool_setup_sensors(sc))
1541 goto out;
1542
1543 if (sc->sc_root_sysctl_num != 0) {
1544 /* If supported, create sysctl tree for fan PWM controllers */
1545 if (sc->sc_dc.dc_chip->power != NULL)
1546 dbcool_setup_controllers(sc);
1547
1548 #ifdef DBCOOL_DEBUG
1549 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL,
1550 (void *)&node,
1551 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL,
1552 sysctl_dbcool_reg_select,
1553 0, (void *)sc, sizeof(int),
1554 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL);
1555 if (node != NULL)
1556 node->sysctl_data = sc;
1557
1558 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL,
1559 (void *)&node,
1560 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL,
1561 sysctl_dbcool_reg_access,
1562 0, (void *)sc, sizeof(int),
1563 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL);
1564 if (node != NULL)
1565 node->sysctl_data = sc;
1566 #endif /* DBCOOL_DEBUG */
1567 }
1568
1569 /*
1570 * Read and rewrite config register to activate device
1571 */
1572 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
1573 cfg_reg = DBCOOL_ADM1030_CFG1;
1574 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466)
1575 cfg_reg = DBCOOL_ADT7466_CONFIG1;
1576 else
1577 cfg_reg = DBCOOL_CONFIG1_REG;
1578 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG);
1579 if ((cfg_val & DBCOOL_CFG1_START) == 0) {
1580 cfg_val |= DBCOOL_CFG1_START;
1581 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val);
1582 }
1583 if (dbcool_islocked(sc))
1584 aprint_normal_dev(self, "configuration locked\n");
1585
1586 sc->sc_sme->sme_name = device_xname(self);
1587 sc->sc_sme->sme_cookie = sc;
1588 sc->sc_sme->sme_refresh = dbcool_refresh;
1589 sc->sc_sme->sme_set_limits = dbcool_set_limits;
1590 sc->sc_sme->sme_get_limits = dbcool_get_limits;
1591
1592 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) {
1593 aprint_error_dev(self,
1594 "unable to register with sysmon (%d)\n", error);
1595 goto out;
1596 }
1597
1598 return;
1599
1600 out:
1601 sysmon_envsys_destroy(sc->sc_sme);
1602 sc->sc_sme = NULL;
1603 }
1604
1605 static int
dbcool_setup_sensors(struct dbcool_softc * sc)1606 dbcool_setup_sensors(struct dbcool_softc *sc)
1607 {
1608 int i;
1609 int error = 0;
1610 uint8_t vid_reg, vid_val;
1611 struct chip_id *chip = sc->sc_dc.dc_chip;
1612
1613 for (i=0; chip->table[i].type != DBC_EOF; i++) {
1614 if (i < DBCOOL_MAXSENSORS)
1615 sc->sc_sysctl_num[i] = -1;
1616 else if (chip->table[i].type != DBC_CTL) {
1617 aprint_normal_dev(sc->sc_dev, "chip table too big!\n");
1618 break;
1619 }
1620 switch (chip->table[i].type) {
1621 case DBC_TEMP:
1622 sc->sc_sensor[i].units = ENVSYS_STEMP;
1623 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1624 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS;
1625 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY;
1626 error = dbcool_attach_sensor(sc, i);
1627 break;
1628 case DBC_VOLT:
1629 /*
1630 * If 12V-In pin has been reconfigured as 6th bit
1631 * of VID code, don't create a 12V-In sensor
1632 */
1633 if ((chip->flags & DBCFLAG_HAS_VID_SEL) &&
1634 (chip->table[i].reg.val_reg == DBCOOL_12VIN) &&
1635 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) &
1636 0x80))
1637 break;
1638
1639 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC;
1640 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1641 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS;
1642 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY;
1643 error = dbcool_attach_sensor(sc, i);
1644 break;
1645 case DBC_FAN:
1646 sc->sc_sensor[i].units = ENVSYS_SFANRPM;
1647 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1648 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS;
1649 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY;
1650 error = dbcool_attach_sensor(sc, i);
1651 break;
1652 case DBC_VID:
1653 sc->sc_sensor[i].units = ENVSYS_INTEGER;
1654 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1655 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP;
1656
1657 /* retrieve 5- or 6-bit value */
1658 vid_reg = chip->table[i].reg.val_reg;
1659 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg);
1660 if (chip->flags & DBCFLAG_HAS_VID_SEL)
1661 vid_val &= 0x3f;
1662 else
1663 vid_val &= 0x1f;
1664 sc->sc_sensor[i].value_cur = vid_val;
1665
1666 error = dbcool_attach_sensor(sc, i);
1667 break;
1668 case DBC_CTL:
1669 error = dbcool_attach_temp_control(sc, i, chip);
1670 if (error) {
1671 aprint_error_dev(sc->sc_dev,
1672 "attach index %d failed %d\n",
1673 i, error);
1674 error = 0;
1675 }
1676 break;
1677 default:
1678 aprint_error_dev(sc->sc_dev,
1679 "sensor_table index %d has bad type %d\n",
1680 i, chip->table[i].type);
1681 break;
1682 }
1683 if (error)
1684 break;
1685 }
1686 return error;
1687 }
1688
1689 static int
dbcool_attach_sensor(struct dbcool_softc * sc,int idx)1690 dbcool_attach_sensor(struct dbcool_softc *sc, int idx)
1691 {
1692 int name_index;
1693 int error = 0;
1694 char name[8];
1695 const char *desc;
1696
1697 name_index = sc->sc_dc.dc_chip->table[idx].name_index;
1698 snprintf(name, 7, "s%02x", sc->sc_dc.dc_chip->table[idx].reg.val_reg);
1699 if (prop_dictionary_get_string(sc->sc_prop, name, &desc)) {
1700 strlcpy(sc->sc_sensor[idx].desc, desc,
1701 sizeof(sc->sc_sensor[idx].desc));
1702 } else {
1703 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index],
1704 sizeof(sc->sc_sensor[idx].desc));
1705 }
1706 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg;
1707 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index;
1708
1709 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]);
1710 return error;
1711 }
1712
1713 static int
dbcool_attach_temp_control(struct dbcool_softc * sc,int idx,struct chip_id * chip)1714 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx,
1715 struct chip_id *chip)
1716 {
1717 const struct sysctlnode *me2 = NULL, *node;
1718 int j, ret, sysctl_index, rw_flag;
1719 uint8_t sysctl_reg;
1720 char name[SYSCTL_NAMELEN];
1721
1722 /* Search for the corresponding temp sensor */
1723 for (j = 0; j < idx; j++) {
1724 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP)
1725 continue;
1726 if (chip->table[j].name_index == chip->table[idx].name_index)
1727 break;
1728 }
1729 if (j >= idx) /* Temp sensor not found */
1730 return ENOENT;
1731
1732 /* create sysctl node for the sensor if not one already there */
1733 if (sc->sc_sysctl_num[j] == -1) {
1734 int name_index = sc->sc_dc.dc_chip->table[idx].name_index;
1735
1736 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2,
1737 CTLFLAG_READWRITE,
1738 CTLTYPE_NODE, dbc_sensor_names[name_index],
1739 sc->sc_sensor[j].desc,
1740 NULL, 0, NULL, 0,
1741 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE,
1742 CTL_EOL);
1743 if (me2 != NULL)
1744 sc->sc_sysctl_num[j] = me2->sysctl_num;
1745 else
1746 return ret;
1747 }
1748 /* add sysctl leaf node for this control variable */
1749 sysctl_index = chip->table[idx].sysctl_index;
1750 sysctl_reg = chip->table[idx].reg.val_reg;
1751 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name));
1752 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc))
1753 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC;
1754 else
1755 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC;
1756 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag,
1757 CTLTYPE_INT, name,
1758 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc),
1759 dbc_sysctl_table[sysctl_index].helper,
1760 0, (void *)sc, sizeof(int),
1761 CTL_HW, sc->sc_root_sysctl_num,
1762 sc->sc_sysctl_num[j],
1763 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL);
1764
1765 return ret;
1766 }
1767
1768 static void
dbcool_setup_controllers(struct dbcool_softc * sc)1769 dbcool_setup_controllers(struct dbcool_softc *sc)
1770 {
1771 int i, j, rw_flag;
1772 uint8_t sysctl_reg;
1773 struct chip_id *chip = sc->sc_dc.dc_chip;
1774 const struct sysctlnode *me2 = NULL;
1775 const struct sysctlnode *node = NULL;
1776 char name[SYSCTL_NAMELEN];
1777
1778 for (i = 0; chip->power[i].desc != NULL; i++) {
1779 snprintf(name, sizeof(name), "fan_ctl_%d", i);
1780 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2,
1781 CTLFLAG_READWRITE | CTLFLAG_OWNDESC,
1782 CTLTYPE_NODE, name, NULL,
1783 NULL, 0, NULL, 0,
1784 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL);
1785
1786 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) {
1787 if (j == DBC_PWM_MAX_DUTY &&
1788 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0)
1789 continue;
1790 sysctl_reg = chip->power[i].power_regs[j];
1791 if (sysctl_reg == DBCOOL_NO_REG)
1792 continue;
1793 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name));
1794 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc))
1795 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC;
1796 else
1797 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC;
1798 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL,
1799 &node, rw_flag,
1800 (j == DBC_PWM_BEHAVIOR)?
1801 CTLTYPE_STRING:CTLTYPE_INT,
1802 name,
1803 SYSCTL_DESCR(dbc_sysctl_table[j].desc),
1804 dbc_sysctl_table[j].helper,
1805 0, sc,
1806 ( j == DBC_PWM_BEHAVIOR)?
1807 sizeof(dbcool_cur_behav): sizeof(int),
1808 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num,
1809 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL);
1810 }
1811 }
1812 }
1813
1814 static void
dbcool_refresh(struct sysmon_envsys * sme,envsys_data_t * edata)1815 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
1816 {
1817 struct dbcool_softc *sc=sme->sme_cookie;
1818 int i, nom_volt_idx, cur;
1819 struct reg_list *reg;
1820
1821 i = edata->sensor;
1822 reg = sc->sc_regs[i];
1823
1824 edata->state = ENVSYS_SVALID;
1825 switch (edata->units)
1826 {
1827 case ENVSYS_STEMP:
1828 cur = dbcool_read_temp(sc, reg->val_reg, true);
1829 break;
1830 case ENVSYS_SVOLTS_DC:
1831 nom_volt_idx = sc->sc_nom_volt[i];
1832 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx,
1833 true);
1834 break;
1835 case ENVSYS_SFANRPM:
1836 cur = dbcool_read_rpm(sc, reg->val_reg);
1837 break;
1838 case ENVSYS_INTEGER:
1839 return;
1840 default:
1841 edata->state = ENVSYS_SINVALID;
1842 return;
1843 }
1844
1845 if (cur == 0 && (edata->units != ENVSYS_SFANRPM))
1846 edata->state = ENVSYS_SINVALID;
1847
1848 /*
1849 * If fan is "stalled" but has no low limit, treat
1850 * it as though the fan is not installed.
1851 */
1852 else if (edata->units == ENVSYS_SFANRPM && cur == 0 &&
1853 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN)))
1854 edata->state = ENVSYS_SINVALID;
1855
1856 edata->value_cur = cur;
1857 }
1858
1859 int
dbcool_chip_ident(struct dbcool_chipset * dc)1860 dbcool_chip_ident(struct dbcool_chipset *dc)
1861 {
1862 /* verify this is a supported dbCool chip */
1863 uint8_t c_id, d_id, r_id;
1864 int i;
1865
1866 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG);
1867 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG);
1868 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG);
1869
1870 /* The EMC6D103S only supports read_byte and since dc->dc_chip is
1871 * NULL when we call dc->dc_readreg above we use
1872 * send_byte/receive_byte which doesn't work.
1873 *
1874 * So if we only get 0's back then try again with dc->dc_chip
1875 * set to the EMC6D103S_DEVICEID and which doesn't have
1876 * DBCFLAG_NO_READBYTE set so read_byte will be used
1877 */
1878 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) {
1879 for (i = 0; chip_table[i].company != 0; i++)
1880 if ((SMSC_COMPANYID == chip_table[i].company) &&
1881 (EMC6D103S_DEVICEID == chip_table[i].device)) {
1882 dc->dc_chip = &chip_table[i];
1883 break;
1884 }
1885 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG);
1886 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG);
1887 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG);
1888 }
1889
1890 for (i = 0; chip_table[i].company != 0; i++)
1891 if ((c_id == chip_table[i].company) &&
1892 (d_id == chip_table[i].device ||
1893 chip_table[i].device == 0xff) &&
1894 (r_id == chip_table[i].rev ||
1895 chip_table[i].rev == 0xff)) {
1896 dc->dc_chip = &chip_table[i];
1897 return i;
1898 }
1899
1900 aprint_debug("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x"
1901 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id,
1902 r_id);
1903
1904 return -1;
1905 }
1906
1907 /*
1908 * Retrieve sensor limits from the chip registers
1909 */
1910 static void
dbcool_get_limits(struct sysmon_envsys * sme,envsys_data_t * edata,sysmon_envsys_lim_t * limits,uint32_t * props)1911 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
1912 sysmon_envsys_lim_t *limits, uint32_t *props)
1913 {
1914 int index = edata->sensor;
1915 struct dbcool_softc *sc = sme->sme_cookie;
1916
1917 *props &= ~(PROP_CRITMIN | PROP_CRITMAX);
1918 switch (edata->units) {
1919 case ENVSYS_STEMP:
1920 dbcool_get_temp_limits(sc, index, limits, props);
1921 break;
1922 case ENVSYS_SVOLTS_DC:
1923 dbcool_get_volt_limits(sc, index, limits, props);
1924 break;
1925 case ENVSYS_SFANRPM:
1926 dbcool_get_fan_limits(sc, index, limits, props);
1927
1928 /* FALLTHROUGH */
1929 default:
1930 break;
1931 }
1932 *props &= ~PROP_DRIVER_LIMITS;
1933
1934 /* If both limits provided, make sure they're sane */
1935 if ((*props & PROP_CRITMIN) &&
1936 (*props & PROP_CRITMAX) &&
1937 (limits->sel_critmin >= limits->sel_critmax))
1938 *props &= ~(PROP_CRITMIN | PROP_CRITMAX);
1939
1940 /*
1941 * If this is the first time through, save these values
1942 * in case user overrides them and then requests a reset.
1943 */
1944 if (sc->sc_defprops[index] == 0) {
1945 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS;
1946 sc->sc_deflims[index] = *limits;
1947 }
1948 }
1949
1950 static void
dbcool_get_temp_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)1951 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx,
1952 sysmon_envsys_lim_t *lims, uint32_t *props)
1953 {
1954 struct reg_list *reg = sc->sc_regs[idx];
1955 uint8_t lo_lim, hi_lim;
1956
1957 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg);
1958 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg);
1959
1960 if (sc->sc_temp_offset) {
1961 if (lo_lim > 0x01) {
1962 lims->sel_critmin = lo_lim - sc->sc_temp_offset;
1963 *props |= PROP_CRITMIN;
1964 }
1965 if (hi_lim != 0xff) {
1966 lims->sel_critmax = hi_lim - sc->sc_temp_offset;
1967 *props |= PROP_CRITMAX;
1968 }
1969 } else {
1970 if (lo_lim != 0x80 && lo_lim != 0x81) {
1971 lims->sel_critmin = (int8_t)lo_lim;
1972 *props |= PROP_CRITMIN;
1973 }
1974
1975 if (hi_lim != 0x7f) {
1976 lims->sel_critmax = (int8_t)hi_lim;
1977 *props |= PROP_CRITMAX;
1978 }
1979 }
1980
1981 /* Convert temp limits to microKelvin */
1982 lims->sel_critmin *= 1000000;
1983 lims->sel_critmin += 273150000;
1984 lims->sel_critmax *= 1000000;
1985 lims->sel_critmax += 273150000;
1986 }
1987
1988 static void
dbcool_get_volt_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)1989 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx,
1990 sysmon_envsys_lim_t *lims, uint32_t *props)
1991 {
1992 struct reg_list *reg = sc->sc_regs[idx];
1993 int64_t limit;
1994 int nom;
1995
1996 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index];
1997 if (nom < 0)
1998 nom = dbcool_supply_voltage(sc);
1999 nom *= 1000000; /* scale for microvolts */
2000
2001 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg);
2002 if (limit != 0x00 && limit != 0xff) {
2003 limit *= nom;
2004 limit /= 0xc0;
2005 lims->sel_critmin = limit;
2006 *props |= PROP_CRITMIN;
2007 }
2008 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg);
2009 if (limit != 0x00 && limit != 0xff) {
2010 limit *= nom;
2011 limit /= 0xc0;
2012 lims->sel_critmax = limit;
2013 *props |= PROP_CRITMAX;
2014 }
2015 }
2016
2017 static void
dbcool_get_fan_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2018 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx,
2019 sysmon_envsys_lim_t *lims, uint32_t *props)
2020 {
2021 struct reg_list *reg = sc->sc_regs[idx];
2022 int32_t limit;
2023
2024 limit = dbcool_read_rpm(sc, reg->lo_lim_reg);
2025 if (limit) {
2026 lims->sel_critmin = limit;
2027 *props |= PROP_CRITMIN;
2028 }
2029 }
2030
2031 /*
2032 * Update sensor limits in the chip registers
2033 */
2034 static void
dbcool_set_limits(struct sysmon_envsys * sme,envsys_data_t * edata,sysmon_envsys_lim_t * limits,uint32_t * props)2035 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
2036 sysmon_envsys_lim_t *limits, uint32_t *props)
2037 {
2038 int index = edata->sensor;
2039 struct dbcool_softc *sc = sme->sme_cookie;
2040
2041 if (limits == NULL) {
2042 limits = &sc->sc_deflims[index];
2043 props = &sc->sc_defprops[index];
2044 }
2045 switch (edata->units) {
2046 case ENVSYS_STEMP:
2047 dbcool_set_temp_limits(sc, index, limits, props);
2048 break;
2049 case ENVSYS_SVOLTS_DC:
2050 dbcool_set_volt_limits(sc, index, limits, props);
2051 break;
2052 case ENVSYS_SFANRPM:
2053 dbcool_set_fan_limits(sc, index, limits, props);
2054
2055 /* FALLTHROUGH */
2056 default:
2057 break;
2058 }
2059 *props &= ~PROP_DRIVER_LIMITS;
2060 }
2061
2062 static void
dbcool_set_temp_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2063 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx,
2064 sysmon_envsys_lim_t *lims, uint32_t *props)
2065 {
2066 struct reg_list *reg = sc->sc_regs[idx];
2067 int32_t limit;
2068
2069 if (*props & PROP_CRITMIN) {
2070 limit = lims->sel_critmin - 273150000;
2071 limit /= 1000000;
2072 if (sc->sc_temp_offset) {
2073 limit += sc->sc_temp_offset;
2074 if (limit < 0)
2075 limit = 0;
2076 else if (limit > 255)
2077 limit = 255;
2078 } else {
2079 if (limit < -127)
2080 limit = -127;
2081 else if (limit > 127)
2082 limit = 127;
2083 }
2084 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,
2085 (uint8_t)limit);
2086 } else if (*props & PROP_DRIVER_LIMITS) {
2087 if (sc->sc_temp_offset)
2088 limit = 0x00;
2089 else
2090 limit = 0x80;
2091 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,
2092 (uint8_t)limit);
2093 }
2094
2095 if (*props & PROP_CRITMAX) {
2096 limit = lims->sel_critmax - 273150000;
2097 limit /= 1000000;
2098 if (sc->sc_temp_offset) {
2099 limit += sc->sc_temp_offset;
2100 if (limit < 0)
2101 limit = 0;
2102 else if (limit > 255)
2103 limit = 255;
2104 } else {
2105 if (limit < -127)
2106 limit = -127;
2107 else if (limit > 127)
2108 limit = 127;
2109 }
2110 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg,
2111 (uint8_t)limit);
2112 } else if (*props & PROP_DRIVER_LIMITS) {
2113 if (sc->sc_temp_offset)
2114 limit = 0xff;
2115 else
2116 limit = 0x7f;
2117 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg,
2118 (uint8_t)limit);
2119 }
2120 }
2121
2122 static void
dbcool_set_volt_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2123 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx,
2124 sysmon_envsys_lim_t *lims, uint32_t *props)
2125 {
2126 struct reg_list *reg = sc->sc_regs[idx];
2127 int64_t limit;
2128 int nom;
2129
2130 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index];
2131 if (nom < 0)
2132 nom = dbcool_supply_voltage(sc);
2133 nom *= 1000000; /* scale for microvolts */
2134
2135 if (*props & PROP_CRITMIN) {
2136 limit = lims->sel_critmin;
2137 limit *= 0xc0;
2138 limit /= nom;
2139 if (limit > 0xff)
2140 limit = 0xff;
2141 else if (limit < 0)
2142 limit = 0;
2143 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit);
2144 } else if (*props & PROP_DRIVER_LIMITS)
2145 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0);
2146
2147 if (*props & PROP_CRITMAX) {
2148 limit = lims->sel_critmax;
2149 limit *= 0xc0;
2150 limit /= nom;
2151 if (limit > 0xff)
2152 limit = 0xff;
2153 else if (limit < 0)
2154 limit = 0;
2155 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit);
2156 } else if (*props & PROP_DRIVER_LIMITS)
2157 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff);
2158 }
2159
2160 static void
dbcool_set_fan_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2161 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx,
2162 sysmon_envsys_lim_t *lims, uint32_t *props)
2163 {
2164 struct reg_list *reg = sc->sc_regs[idx];
2165 int32_t limit, dividend;
2166
2167 if (*props & PROP_CRITMIN) {
2168 limit = lims->sel_critmin;
2169 if (limit == 0)
2170 limit = 0xffff;
2171 else {
2172 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
2173 dividend = 11250 * 60;
2174 else
2175 dividend = 90000 * 60;
2176 limit = limit / dividend;
2177 if (limit > 0xffff)
2178 limit = 0xffff;
2179 }
2180 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,
2181 limit & 0xff);
2182 limit >>= 8;
2183 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1,
2184 limit & 0xff);
2185 } else if (*props & PROP_DRIVER_LIMITS) {
2186 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff);
2187 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff);
2188 }
2189 }
2190
2191 MODULE(MODULE_CLASS_DRIVER, dbcool, "iic,sysmon_envsys");
2192
2193 #ifdef _MODULE
2194 #include "ioconf.c"
2195 #endif
2196
2197 static int
dbcool_modcmd(modcmd_t cmd,void * opaque)2198 dbcool_modcmd(modcmd_t cmd, void *opaque)
2199 {
2200 int error = 0;
2201 #ifdef _MODULE
2202 static struct sysctllog *dbcool_sysctl_clog;
2203 #endif
2204
2205 switch (cmd) {
2206 case MODULE_CMD_INIT:
2207 #ifdef _MODULE
2208 error = config_init_component(cfdriver_ioconf_dbcool,
2209 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool);
2210 sysctl_dbcoolsetup(&dbcool_sysctl_clog);
2211 #endif
2212 return error;
2213 case MODULE_CMD_FINI:
2214 #ifdef _MODULE
2215 error = config_fini_component(cfdriver_ioconf_dbcool,
2216 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool);
2217 sysctl_teardown(&dbcool_sysctl_clog);
2218 #endif
2219 return error;
2220 default:
2221 return ENOTTY;
2222 }
2223 }
2224