1 /* $NetBSD: imcsmb.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Goyette
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*-
33 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
34 *
35 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
36 *
37 * Copyright (c) 2017-2018 Panasas
38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in the
47 * documentation and/or other materials provided with the distribution.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
52 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 * SUCH DAMAGE.
60 */
61
62 /*
63 * Driver for the SMBus controllers in Intel's Integrated Memory Controllers
64 * in certain CPUs. A more detailed description of this device is present
65 * in imc.c
66 */
67
68 #include <sys/cdefs.h>
69 __KERNEL_RCSID(0, "$NetBSD: imcsmb.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $");
70
71 #include <sys/param.h>
72 #include <sys/kernel.h>
73 #include <sys/module.h>
74 #include <sys/endian.h>
75 #include <sys/errno.h>
76 #include <sys/mutex.h>
77 #include <sys/bus.h>
78
79 #include <dev/pci/pcidevs.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pcireg.h>
82
83 #include <dev/i2c/i2cvar.h>
84
85 #include "imcsmb_reg.h"
86 #include "imcsmb_var.h"
87
88 /* Device methods */
89 static int imcsmb_probe(device_t, cfdata_t, void *);
90 static void imcsmb_attach(device_t, device_t, void *);
91 static int imcsmb_detach(device_t, int flags);
92 static int imcsmb_rescan(device_t, const char *, const int *);
93 static void imcsmb_chdet(device_t, device_t);
94
95 CFATTACH_DECL3_NEW(imcsmb, sizeof(struct imcsmb_softc),
96 imcsmb_probe, imcsmb_attach, imcsmb_detach, NULL, imcsmb_rescan,
97 imcsmb_chdet, 0);
98
99 /* Bus access control methods */
100 static int imcsmb_acquire_bus(void *cookie, int flags);
101 static void imcsmb_release_bus(void *cookie, int flags);
102
103 /* SMBus methods */
104 static int imcsmb_exec(void *cookie, i2c_op_t, i2c_addr_t, const void *,
105 size_t, void *, size_t, int);
106
107 /**
108 * device_attach() method. Set up the softc, including getting the set of the
109 * parent imcsmb_pci's registers that we will use. Create the smbus(4) device,
110 * which any SMBus slave device drivers will connect to. Probe and attach
111 * anything which might be downstream.
112 *
113 * @author rpokala
114 *
115 * @param[in,out] dev
116 * Device being attached.
117 */
118
119 static void
imcsmb_attach(device_t parent,device_t self,void * aux)120 imcsmb_attach(device_t parent, device_t self, void *aux)
121 {
122 struct imcsmb_softc *sc = device_private(self);
123 struct imc_attach_args *imca = aux;
124
125 aprint_naive("\n");
126 aprint_normal(": SMBus controller\n");
127
128 /* Initialize private state */
129 sc->sc_dev = self;
130 sc->sc_regs = imca->ia_regs;
131 sc->sc_pci_tag = imca->ia_pci_tag;
132 sc->sc_pci_chipset_tag = imca->ia_pci_chipset_tag;
133
134 if (!pmf_device_register(self, NULL, NULL))
135 aprint_error_dev(self, "couldn't establish power handler\n");
136
137 imcsmb_rescan(self, NULL, NULL);
138 }
139
140 static int
imcsmb_rescan(device_t self,const char * ifattr,const int * locs)141 imcsmb_rescan(device_t self, const char *ifattr, const int *locs)
142 {
143 struct imcsmb_softc *sc = device_private(self);
144 struct i2cbus_attach_args iba;
145
146 /* Create the i2cbus child */
147 if (sc->sc_smbus != NULL)
148 return 0;
149
150 iic_tag_init(&sc->sc_i2c_tag);
151 sc->sc_i2c_tag.ic_cookie = sc;
152 sc->sc_i2c_tag.ic_acquire_bus = imcsmb_acquire_bus;
153 sc->sc_i2c_tag.ic_release_bus = imcsmb_release_bus;
154 sc->sc_i2c_tag.ic_exec = imcsmb_exec;
155
156 memset(&iba, 0, sizeof(iba));
157 iba.iba_tag = &sc->sc_i2c_tag;
158 sc->sc_smbus = config_found(self, &iba, iicbus_print, CFARGS_NONE);
159
160 if (sc->sc_smbus == NULL) {
161 aprint_normal_dev(self, "no child found\n");
162 return ENXIO;
163 }
164
165 return 0;
166 }
167
168 static void
imcsmb_chdet(device_t self,device_t child)169 imcsmb_chdet(device_t self, device_t child)
170 {
171 struct imcsmb_softc *sc = device_private(self);
172
173 if (child == sc->sc_smbus)
174 sc->sc_smbus = NULL;
175 else KASSERT(child == NULL);
176 }
177
178 /**
179 * device_detach() method. attach() didn't do any allocations, so there's
180 * nothing special needed
181 */
182 static int
imcsmb_detach(device_t self,int flags)183 imcsmb_detach(device_t self, int flags)
184 {
185 struct imcsmb_softc *sc = device_private(self);
186 int error;
187
188 error = config_detach_children(self, flags);
189 if (error)
190 return error;
191
192 pmf_device_deregister(self);
193 iic_tag_fini(&sc->sc_i2c_tag);
194 return 0;
195 }
196
197 /**
198 * device_probe() method. All the actual probing was done by the imc
199 * parent, so just report success.
200 *
201 * @author Joe Kloss
202 *
203 * @param[in,out] dev
204 * Device being probed.
205 */
206 static int
imcsmb_probe(device_t parent,cfdata_t match,void * aux)207 imcsmb_probe(device_t parent, cfdata_t match, void *aux)
208 {
209
210 return 1;
211 }
212
213 static int
imcsmb_acquire_bus(void * cookie,int flags)214 imcsmb_acquire_bus(void *cookie, int flags)
215 {
216 struct imcsmb_softc *sc = cookie;
217
218 if (cold)
219 return 0;
220
221 imc_callback(sc, IMC_BIOS_DISABLE);
222
223 return 0;
224 }
225
226 static void
imcsmb_release_bus(void * cookie,int flags)227 imcsmb_release_bus(void *cookie, int flags)
228 {
229 struct imcsmb_softc *sc = cookie;
230
231 if (cold)
232 return;
233
234 imc_callback(sc, IMC_BIOS_ENABLE);
235 }
236
237 static int
imcsmb_exec(void * cookie,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)238 imcsmb_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf,
239 size_t cmdlen, void *buf, size_t len, int flags)
240 {
241 struct imcsmb_softc *sc = cookie;
242 int i;
243 int rc = 0;
244 uint32_t cmd_val;
245 uint32_t cntl_val;
246 uint32_t orig_cntl_val;
247 uint32_t stat_val;
248 uint16_t *word;
249 uint16_t lword;
250 uint8_t *byte;
251 uint8_t lbyte;
252 uint8_t cmd;
253
254 if ((cmdlen != 1) || (len > 2) || (len < 1))
255 return EINVAL;
256
257 byte = (uint8_t *) buf;
258 word = (uint16_t *) buf;
259 lbyte = *byte;
260 lword = *word;
261
262 /* We modify the value of the control register; save the original, so
263 * we can restore it later
264 */
265 orig_cntl_val = pci_conf_read(sc->sc_pci_chipset_tag, sc->sc_pci_tag,
266 sc->sc_regs->smb_cntl);
267
268 cntl_val = orig_cntl_val;
269
270 /*
271 * Set up the SMBCNTL register
272 */
273
274 /* [31:28] Clear the existing value of the DTI bits, then set them to
275 * the four high bits of the slave address.
276 */
277 cntl_val &= ~IMCSMB_CNTL_DTI_MASK;
278 cntl_val |= ((uint32_t) addr & 0x78) << 25;
279
280 /* [27:27] Set the CLK_OVERRIDE bit, to enable normal operation */
281 cntl_val |= IMCSMB_CNTL_CLK_OVERRIDE;
282
283 /* [26:26] Clear the WRITE_DISABLE bit; the datasheet says this isn't
284 * necessary, but empirically, it is.
285 */
286 cntl_val &= ~IMCSMB_CNTL_WRITE_DISABLE_BIT;
287
288 /* [9:9] Clear the POLL_EN bit, to stop the hardware TSOD polling. */
289 cntl_val &= ~IMCSMB_CNTL_POLL_EN;
290
291 /*
292 * Set up the SMBCMD register
293 */
294
295 /* [31:31] Set the TRIGGER bit; when this gets written, the controller
296 * will issue the command.
297 */
298 cmd_val = IMCSMB_CMD_TRIGGER_BIT;
299
300 /* [29:29] For word operations, set the WORD_ACCESS bit. */
301 if (len == 2) {
302 cmd_val |= IMCSMB_CMD_WORD_ACCESS;
303 }
304
305 /* [27:27] For write operations, set the WRITE bit. */
306 if (I2C_OP_WRITE_P(op)) {
307 cmd_val |= IMCSMB_CMD_WRITE_BIT;
308 }
309
310 /* [26:24] The three non-DTI, non-R/W bits of the slave address. */
311 cmd_val |= (uint32_t) ((addr & 0x7) << 24);
312
313 /* [23:16] The command (offset in the case of an EEPROM, or register in
314 * the case of TSOD or NVDIMM controller).
315 */
316 cmd = *((const uint8_t *) cmdbuf);
317 cmd_val |= (uint32_t) (cmd << 16);
318
319 /* [15:0] The data to be written for a write operation. */
320 if (I2C_OP_WRITE_P(op)) {
321 if (len == 2) {
322 /* The datasheet says the controller uses different
323 * endianness for word operations on I2C vs SMBus!
324 * I2C: [15:8] = MSB; [7:0] = LSB
325 * SMB: [15:8] = LSB; [7:0] = MSB
326 * As a practical matter, this controller is very
327 * specifically for use with DIMMs, the SPD (and
328 * NVDIMM controllers) are only accessed as bytes,
329 * the temperature sensor is only accessed as words, and
330 * the temperature sensors are I2C. Thus, byte-swap the
331 * word.
332 */
333 lword = htobe16(*(uint16_t *)buf);
334 } else {
335 /* For byte operations, the data goes in the LSB, and
336 * the MSB is a don't care.
337 */
338 lword = *(uint8_t *)buf;
339 }
340 cmd_val |= lword;
341 }
342
343 /* Write the updated value to the control register first, to disable
344 * the hardware TSOD polling.
345 */
346 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag,
347 sc->sc_regs->smb_cntl, cntl_val);
348
349 /* Poll on the BUSY bit in the status register until clear, or timeout.
350 * We just cleared the auto-poll bit, so we need to make sure the device
351 * is idle before issuing a command. We can safely timeout after 35 ms,
352 * as this is the maximum time the SMBus spec allows for a transaction.
353 */
354 for (i = 4; i != 0; i--) {
355 stat_val = pci_conf_read(sc->sc_pci_chipset_tag,
356 sc->sc_pci_tag, sc->sc_regs->smb_stat);
357 if (! (stat_val & IMCSMB_STATUS_BUSY_BIT)) {
358 break;
359 }
360 delay(100); /* wait 10ms */
361 }
362
363 if (i == 0) {
364 aprint_debug_dev(sc->sc_dev,
365 "transfer: timeout waiting for device to settle\n");
366 }
367
368 /* Now that polling has stopped, we can write the command register. This
369 * starts the SMBus command.
370 */
371 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag,
372 sc->sc_regs->smb_cmd, cmd_val);
373
374 /* Wait for WRITE_DATA_DONE/READ_DATA_VALID to be set, or timeout and
375 * fail. We wait up to 35ms.
376 */
377 for (i = 35000; i != 0; i -= 10)
378 {
379 delay(10);
380 stat_val = pci_conf_read(sc->sc_pci_chipset_tag,
381 sc->sc_pci_tag, sc->sc_regs->smb_stat);
382 /*
383 * For a write, the bits holding the data contain the data
384 * being written. You would think that would cause the
385 * READ_DATA_VALID bit to be cleared, because the data bits
386 * no longer contain valid data from the most recent read
387 * operation. While that would be logical, that's not the
388 * case here: READ_DATA_VALID is only cleared when starting
389 * a read operation, and WRITE_DATA_DONE is only cleared
390 * when starting a write operation.
391 */
392 if (I2C_OP_WRITE_P(op)) {
393 if (stat_val & IMCSMB_STATUS_WRITE_DATA_DONE) {
394 break;
395 }
396 } else {
397 if (stat_val & IMCSMB_STATUS_READ_DATA_VALID) {
398 break;
399 }
400 }
401 }
402 if (i == 0) {
403 rc = ETIMEDOUT;
404 aprint_debug_dev(sc->sc_dev, "transfer timeout\n");
405 goto out;
406 }
407
408 /* It is generally the case that this bit indicates non-ACK, but it
409 * could also indicate other bus errors. There's no way to tell the
410 * difference.
411 */
412 if (stat_val & IMCSMB_STATUS_BUS_ERROR_BIT) {
413 /* While it is not documented, empirically, SPD page-change
414 * commands (writes with DTI = 0x30) always complete with the
415 * error bit set. So, ignore it in those cases.
416 */
417 if ((addr & 0x78) != 0x30) {
418 rc = ENODEV;
419 goto out;
420 }
421 }
422
423 /* For a read operation, copy the data out */
424 if (I2C_OP_READ_P(op)) {
425 if (len == 2) {
426 /* The data is returned in bits [15:0]; as discussed
427 * above, byte-swap.
428 */
429 lword = (uint16_t) (stat_val & 0xffff);
430 lword = htobe16(lword);
431 *(uint16_t *)buf = lword;
432 } else {
433 /* The data is returned in bits [7:0] */
434 lbyte = (uint8_t) (stat_val & 0xff);
435 *(uint8_t *)buf = lbyte;
436 }
437 }
438
439 out:
440 /* Restore the original value of the control register. */
441 pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag,
442 sc->sc_regs->smb_cntl, orig_cntl_val);
443 return rc;
444 };
445
446 MODULE(MODULE_CLASS_DRIVER, imcsmb, "imc,iic");
447
448 #ifdef _MODULE
449 #include "ioconf.c"
450 #endif
451
452 static int
imcsmb_modcmd(modcmd_t cmd,void * opaque)453 imcsmb_modcmd(modcmd_t cmd, void *opaque)
454 {
455 int error = 0;
456
457 #ifdef _MODULE
458 switch (cmd) {
459 case MODULE_CMD_INIT:
460 error = config_init_component(cfdriver_ioconf_imcsmb,
461 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb);
462 break;
463 case MODULE_CMD_FINI:
464 error = config_fini_component(cfdriver_ioconf_imcsmb,
465 cfattach_ioconf_imcsmb, cfdata_ioconf_imcsmb);
466 break;
467 default:
468 error = ENOTTY;
469 break;
470 }
471 #endif
472
473 return error;
474 }
475