1 /* $NetBSD: imc.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Goyette
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*-
33 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
34 *
35 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
36 *
37 * Copyright (c) 2017-2018 Panasas
38 * All rights reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in the
47 * documentation and/or other materials provided with the distribution.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
52 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 * SUCH DAMAGE.
60 */
61
62 /*
63 * Driver to expose the SMBus controllers in Intel's Integrated
64 * Memory Controllers in certain CPUs.
65 */
66
67 #include <sys/cdefs.h>
68 __KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $");
69
70 #include <sys/param.h>
71 #include <sys/kernel.h>
72 #include <sys/module.h>
73 #include <sys/errno.h>
74 #include <sys/mutex.h>
75 #include <sys/bus.h>
76
77 #include <dev/pci/pcidevs.h>
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcireg.h>
80
81 #include "imcsmb_reg.h"
82 #include "imcsmb_var.h"
83
84 #include "ioconf.h"
85
86 /* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two
87 * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
88 * SMBus controllers. These are used for reading SPD data from the DIMMs, and
89 * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
90 * are very simple devices, and have limited functionality compared to
91 * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs.
92 *
93 * The publicly available documentation for the iMC SMBus controllers can be
94 * found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and
95 * (Has,broad)well-Xeon, respectively:
96 *
97 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/
98 * Sandybridge xeon-e5-1600-2600-vol-2-datasheet.pdf
99 * Ivybridge xeon-e5-v2-datasheet-vol-2.pdf
100 * Haswell xeon-e5-v3-datasheet-vol-2.pdf
101 * Broadwell xeon-e5-v4-datasheet-vol-2.pdf
102 *
103 * Another useful resource is the Linux driver. It is not in the main tree.
104 *
105 * https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg840043.html
106 *
107 * The iMC SMBus controllers do not support interrupts (thus, they must be
108 * polled for IO completion). All of the iMC registers are in PCI configuration
109 * space; there is no support for PIO or MMIO. As a result, this driver does
110 * not need to perform and newbus resource manipulation.
111 *
112 * Because there are multiple SMBus controllers sharing the same PCI device,
113 * this driver is actually *two* drivers:
114 *
115 * - "imcsmb" is an smbus(4)-compliant SMBus controller driver
116 *
117 * - "imcsmb_pci" recognizes the PCI device and assigns the appropriate set of
118 * PCI config registers to a specific "imcsmb" instance.
119 */
120
121 /* Depending on the motherboard and firmware, the TSODs might be polled by
122 * firmware. Therefore, when this driver accesses these SMBus controllers, the
123 * firmware polling must be disabled as part of requesting the bus, and
124 * re-enabled when releasing the bus. Unfortunately, the details of how to do
125 * this are vendor-specific. Contact your motherboard vendor to get the
126 * information you need to do proper implementations.
127 *
128 * For NVDIMMs which conform to the ACPI "NFIT" standard, the ACPI firmware
129 * manages the NVDIMM; for those which pre-date the standard, the operating
130 * system interacts with the NVDIMM controller using a vendor-proprietary API
131 * over the SMBus. In that case, the NVDIMM driver would be an SMBus slave
132 * device driver, and would interface with the hardware via an SMBus controller
133 * driver such as this one.
134 */
135
136 /* PCIe device IDs for (Sandy,Ivy)bridge)-Xeon and (Has,Broad)well-Xeon */
137
138 #define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8
139 #define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8
140 #define IMCSMB_PCI_DEV_ID_IMC0_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC0_TATRR
141 #define IMCSMB_PCI_DEV_ID_IMC0_BDX PCI_PRODUCT_INTEL_XEOND_MEM_0_TTR_1
142
143 /* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */
144
145 #define IMCSMB_PCI_DEV_ID_IMC1_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC1_TATRR
146 #define IMCSMB_PCI_DEV_ID_IMC1_BDX PCI_PRODUCT_INTEL_COREI76K_IMC_0
147
148 /* There are two SMBus controllers in each device. These define the registers
149 * for each of these devices.
150 */
151 static struct imcsmb_reg_set imcsmb_regs[] = {
152 {
153 .smb_stat = IMCSMB_REG_STATUS0,
154 .smb_cmd = IMCSMB_REG_COMMAND0,
155 .smb_cntl = IMCSMB_REG_CONTROL0
156 },
157 {
158 .smb_stat = IMCSMB_REG_STATUS1,
159 .smb_cmd = IMCSMB_REG_COMMAND1,
160 .smb_cntl = IMCSMB_REG_CONTROL1
161 },
162 };
163
164 static struct imcsmb_pci_device {
165 uint16_t id;
166 const char *name;
167 } imcsmb_pci_devices[] = {
168 {IMCSMB_PCI_DEV_ID_IMC0_SBX,
169 "Intel Sandybridge Xeon iMC 0 SMBus controllers" },
170 {IMCSMB_PCI_DEV_ID_IMC0_IBX,
171 "Intel Ivybridge Xeon iMC 0 SMBus controllers" },
172 {IMCSMB_PCI_DEV_ID_IMC0_HSX,
173 "Intel Haswell Xeon iMC 0 SMBus controllers" },
174 {IMCSMB_PCI_DEV_ID_IMC1_HSX,
175 "Intel Haswell Xeon iMC 1 SMBus controllers" },
176 {IMCSMB_PCI_DEV_ID_IMC0_BDX,
177 "Intel Broadwell Xeon iMC 0 SMBus controllers" },
178 {IMCSMB_PCI_DEV_ID_IMC1_BDX,
179 "Intel Broadwell Xeon iMC 1 SMBus controllers" },
180 {0, NULL},
181 };
182
183 /* Device methods. */
184 static void imc_attach(device_t, device_t, void *);
185 static int imc_rescan(device_t, const char *, const int *);
186 static int imc_detach(device_t, int);
187 static int imc_probe(device_t, cfdata_t, void *);
188 static void imc_chdet(device_t, device_t);
189
190 CFATTACH_DECL3_NEW(imc, sizeof(struct imc_softc),
191 imc_probe, imc_attach, imc_detach, NULL, imc_rescan, imc_chdet, 0);
192
193 /**
194 * device_attach() method. Set up the PCI device's softc, then explicitly create
195 * children for the actual imcsmbX controllers. Set up the child's ivars to
196 * point to the proper set of the PCI device's config registers. Finally, probe
197 * and attach anything which might be downstream.
198 *
199 * @author Joe Kloss, rpokala
200 *
201 * @param[in,out] dev
202 * Device being attached.
203 */
204 static void
imc_attach(device_t parent,device_t self,void * aux)205 imc_attach(device_t parent, device_t self, void *aux)
206 {
207 struct imc_softc *sc = device_private(self);
208 struct pci_attach_args *pa = aux;
209 int i;
210
211 sc->sc_dev = self;
212 sc->sc_pci_tag = pa->pa_tag;
213 sc->sc_pci_chipset_tag = pa->pa_pc;
214
215 pci_aprint_devinfo(pa, NULL);
216
217 for (i = 0; imcsmb_pci_devices[i].id != 0; i++) {
218 if (PCI_PRODUCT(pa->pa_id) == imcsmb_pci_devices[i].id) {
219 aprint_normal_dev(self, "%s\n",
220 imcsmb_pci_devices[i].name);
221 break;
222 }
223 }
224
225 if (!pmf_device_register(self, NULL, NULL))
226 aprint_error_dev(self, "couldn't establish power handler\n");
227
228 imc_rescan(self, NULL, NULL);
229 }
230
231 /* Create the imcsmbX children */
232
233 static int
imc_rescan(device_t self,const char * ifattr,const int * locs)234 imc_rescan(device_t self, const char *ifattr, const int *locs)
235 {
236 struct imc_softc *sc = device_private(self);
237 struct imc_attach_args imca;
238 int unit;
239
240 for (unit = 0; unit < 2; unit++) {
241 if (sc->sc_smbchild[unit] != NULL)
242 continue;
243
244 imca.ia_unit = unit;
245 imca.ia_regs = &imcsmb_regs[unit];
246 imca.ia_pci_tag = sc->sc_pci_tag;
247 imca.ia_pci_chipset_tag = sc->sc_pci_chipset_tag;
248 sc->sc_smbchild[unit] =
249 config_found(self, &imca, NULL, CFARGS_NONE);
250 }
251
252 return 0;
253 }
254
255 /*
256 * device_detach() method. attach() didn't do any allocations, so there's
257 * nothing special needed
258 */
259 static int
imc_detach(device_t self,int flags)260 imc_detach(device_t self, int flags)
261 {
262 int error;
263
264 error = config_detach_children(self, flags);
265 if (error)
266 return error;
267
268 pmf_device_deregister(self);
269 return 0;
270 }
271
272 /**
273 * device_probe() method. Look for the right PCI vendor/device IDs.
274 *
275 * @author Joe Kloss, rpokala
276 *
277 * @param[in,out] dev
278 * Device being probed.
279 */
280 static int
imc_probe(device_t dev,cfdata_t cf,void * aux)281 imc_probe(device_t dev, cfdata_t cf, void *aux)
282 {
283 struct pci_attach_args *pa = aux;
284
285 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
286 switch(PCI_PRODUCT(pa->pa_id)) {
287 case PCI_PRODUCT_INTEL_COREI76K_IMC_0:
288 case PCI_PRODUCT_INTEL_XEOND_MEM_0_TTR_1:
289 case PCI_PRODUCT_INTEL_XE5_V3_IMC0_TATRR:
290 case PCI_PRODUCT_INTEL_XE5_V3_IMC1_TATRR:
291 case PCI_PRODUCT_INTEL_E5_IMC_TA:
292 case PCI_PRODUCT_INTEL_E5V2_IMC_TA:
293 return 1;
294 }
295 }
296 return 0;
297 }
298
299 /*
300 * child_detach() method
301 */
302 static void
imc_chdet(device_t self,device_t child)303 imc_chdet(device_t self, device_t child)
304 {
305 struct imc_softc *sc = device_private(self);
306 int unit;
307
308 for (unit = 0; unit < 2; unit++)
309 if (sc->sc_smbchild[unit] == child)
310 sc->sc_smbchild[unit] = NULL;
311 return;
312 }
313
314 /*
315 * bios/motherboard access control
316 *
317 * XXX
318 * If necessary, add the code here to prevent concurrent access to the
319 * IMC controllers. The softc argument is for the imcsmb child device
320 * (for the specific i2cbus instance); if you need to disable all
321 * i2cbus instances on a given IMC (or all instances on all IMCs), you
322 * may need to examine the softc's parent.
323 * XXX
324 */
325
326 kmutex_t imc_access_mutex;
327 static int imc_access_count = 0;
328
329 void
imc_callback(struct imcsmb_softc * sc,imc_bios_control action)330 imc_callback(struct imcsmb_softc *sc, imc_bios_control action)
331 {
332
333 mutex_enter(&imc_access_mutex);
334 switch (action) {
335 case IMC_BIOS_ENABLE:
336 imc_access_count--;
337 if (imc_access_count == 0) {
338 /*
339 * Insert motherboard-specific enable code here!
340 */
341 }
342 break;
343 case IMC_BIOS_DISABLE:
344 if (imc_access_count == 0) {
345 /*
346 * Insert motherboard-specific disable code here!
347 */
348 }
349 imc_access_count++;
350 break;
351 }
352 mutex_exit(&imc_access_mutex);
353 }
354
355 MODULE(MODULE_CLASS_DRIVER, imc, "pci");
356
357 #ifdef _MODULE
358 #include "ioconf.c"
359 #endif
360
361 static int
imc_modcmd(modcmd_t cmd,void * opaque)362 imc_modcmd(modcmd_t cmd, void *opaque)
363 {
364 int error = 0;
365
366 switch (cmd) {
367 case MODULE_CMD_INIT:
368 mutex_init(&imc_access_mutex, MUTEX_DEFAULT, IPL_NONE);
369 #ifdef _MODULE
370 error = config_init_component(cfdriver_ioconf_imc,
371 cfattach_ioconf_imc, cfdata_ioconf_imc);
372 #endif
373 break;
374
375 case MODULE_CMD_FINI:
376 #ifdef _MODULE
377 error = config_fini_component(cfdriver_ioconf_imc,
378 cfattach_ioconf_imc, cfdata_ioconf_imc);
379 #endif
380 if (error == 0)
381 mutex_destroy(&imc_access_mutex);
382 break;
383 default:
384 error = ENOTTY;
385 break;
386 }
387
388 return error;
389 }
390