1 /* $NetBSD: amdtemp.c,v 1.23 2018/12/30 15:43:43 is Exp $ */
2 /* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
3
4 /*
5 * Copyright (c) 2008 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Christoph Egger.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd@bugmail.mojo.ru>
35 *
36 * Permission to use, copy, modify, and distribute this software for any
37 * purpose with or without fee is hereby granted, provided that the above
38 * copyright notice and this permission notice appear in all copies.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
41 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
42 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
43 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
44 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
45 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
46 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
47 */
48
49 #include <sys/cdefs.h>
50 __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.23 2018/12/30 15:43:43 is Exp $ ");
51
52 #include <sys/param.h>
53 #include <sys/bus.h>
54 #include <sys/cpu.h>
55 #include <sys/systm.h>
56 #include <sys/device.h>
57 #include <sys/kmem.h>
58 #include <sys/module.h>
59
60 #include <machine/specialreg.h>
61
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
64 #include <dev/pci/pcidevs.h>
65
66 #include <dev/sysmon/sysmonvar.h>
67
68 /*
69 * AMD K8:
70 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
71 * AMD K8 Errata: #141
72 * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf
73 *
74 * Family10h:
75 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF
76 * Family10h Errata: #319
77 * http://support.amd.com/de/Processor_TechDocs/41322.pdf
78 *
79 * Family11h:
80 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf
81 */
82
83 /* AMD Processors, Function 3 -- Miscellaneous Control
84 */
85
86 /* Function 3 Registers */
87 #define THERMTRIP_STAT_R 0xe4
88 #define NORTHBRIDGE_CAP_R 0xe8
89 #define CPUID_FAMILY_MODEL_R 0xfc
90
91 /*
92 * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control
93 */
94
95 /* Bits within Thermtrip Status Register */
96 #define K8_THERM_SENSE_SEL (1 << 6)
97 #define K8_THERM_SENSE_CORE_SEL (1 << 2)
98
99 /* Flip core and sensor selection bits */
100 #define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL)
101 #define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL))
102 #define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL))
103 #define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL)
104
105 /*
106 * AMD Family 10h Processors, Function 3 -- Miscellaneous Control
107 */
108
109 /* Function 3 Registers */
110 #define F10_TEMPERATURE_CTL_R 0xa4
111 #define F10_TEMP_CURTMP __BITS(31,21)
112
113 /*
114 * Revision Guide for AMD NPT Family 0Fh Processors,
115 * Publication # 33610, Revision 3.30, February 2008
116 */
117 #define K8_SOCKET_F 1 /* Server */
118 #define K8_SOCKET_AM2 2 /* Desktop */
119 #define K8_SOCKET_S1 3 /* Laptop */
120
121 static const struct {
122 const char rev[5];
123 const struct {
124 const pcireg_t cpuid;
125 const uint8_t socket;
126 } cpu[5];
127 } amdtemp_core[] = {
128 { "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */
129 { 0x00040F80, K8_SOCKET_S1 }, /* F2 */
130 { 0, 0 }, { 0, 0 }, { 0, 0 } } },
131 { "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */
132 { 0x00040FC0, K8_SOCKET_S1 }, /* F2 */
133 { 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */
134 { 0, 0 }, { 0, 0 } } },
135 { "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */
136 { 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */
137 { 0x000C0F10, K8_SOCKET_F }, /* F3 */
138 { 0, 0 }, { 0, 0 } } },
139 { "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */
140 { 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */
141 { 0, 0 }, { 0, 0 }, { 0, 0 } } },
142 { "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */
143 { 0x00060FC0, K8_SOCKET_S1 }, /* G2 */
144 { 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */
145 { 0x00070FC0, K8_SOCKET_S1 }, /* G2 */
146 { 0, 0 } } }
147 };
148
149 struct amdtemp_softc {
150 pci_chipset_tag_t sc_pc;
151 pcitag_t sc_pcitag;
152
153 struct sysmon_envsys *sc_sme;
154 envsys_data_t *sc_sensor;
155 size_t sc_sensor_len;
156
157 char sc_rev;
158 int8_t sc_numsensors;
159 uint32_t sc_family;
160 int32_t sc_adjustment;
161 };
162
163 static int amdtemp_match(device_t, cfdata_t, void *);
164 static void amdtemp_attach(device_t, device_t, void *);
165 static int amdtemp_detach(device_t, int);
166
167 static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t);
168 static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int);
169 static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *);
170
171 static void amdtemp_family10_init(struct amdtemp_softc *);
172 static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int);
173 static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *);
174
175 CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc),
176 amdtemp_match, amdtemp_attach, amdtemp_detach, NULL);
177
178 static int
amdtemp_match(device_t parent,cfdata_t match,void * aux)179 amdtemp_match(device_t parent, cfdata_t match, void *aux)
180 {
181 struct pci_attach_args *pa = aux;
182 pcireg_t cpu_signature;
183 uint32_t family;
184
185 KASSERT(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD);
186
187 cpu_signature = pci_conf_read(pa->pa_pc,
188 pa->pa_tag, CPUID_FAMILY_MODEL_R);
189
190 /*
191 * This CPUID northbridge register has been introduced in
192 * Revision F.
193 */
194 if (cpu_signature == 0x0)
195 return 0;
196
197 family = CPUID_TO_FAMILY(cpu_signature);
198
199 /* Errata #319: This has been fixed in Revision C2. */
200 if (family == 0x10) {
201 if (CPUID_TO_BASEMODEL(cpu_signature) < 4)
202 return 0;
203 if (CPUID_TO_BASEMODEL(cpu_signature) == 4 &&
204 CPUID_TO_STEPPING(cpu_signature) < 2)
205 return 0;
206 }
207
208 /* Not yet supported CPUs. */
209 if (family > 0x16)
210 return 0;
211
212 return 1;
213 }
214
215 static void
amdtemp_attach(device_t parent,device_t self,void * aux)216 amdtemp_attach(device_t parent, device_t self, void *aux)
217 {
218 struct amdtemp_softc *sc = device_private(self);
219 struct pci_attach_args *pa = aux;
220 pcireg_t cpu_signature;
221 int error;
222 uint8_t i;
223
224 aprint_naive("\n");
225 aprint_normal(": AMD CPU Temperature Sensors");
226
227 cpu_signature = pci_conf_read(pa->pa_pc,
228 pa->pa_tag, CPUID_FAMILY_MODEL_R);
229
230 /* If we hit this, then match routine is wrong. */
231 KASSERT(cpu_signature != 0x0);
232
233 sc->sc_family = CPUID_TO_FAMILY(cpu_signature);
234
235 KASSERT(sc->sc_family >= 0xf);
236
237 sc->sc_sme = NULL;
238 sc->sc_sensor = NULL;
239
240 sc->sc_pc = pa->pa_pc;
241 sc->sc_pcitag = pa->pa_tag;
242 sc->sc_adjustment = 0;
243
244 switch (sc->sc_family) {
245 case 0xf: /* AMD K8 NPT */
246 amdtemp_k8_init(sc, cpu_signature);
247 break;
248
249 case 0x10: /* AMD Barcelona/Phenom */
250 case 0x11: /* AMD Griffin */
251 case 0x12: /* AMD Lynx/Sabine (Llano) */
252 case 0x14: /* AMD Brazos (Ontario/Zacate/Desna) */
253 case 0x15: /* AMD Bobcat */
254 case 0x16: /* AMD Puma/Jaguar */
255 amdtemp_family10_init(sc);
256 break;
257
258 default:
259 aprint_normal(", family 0x%x not supported\n",
260 sc->sc_family);
261 return;
262 }
263
264 aprint_normal("\n");
265
266 if (sc->sc_adjustment != 0)
267 aprint_debug_dev(self, "Workaround enabled\n");
268
269 sc->sc_sme = sysmon_envsys_create();
270 sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors;
271 sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP);
272
273 switch (sc->sc_family) {
274 case 0xf:
275 amdtemp_k8_setup_sensors(sc, device_unit(self));
276 break;
277 case 0x10:
278 case 0x11:
279 case 0x12:
280 case 0x14:
281 case 0x15:
282 case 0x16:
283 amdtemp_family10_setup_sensors(sc, device_unit(self));
284 break;
285 }
286
287 /*
288 * Set properties in sensors.
289 */
290 for (i = 0; i < sc->sc_numsensors; i++) {
291 if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[i]))
292 goto bad;
293 }
294
295 /*
296 * Register the sysmon_envsys device.
297 */
298 sc->sc_sme->sme_name = device_xname(self);
299 sc->sc_sme->sme_cookie = sc;
300
301 switch (sc->sc_family) {
302 case 0xf:
303 sc->sc_sme->sme_refresh = amdtemp_k8_refresh;
304 break;
305 case 0x10:
306 case 0x11:
307 case 0x12:
308 case 0x14:
309 case 0x15:
310 case 0x16:
311 sc->sc_sme->sme_refresh = amdtemp_family10_refresh;
312 break;
313 }
314
315 error = sysmon_envsys_register(sc->sc_sme);
316 if (error) {
317 aprint_error_dev(self, "unable to register with sysmon "
318 "(error=%d)\n", error);
319 goto bad;
320 }
321
322 (void)pmf_device_register(self, NULL, NULL);
323
324 return;
325
326 bad:
327 if (sc->sc_sme != NULL) {
328 sysmon_envsys_destroy(sc->sc_sme);
329 sc->sc_sme = NULL;
330 }
331
332 if (sc->sc_sensor != NULL) {
333 kmem_free(sc->sc_sensor, sc->sc_sensor_len);
334 sc->sc_sensor = NULL;
335 }
336 }
337
338 static int
amdtemp_detach(device_t self,int flags)339 amdtemp_detach(device_t self, int flags)
340 {
341 struct amdtemp_softc *sc = device_private(self);
342
343 pmf_device_deregister(self);
344 if (sc->sc_sme != NULL)
345 sysmon_envsys_unregister(sc->sc_sme);
346
347 if (sc->sc_sensor != NULL)
348 kmem_free(sc->sc_sensor, sc->sc_sensor_len);
349
350 return 0;
351 }
352
353 static void
amdtemp_k8_init(struct amdtemp_softc * sc,pcireg_t cpu_signature)354 amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature)
355 {
356 pcireg_t data;
357 uint32_t cmpcap;
358 uint8_t i, j;
359
360 aprint_normal(" (K8");
361
362 for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) {
363 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) {
364 if ((cpu_signature & ~0xf)
365 != amdtemp_core[i].cpu[j].cpuid)
366 continue;
367
368 sc->sc_rev = amdtemp_core[i].rev[3];
369 aprint_normal(": core rev %.4s%.1x",
370 amdtemp_core[i].rev,
371 CPUID_TO_STEPPING(cpu_signature));
372
373 switch (amdtemp_core[i].cpu[j].socket) {
374 case K8_SOCKET_AM2:
375 if (sc->sc_rev == 'G')
376 sc->sc_adjustment = 21000000;
377 aprint_normal(", socket AM2");
378 break;
379 case K8_SOCKET_S1:
380 aprint_normal(", socket S1");
381 break;
382 case K8_SOCKET_F:
383 aprint_normal(", socket F");
384 break;
385 }
386 }
387 }
388
389 if (sc->sc_rev == '\0') {
390 /*
391 * CPUID Family Model Register was introduced in
392 * Revision F
393 */
394 sc->sc_rev = 'G'; /* newer than E, assume G */
395 aprint_normal(": cpuid 0x%x", cpu_signature);
396 }
397
398 aprint_normal(")");
399
400 data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R);
401 cmpcap = (data >> 12) & 0x3;
402
403 sc->sc_numsensors = cmpcap ? 4 : 2;
404 }
405
406 static void
amdtemp_k8_setup_sensors(struct amdtemp_softc * sc,int dv_unit)407 amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit)
408 {
409 uint8_t i;
410
411 /*
412 * There are two sensors per CPU core. So we use the device unit as
413 * socket counter to correctly enumerate the CPUs on multi-socket
414 * machines.
415 */
416 dv_unit *= (sc->sc_numsensors / 2);
417 for (i = 0; i < sc->sc_numsensors; i++) {
418 sc->sc_sensor[i].units = ENVSYS_STEMP;
419 sc->sc_sensor[i].state = ENVSYS_SVALID;
420 sc->sc_sensor[i].flags = ENVSYS_FHAS_ENTROPY;
421
422 snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc),
423 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2);
424 }
425 }
426
427 static void
amdtemp_k8_refresh(struct sysmon_envsys * sme,envsys_data_t * edata)428 amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
429 {
430 struct amdtemp_softc *sc = sme->sme_cookie;
431 pcireg_t status, match, tmp;
432 uint32_t value;
433
434 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R);
435
436 switch (edata->sensor) { /* sensor number */
437 case 0: /* Core 0 Sensor 0 */
438 K8_T_SEL_C0(status);
439 K8_T_SEL_S0(status);
440 break;
441 case 1: /* Core 0 Sensor 1 */
442 K8_T_SEL_C0(status);
443 K8_T_SEL_S1(status);
444 break;
445 case 2: /* Core 1 Sensor 0 */
446 K8_T_SEL_C1(status);
447 K8_T_SEL_S0(status);
448 break;
449 case 3: /* Core 1 Sensor 1 */
450 K8_T_SEL_C1(status);
451 K8_T_SEL_S1(status);
452 break;
453 }
454
455 match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL);
456 pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status);
457 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R);
458 tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL);
459
460 value = 0x3ff & (status >> 14);
461 if (sc->sc_rev != 'G')
462 value &= ~0x3;
463
464 edata->state = ENVSYS_SINVALID;
465 if ((tmp == match) && ((value & ~0x3) != 0)) {
466 edata->state = ENVSYS_SVALID;
467 edata->value_cur = (value * 250000 - 49000000) + 273150000 +
468 sc->sc_adjustment;
469 }
470 }
471
472 static void
amdtemp_family10_init(struct amdtemp_softc * sc)473 amdtemp_family10_init(struct amdtemp_softc *sc)
474 {
475 aprint_normal(" (Family%02xh)", sc->sc_family);
476
477 sc->sc_numsensors = 1;
478 }
479
480 static void
amdtemp_family10_setup_sensors(struct amdtemp_softc * sc,int dv_unit)481 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit)
482 {
483 /* sanity check for future enhancements */
484 KASSERT(sc->sc_numsensors == 1);
485
486 /*
487 * There's one sensor per memory controller (= socket), so we use the
488 * device unit as socket counter to correctly enumerate the CPUs.
489 */
490 sc->sc_sensor[0].units = ENVSYS_STEMP;
491 sc->sc_sensor[0].state = ENVSYS_SVALID;
492 sc->sc_sensor[0].flags = ENVSYS_FHAS_ENTROPY;
493
494 snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc),
495 "cpu%u temperature", dv_unit);
496 }
497
498 static void
amdtemp_family10_refresh(struct sysmon_envsys * sme,envsys_data_t * edata)499 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
500 {
501 struct amdtemp_softc *sc = sme->sme_cookie;
502 pcireg_t status;
503 uint32_t value;
504
505 status = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
506 F10_TEMPERATURE_CTL_R);
507 value = __SHIFTOUT(status, F10_TEMP_CURTMP);
508
509 /* From Celsius to micro-Kelvin. */
510 edata->value_cur = (value * 125000) + 273150000;
511 edata->state = ENVSYS_SVALID;
512 }
513
514 MODULE(MODULE_CLASS_DRIVER, amdtemp, "sysmon_envsys");
515
516 #ifdef _MODULE
517 #include "ioconf.c"
518 #endif
519
520 static int
amdtemp_modcmd(modcmd_t cmd,void * aux)521 amdtemp_modcmd(modcmd_t cmd, void *aux)
522 {
523 int error = 0;
524
525 switch (cmd) {
526 case MODULE_CMD_INIT:
527 #ifdef _MODULE
528 error = config_init_component(cfdriver_ioconf_amdtemp,
529 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp);
530 #endif
531 return error;
532 case MODULE_CMD_FINI:
533 #ifdef _MODULE
534 error = config_fini_component(cfdriver_ioconf_amdtemp,
535 cfattach_ioconf_amdtemp, cfdata_ioconf_amdtemp);
536 #endif
537 return error;
538 default:
539 return ENOTTY;
540 }
541 }
542