1 /* $NetBSD: intr.h,v 1.2 2024/01/19 05:46:36 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2023 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _VIRT68K_INTR_H_
33 #define _VIRT68K_INTR_H_
34
35 #include <machine/psl.h>
36
37 /*
38 * The Qemu virt68k platform uses 6 Goldfish PICs. Each PIC is
39 * connected to one of the CPU interrupt inputs:
40 *
41 * CPU IRQ 1 -> PIC 1
42 * IRQ 1-31 unused
43 * IRQ 32 goldfish-tty
44 *
45 * CPU IRQ 2 -> PIC 2
46 * IRQ 1-32 virtio-mmio 1-32
47 *
48 * CPU IRQ 3 -> PIC 3
49 * IRQ 1-32 virtio-mmio 33-64
50 *
51 * CPU IRQ 4 -> PIC 4
52 * IRQ 1-32 virtio-mmio 65-96
53 *
54 * CPU IRQ 5 -> PIC 5
55 * IRQ 1-32 virtio-mmio 97-128
56 *
57 * CPU IRQ 6 -> PIC 6
58 * IRQ 1 goldfish-rtc
59 * IRQ 2-32 unused
60 *
61 * CPU IRQ 7 -> NMI
62 *
63 * Qemu counts the 8 CPU IPLs as IRQs, so then the IRQ numbers
64 * reported in the bootinfo are:
65 *
66 * IRQ0 CPU IPL0
67 * ...
68 * IRQ7 CPU IPL7
69 * IRQ8 PIC 1 IRQ 1 IPL1
70 * ...
71 * IRQ39 PIC 1 IRQ 32
72 * IRQ40 PIC 2 IRQ 1 IPL2
73 * ...
74 * IRQ71 PIC 2 IRQ 32
75 * . IPL3
76 * . .
77 * . .
78 *
79 * Unfortunately for us, there is a hardware interrupt at IPL1,
80 * and the m68k platforms have historically used IPL1 as the
81 * soft interrupt IPL. We will continue to do this, but may have
82 * to re-think things if it negatively impacts using the Goldfish
83 * TTY console.
84 */
85
86 #define IRQ_CPU_BASE 1 /* can't hook up to "IPL0" */
87 #define IRQ_PIC_BASE 8
88 #define IRQ_TO_PIC(x) (((x) - IRQ_PIC_BASE) >> 5)
89 #define IRQ_TO_PIRQ(x) (((x) - IRQ_PIC_BASE) & 31)
90 #define NPIC 6
91 #define NIRQ_PER_PIC 32
92
93 #define NIRQ (IRQ_PIC_BASE + (NIRQ_PER_PIC * NPIC))
94
95 #define IPL_NONE 0
96 #define IPL_SOFTCLOCK 1 /* clock software interrupts */
97 #define IPL_SOFTBIO 1 /* block software interrupts */
98 #define IPL_SOFTNET 1 /* network software interrupts */
99 #define IPL_SOFTSERIAL 1 /* serial software interrupts */
100 #define IPL_VM 5
101 #define IPL_SCHED 6
102 #define IPL_HIGH 7
103 #define NIPL 8
104
105 #if defined(_KERNEL) || defined(_KMEMUSER)
106 typedef struct {
107 uint16_t _psl;
108 } ipl_cookie_t;
109 #endif
110
111 #ifdef _KERNEL
112 #define spl0() _spl0()
113 #define splsoftclock() splraise1()
114 #define splsoftbio() splraise1()
115 #define splsoftnet() splraise1()
116 #define splsoftserial() splraise1()
117 #define splvm() splraise5()
118 #define splsched() splraise6()
119 #define splhigh() spl7()
120
121 #ifndef _LOCORE
122
123 extern const uint16_t ipl2psl_table[NIPL];
124
125 typedef int ipl_t;
126
127 static __inline ipl_cookie_t
makeiplcookie(ipl_t ipl)128 makeiplcookie(ipl_t ipl)
129 {
130
131 return (ipl_cookie_t){._psl = ipl2psl_table[ipl]};
132 }
133
134 static __inline int
splraiseipl(ipl_cookie_t icookie)135 splraiseipl(ipl_cookie_t icookie)
136 {
137
138 return _splraise(icookie._psl);
139 }
140
141 static __inline void
splx(int sr)142 splx(int sr)
143 {
144
145 __asm volatile("movw %0,%%sr" : : "di" (sr));
146 }
147
148 #define INTR_STRING_BUFSIZE 64
149
150 void intr_init(void);
151 void *intr_establish(int (*)(void *), void *, int, int, int);
152 void intr_disestablish(void *);
153 const char *intr_string(void *, char *, size_t);
154
155 struct device; /* XXX */
156 void intr_register_pic(struct device *, int);
157
158 /* Flags for intr_establish() */
159 #define INTR_F_MPSAFE __BIT(0)
160
161 #ifdef _VIRT68K_INTR_PRIVATE
162 #include <sys/cpu.h>
163 #include <sys/device.h>
164
165 void intr_dispatch(struct clockframe);
166 #endif /* _VIRT68K_INTR_PRIVATE */
167
168 #endif /* !_LOCORE */
169 #endif /* _KERNEL */
170
171 #endif /* _VIRT68K_INTR_H_ */
172