1 /* $NetBSD: bus_space.h,v 1.1 2024/01/02 07:41:00 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (C) 1997 Scott Reynolds. All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #ifndef _VIRT68K_BUS_SPACE_H_
60 #define _VIRT68K_BUS_SPACE_H_
61
62 /*
63 * Addresses (in bus space).
64 */
65 typedef u_long bus_addr_t;
66 typedef u_long bus_size_t;
67
68 #define PRIxBUSADDR "lx"
69 #define PRIxBUSSIZE "lx"
70 #define PRIuBUSSIZE "lu"
71
72 /*
73 * Access methods for bus resources and address space.
74 */
75 struct virt68k_bus_space_tag;
76 typedef struct virt68k_bus_space_tag *bus_space_tag_t;
77 typedef u_long bus_space_handle_t;
78
79 #define PRIxBSH "lx"
80
81 struct virt68k_bus_space_tag {
82 void *bs_cookie;
83 int (*bs_map)(void *, bus_addr_t, bus_size_t,
84 int, bus_space_handle_t *);
85 void (*bs_unmap)(void *, bus_space_handle_t, bus_size_t);
86 int (*bs_peek_1)(void *, bus_space_handle_t,
87 bus_size_t, uint8_t *);
88 int (*bs_peek_2)(void *, bus_space_handle_t,
89 bus_size_t, uint16_t *);
90 int (*bs_peek_4)(void *, bus_space_handle_t,
91 bus_size_t, uint32_t *);
92 #if 0
93 int (*bs_peek_8)(void *, bus_space_handle_t,
94 bus_size_t, uint64_t *);
95 #endif
96 int (*bs_poke_1)(void *, bus_space_handle_t,
97 bus_size_t, uint8_t);
98 int (*bs_poke_2)(void *, bus_space_handle_t,
99 bus_size_t, uint16_t);
100 int (*bs_poke_4)(void *, bus_space_handle_t,
101 bus_size_t, uint32_t);
102 #if 0
103 int (*bs_poke_8)(void *, bus_space_handle_t,
104 bus_size_t, uint64_t);
105 #endif
106 };
107
108 /*
109 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
110 * bus_size_t size, int flags,
111 * bus_space_handle_t *bshp);
112 *
113 * Map a region of bus space.
114 */
115 #define bus_space_map(tag, offset, size, flags, handlep) \
116 (*((tag)->bs_map))((tag)->bs_cookie, (offset), (size), (flags), (handlep))
117
118 /*
119 * Possible values for the 'flags' parameter of bus_space_map()
120 */
121 #define BUS_SPACE_MAP_CACHEABLE 0x01
122 #define BUS_SPACE_MAP_LINEAR 0x02
123 #define BUS_SPACE_MAP_PREFETCHABLE 0x04
124
125 /*
126 * void bus_space_unmap(bus_space_tag_t t,
127 * bus_space_handle_t bsh, bus_size_t size);
128 *
129 * Unmap a region of bus space.
130 */
131 #define bus_space_unmap(tag, handle, size) \
132 (*((tag)->bs_unmap))((tag)->bs_cookie, (handle), (size))
133
134 /*
135 * int bus_space_subregion(bus_space_tag_t t, bus_space_handle_t h
136 * bus_addr_t offset, bus_size_t size, bus_space_handle_t *newh);
137 *
138 * Allocate a sub-region of an existing map
139 */
140 #define bus_space_subregion(t, h, o, s, hp) \
141 ((*(hp)=(h)+(o)), 0)
142
143 /*
144 * Allocation and deallocation operations.
145 */
146 #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
147 (-1)
148
149 #define bus_space_free(t, h, s)
150
151 /*
152 * int bus_space_peek_N(bus_space_tag_t tag,
153 * bus_space_handle_t bsh, bus_size_t offset, uintN_t *valuep);
154 *
155 * Cautiously read 1, 2, 4 or 8 byte quantity from bus space described
156 * by tag/handle/offset.
157 * If no hardware responds to the read access, the function returns a
158 * non-zero value. Otherwise the value read is placed in `valuep'.
159 */
160 #define bus_space_peek_1(t, h, o, vp) \
161 (*((t)->bs_peek_1))((t)->bs_cookie, (h), (o), (vp))
162
163 #define bus_space_peek_2(t, h, o, vp) \
164 (*((t)->bs_peek_2))((t)->bs_cookie, (h), (o), (vp))
165
166 #define bus_space_peek_4(t, h, o, vp) \
167 (*((t)->bs_peek_4))((t)->bs_cookie, (h), (o), (vp))
168
169 /*
170 * int bus_space_poke_N(bus_space_tag_t tag,
171 * bus_space_handle_t bsh, bus_size_t offset, uintN_t value);
172 *
173 * Cautiously write 1, 2, 4 or 8 byte quantity to bus space described
174 * by tag/handle/offset.
175 * If no hardware responds to the write access, the function returns a
176 * non-zero value.
177 */
178 #define bus_space_poke_1(t, h, o, v) \
179 (*((t)->bs_poke_1))((t)->bs_cookie, (h), (o), (v))
180
181 #define bus_space_poke_2(t, h, o, v) \
182 (*((t)->bs_poke_2))((t)->bs_cookie, (h), (o), (v))
183
184 #define bus_space_poke_4(t, h, o, v) \
185 (*((t)->bs_poke_4))((t)->bs_cookie, (h), (o), (v))
186
187 /*
188 * uintN_t bus_space_read_N(bus_space_tag_t tag,
189 * bus_space_handle_t bsh, bus_size_t offset);
190 *
191 * Read a 1, 2, 4, or 8 byte quantity from bus space
192 * described by tag/handle/offset.
193 */
194 static inline uint8_t
bus_space_read_1(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o)195 bus_space_read_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
196 {
197 (void) t;
198 return *(volatile uint8_t *)((intptr_t)(h + o));
199 }
200
201 static inline uint16_t
bus_space_read_2(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o)202 bus_space_read_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
203 {
204 (void) t;
205 return *(volatile uint16_t *)((intptr_t)(h + o));
206 }
207
208 static inline uint32_t
bus_space_read_4(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o)209 bus_space_read_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
210 {
211 (void) t;
212 return *(volatile uint32_t *)((intptr_t)(h + o));
213 }
214
215 /*
216 * void bus_space_read_multi_N(bus_space_tag_t tag,
217 * bus_space_handle_t bsh, bus_size_t offset,
218 * uintN_t *addr, size_t count);
219 *
220 * Read `count' 1, 2, 4, or 8 byte quantities from bus space
221 * described by tag/handle/offset and copy into buffer provided.
222 */
223
224 #define bus_space_read_multi_1(t, h, o, a, c) do { \
225 (void) t; \
226 __asm volatile (" \
227 movl %0,%%a0 ; \
228 movl %1,%%a1 ; \
229 movl %2,%%d0 ; \
230 1: movb %%a0@,%%a1@+ ; \
231 subql #1,%%d0 ; \
232 jne 1b" : \
233 : \
234 "r" ((h) + (o)), "g" (a), "g" (c) : \
235 "a0","a1","d0","memory"); \
236 } while (0);
237
238 #define bus_space_read_multi_2(t, h, o, a, c) do { \
239 (void) t; \
240 __asm volatile (" \
241 movl %0,%%a0 ; \
242 movl %1,%%a1 ; \
243 movl %2,%%d0 ; \
244 1: movw %%a0@,%%a1@+ ; \
245 subql #1,%%d0 ; \
246 jne 1b" : \
247 : \
248 "r" ((h) + (o)), "g" (a), "g" (c) : \
249 "a0","a1","d0","memory"); \
250 } while (0);
251
252 #define bus_space_read_multi_4(t, h, o, a, c) do { \
253 (void) t; \
254 __asm volatile (" \
255 movl %0,%%a0 ; \
256 movl %1,%%a1 ; \
257 movl %2,%%d0 ; \
258 1: movl %%a0@,%%a1@+ ; \
259 subql #1,%%d0 ; \
260 jne 1b" : \
261 : \
262 "r" ((h) + (o)), "g" (a), "g" (c) : \
263 "a0","a1","d0","memory"); \
264 } while (0);
265
266 /*
267 * void bus_space_read_region_N(bus_space_tag_t tag,
268 * bus_space_handle_t bsh, bus_size_t offset,
269 * uintN_t *addr, size_t count);
270 *
271 * Read `count' 1, 2, 4, or 8 byte quantities from bus space
272 * described by tag/handle and starting at `offset' and copy into
273 * buffer provided.
274 */
275
276 #define bus_space_read_region_1(t, h, o, a, c) do { \
277 (void) t; \
278 __asm volatile (" \
279 movl %0,%%a0 ; \
280 movl %1,%%a1 ; \
281 movl %2,%%d0 ; \
282 1: movb %%a0@+,%%a1@+ ; \
283 subql #1,%%d0 ; \
284 jne 1b" : \
285 : \
286 "r" ((h) + (o)), "g" (a), "g" (c) : \
287 "a0","a1","d0","memory"); \
288 } while (0);
289
290 #define bus_space_read_region_2(t, h, o, a, c) do { \
291 (void) t; \
292 __asm volatile (" \
293 movl %0,%%a0 ; \
294 movl %1,%%a1 ; \
295 movl %2,%%d0 ; \
296 1: movw %%a0@+,%%a1@+ ; \
297 subql #1,%%d0 ; \
298 jne 1b" : \
299 : \
300 "r" ((h) + (o)), "g" (a), "g" (c) : \
301 "a0","a1","d0","memory"); \
302 } while (0);
303
304 #define bus_space_read_region_4(t, h, o, a, c) do { \
305 (void) t; \
306 __asm volatile (" \
307 movl %0,%%a0 ; \
308 movl %1,%%a1 ; \
309 movl %2,%%d0 ; \
310 1: movl %%a0@+,%%a1@+ ; \
311 subql #1,%%d0 ; \
312 jne 1b" : \
313 : \
314 "r" ((h) + (o)), "g" (a), "g" (c) : \
315 "a0","a1","d0","memory"); \
316 } while (0);
317
318 /*
319 * void bus_space_write_N(bus_space_tag_t tag,
320 * bus_space_handle_t bsh, bus_size_t offset,
321 * uintN_t value);
322 *
323 * Write the 1, 2, 4, or 8 byte value `value' to bus space
324 * described by tag/handle/offset.
325 */
326 #define bus_space_write_1(t,h,o,v) \
327 do { \
328 (void) t; \
329 *((volatile uint8_t *)(intptr_t)((h) + (o))) = (v); \
330 } while (/*CONSTCOND*/0)
331 #define bus_space_write_2(t,h,o,v) \
332 do { \
333 (void) t; \
334 *((volatile uint16_t *)(intptr_t)((h) + (o))) = (v); \
335 } while (/*CONSTCOND*/0)
336 #define bus_space_write_4(t,h,o,v) \
337 do { \
338 (void) t; \
339 *((volatile uint32_t *)(intptr_t)((h) + (o))) = (v); \
340 } while (/*CONSTCOND*/0)
341
342 /*
343 * void bus_space_write_multi_N(bus_space_tag_t tag,
344 * bus_space_handle_t bsh, bus_size_t offset,
345 * const uintN_t *addr, size_t count);
346 *
347 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
348 * provided to bus space described by tag/handle/offset.
349 */
350
351 #define bus_space_write_multi_1(t, h, o, a, c) do { \
352 (void) t; \
353 __asm volatile (" \
354 movl %0,%%a0 ; \
355 movl %1,%%a1 ; \
356 movl %2,%%d0 ; \
357 1: movb %%a1@+,%%a0@ ; \
358 subql #1,%%d0 ; \
359 jne 1b" : \
360 : \
361 "r" ((h) + (o)), "g" (a), "g" (c) : \
362 "a0","a1","d0"); \
363 } while (0);
364
365 #define bus_space_write_multi_2(t, h, o, a, c) do { \
366 (void) t; \
367 __asm volatile (" \
368 movl %0,%%a0 ; \
369 movl %1,%%a1 ; \
370 movl %2,%%d0 ; \
371 1: movw %%a1@+,%%a0@ ; \
372 subql #1,%%d0 ; \
373 jne 1b" : \
374 : \
375 "r" ((h) + (o)), "g" (a), "g" (c) : \
376 "a0","a1","d0"); \
377 } while (0);
378
379 #define bus_space_write_multi_4(t, h, o, a, c) do { \
380 (void) t; \
381 __asm volatile (" \
382 movl %0,%%a0 ; \
383 movl %1,%%a1 ; \
384 movl %2,%%d0 ; \
385 1: movl a1@+,%%a0@ ; \
386 subql #1,%%d0 ; \
387 jne 1b" : \
388 : \
389 "r" ((h) + (o)), "g" (a), "g" (c) : \
390 "a0","a1","d0"); \
391 } while (0);
392
393 /*
394 * void bus_space_write_region_N(bus_space_tag_t tag,
395 * bus_space_handle_t bsh, bus_size_t offset,
396 * const uintN_t *addr, size_t count);
397 *
398 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
399 * to bus space described by tag/handle starting at `offset'.
400 */
401
402 #define bus_space_write_region_1(t, h, o, a, c) do { \
403 (void) t; \
404 __asm volatile (" \
405 movl %0,%%a0 ; \
406 movl %1,%%a1 ; \
407 movl %2,%%d0 ; \
408 1: movb %%a1@+,%%a0@+ ; \
409 subql #1,%%d0 ; \
410 jne 1b" : \
411 : \
412 "r" ((h) + (o)), "g" (a), "g" (c) : \
413 "a0","a1","d0"); \
414 } while (0);
415
416 #define bus_space_write_region_2(t, h, o, a, c) do { \
417 (void) t; \
418 __asm volatile (" \
419 movl %0,%%a0 ; \
420 movl %1,%%a1 ; \
421 movl %2,%%d0 ; \
422 1: movw %%a1@+,%%a0@+ ; \
423 subql #1,%%d0 ; \
424 jne 1b" : \
425 : \
426 "r" ((h) + (o)), "g" (a), "g" (c) : \
427 "a0","a1","d0"); \
428 } while (0);
429
430 #define bus_space_write_region_4(t, h, o, a, c) do { \
431 (void) t; \
432 __asm volatile (" \
433 movl %0,%%a0 ; \
434 movl %1,%%a1 ; \
435 movl %2,%%d0 ; \
436 1: movl %%a1@+,%%a0@+ ; \
437 subql #1,%%d0 ; \
438 jne 1b" : \
439 : \
440 "r" ((h) + (o)), "g" (a), "g" (c) : \
441 "a0","a1","d0"); \
442 } while (0);
443
444 /*
445 * void bus_space_set_multi_N(bus_space_tag_t tag,
446 * bus_space_handle_t bsh, bus_size_t offset, uintN_t val,
447 * size_t count);
448 *
449 * Write the 1, 2, 4, or 8 byte value `val' to bus space described
450 * by tag/handle/offset `count' times.
451 */
452
453 #define bus_space_set_multi_1(t, h, o, val, c) do { \
454 (void) t; \
455 __asm volatile (" \
456 movl %0,%%a0 ; \
457 movl %1,%%d1 ; \
458 movl %2,%%d0 ; \
459 1: movb %%d1,%%a0@ ; \
460 subql #1,%%d0 ; \
461 jne 1b" : \
462 : \
463 "r" ((h) + (o)), "g" (val), "g" (c) : \
464 "a0","d0","d1"); \
465 } while (0);
466
467 #define bus_space_set_multi_2(t, h, o, val, c) do { \
468 (void) t; \
469 __asm volatile (" \
470 movl %0,%%a0 ; \
471 movl %1,%%d1 ; \
472 movl %2,%%d0 ; \
473 1: movw %%d1,%%a0@ ; \
474 subql #1,%%d0 ; \
475 jne 1b" : \
476 : \
477 "r" ((h) + (o)), "g" (val), "g" (c) : \
478 "a0","d0","d1"); \
479 } while (0);
480
481 #define bus_space_set_multi_4(t, h, o, val, c) do { \
482 (void) t; \
483 __asm volatile (" \
484 movl %0,%%a0 ; \
485 movl %1,%%d1 ; \
486 movl %2,%%d0 ; \
487 1: movl %%d1,%%a0@ ; \
488 subql #1,%%d0 ; \
489 jne 1b" : \
490 : \
491 "r" ((h) + (o)), "g" (val), "g" (c) : \
492 "a0","d0","d1"); \
493 } while (0);
494
495 /*
496 * void bus_space_set_region_N(bus_space_tag_t tag,
497 * bus_space_handle_t bsh, bus_size_t offset, uintN_t val,
498 * size_t count);
499 *
500 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
501 * by tag/handle starting at `offset'.
502 */
503
504 #define bus_space_set_region_1(t, h, o, val, c) do { \
505 (void) t; \
506 __asm volatile (" \
507 movl %0,%%a0 ; \
508 movl %1,%%d1 ; \
509 movl %2,%%d0 ; \
510 1: movb %%d1,%%a0@+ ; \
511 subql #1,%%d0 ; \
512 jne 1b" : \
513 : \
514 "r" ((h) + (o)), "g" (val), "g" (c) : \
515 "a0","d0","d1"); \
516 } while (0);
517
518 #define bus_space_set_region_2(t, h, o, val, c) do { \
519 (void) t; \
520 __asm volatile (" \
521 movl %0,%%a0 ; \
522 movl %1,%%d1 ; \
523 movl %2,%%d0 ; \
524 1: movw %%d1,%%a0@+ ; \
525 subql #1,%%d0 ; \
526 jne 1b" : \
527 : \
528 "r" ((h) + (o)), "g" (val), "g" (c) : \
529 "a0","d0","d1"); \
530 } while (0);
531
532 #define bus_space_set_region_4(t, h, o, val, c) do { \
533 (void) t; \
534 __asm volatile (" \
535 movl %0,%%a0 ; \
536 movl %1,%%d1 ; \
537 movl %2,%%d0 ; \
538 1: movl d1,%%a0@+ ; \
539 subql #1,%%d0 ; \
540 jne 1b" : \
541 : \
542 "r" ((h) + (o)), "g" (val), "g" (c) : \
543 "a0","d0","d1"); \
544 } while (0);
545
546 /*
547 * void bus_space_copy_N(bus_space_tag_t tag,
548 * bus_space_handle_t bsh1, bus_size_t off1,
549 * bus_space_handle_t bsh2, bus_size_t off2,
550 * size_t count);
551 *
552 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
553 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
554 */
555
556 #define __VIRT68K_copy_region_N(BYTES) \
557 static __inline void __CONCAT(bus_space_copy_region_,BYTES) \
558 (bus_space_tag_t, \
559 bus_space_handle_t bsh1, bus_size_t off1, \
560 bus_space_handle_t bsh2, bus_size_t off2, \
561 bus_size_t count); \
562 \
563 static __inline void \
564 __CONCAT(bus_space_copy_region_,BYTES)( \
565 bus_space_tag_t t, \
566 bus_space_handle_t h1, \
567 bus_size_t o1, \
568 bus_space_handle_t h2, \
569 bus_size_t o2, \
570 bus_size_t c) \
571 { \
572 bus_size_t o; \
573 (void) t; \
574 \
575 if ((h1 + o1) >= (h2 + o2)) { \
576 /* src after dest: copy forward */ \
577 for (o = 0; c != 0; c--, o += BYTES) \
578 __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
579 __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
580 } else { \
581 /* dest after src: copy backwards */ \
582 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
583 __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
584 __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
585 } \
586 }
587 __VIRT68K_copy_region_N(1)
588 __VIRT68K_copy_region_N(2)
589 __VIRT68K_copy_region_N(4)
590
591 #undef __VIRT68K_copy_region_N
592
593 /*
594 * Bus read/write barrier methods.
595 *
596 * void bus_space_barrier(bus_space_tag_t tag,
597 * bus_space_handle_t bsh, bus_size_t offset,
598 * bus_size_t len, int flags);
599 *
600 * Note: the 680x0 does not currently require barriers, but we must
601 * provide the flags to MI code.
602 */
603 #define bus_space_barrier(t, h, o, l, f) \
604 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
605 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
606 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
607
608 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
609
610
611 #ifdef _VIRT68K_BUS_SPACE_PRIVATE
612 extern int _bus_space_map(void *, bus_addr_t, bus_size_t,
613 int, bus_space_handle_t *);
614 extern void _bus_space_unmap(void *, bus_space_handle_t, bus_size_t);
615 extern int _bus_space_peek_1(void *, bus_space_handle_t,
616 bus_size_t, uint8_t *);
617 extern int _bus_space_peek_2(void *, bus_space_handle_t,
618 bus_size_t, uint16_t *);
619 extern int _bus_space_peek_4(void *, bus_space_handle_t,
620 bus_size_t, uint32_t *);
621 extern int _bus_space_poke_1(void *, bus_space_handle_t, bus_size_t, uint8_t);
622 extern int _bus_space_poke_2(void *, bus_space_handle_t, bus_size_t, uint16_t);
623 extern int _bus_space_poke_4(void *, bus_space_handle_t, bus_size_t, uint32_t);
624 #endif /* _VIRT68K_BUS_SPACE_PRIVATE */
625
626 #endif /* _VIRT68K_BUS_SPACE_H_ */
627