1 /* $NetBSD: clock.c,v 1.69 2024/01/19 18:18:55 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 1982, 1990, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * the Systems Programming Group of the University of Utah Computer
9 * Science Department.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * from: Utah Hdr: clock.c 1.18 91/01/21$
36 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94
37 */
38
39 /*
40 * Copyright (c) 1994 Gordon W. Ross
41 * Copyright (c) 1993 Adam Glass
42 * Copyright (c) 1988 University of Utah.
43 *
44 * This code is derived from software contributed to Berkeley by
45 * the Systems Programming Group of the University of Utah Computer
46 * Science Department.
47 *
48 * Redistribution and use in source and binary forms, with or without
49 * modification, are permitted provided that the following conditions
50 * are met:
51 * 1. Redistributions of source code must retain the above copyright
52 * notice, this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright
54 * notice, this list of conditions and the following disclaimer in the
55 * documentation and/or other materials provided with the distribution.
56 * 3. All advertising materials mentioning features or use of this software
57 * must display the following acknowledgement:
58 * This product includes software developed by the University of
59 * California, Berkeley and its contributors.
60 * 4. Neither the name of the University nor the names of its contributors
61 * may be used to endorse or promote products derived from this software
62 * without specific prior written permission.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * SUCH DAMAGE.
75 *
76 * from: Utah Hdr: clock.c 1.18 91/01/21$
77 * from: @(#)clock.c 8.2 (Berkeley) 1/12/94
78 */
79
80 /*
81 * Machine-dependent clock routines for the Intersil 7170:
82 * Original by Adam Glass; partially rewritten by Gordon Ross.
83 */
84
85 #include <sys/cdefs.h>
86 __KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.69 2024/01/19 18:18:55 thorpej Exp $");
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/time.h>
91 #include <sys/kernel.h>
92 #include <sys/device.h>
93 #include <sys/intr.h>
94
95 #include <uvm/uvm_extern.h>
96
97 #include <m68k/asm_single.h>
98
99 #include <machine/autoconf.h>
100 #include <machine/bus.h>
101 #include <machine/cpu.h>
102 #include <machine/leds.h>
103 #include <machine/vectors.h>
104
105 #include <sun3/sun3/control.h>
106 #include <sun3/sun3/interreg.h>
107 #include <sun3/sun3/machdep.h>
108
109 #include <dev/clock_subr.h>
110 #include <dev/ic/intersil7170reg.h>
111 #include <dev/ic/intersil7170var.h>
112
113 #define CLOCK_PRI 5
114 #define IREG_CLK_BITS (IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5)
115
116 void _isr_clock(void); /* in locore.s */
117 void clock_intr(struct clockframe);
118
119 static volatile void *intersil_va;
120
121 #define intersil_clock ((volatile struct intersil7170 *)intersil_va)
122
123 #define intersil_clear() (void)intersil_clock->clk_intr_reg
124
125 static int oclock_match(device_t, cfdata_t, void *);
126 static void oclock_attach(device_t, device_t, void *);
127
128 CFATTACH_DECL_NEW(oclock, sizeof(struct intersil7170_softc),
129 oclock_match, oclock_attach, NULL, NULL);
130
131 static int
oclock_match(device_t parent,cfdata_t cf,void * aux)132 oclock_match(device_t parent, cfdata_t cf, void *aux)
133 {
134 struct confargs *ca = aux;
135
136 /* This driver only supports one unit. */
137 if (intersil_va)
138 return 0;
139
140 /* Make sure there is something there... */
141 if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1)
142 return 0;
143
144 /* Default interrupt priority. */
145 if (ca->ca_intpri == -1)
146 ca->ca_intpri = CLOCK_PRI;
147
148 return 1;
149 }
150
151 static void
oclock_attach(device_t parent,device_t self,void * aux)152 oclock_attach(device_t parent, device_t self, void *aux)
153 {
154 struct intersil7170_softc *sc = device_private(self);
155 struct confargs *ca = aux;
156
157 sc->sc_dev = self;
158
159 /* Get a mapping for it. */
160 sc->sc_bst = ca->ca_bustag;
161 if (bus_space_map(sc->sc_bst, ca->ca_paddr, sizeof(struct intersil7170),
162 0, &sc->sc_bsh) != 0) {
163 aprint_error(": can't map registers\n");
164 return;
165 }
166
167 intersil_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh);
168
169 /*
170 * Set the clock to the correct interrupt rate, but
171 * do not enable the interrupt until cpu_initclocks.
172 * XXX: Actually, the interrupt_reg should be zero
173 * at this point, so the clock interrupts should not
174 * affect us, but we need to set the rate...
175 */
176 bus_space_write_1(sc->sc_bst, sc->sc_bsh, INTERSIL_ICMD,
177 INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE));
178 (void)bus_space_read_1(sc->sc_bst, sc->sc_bsh, INTERSIL_IINTR);
179
180 /* Set the clock to 100 Hz, but do not enable it yet. */
181 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
182 INTERSIL_IINTR, INTERSIL_INTER_CSECONDS);
183
184 sc->sc_year0 = 1968;
185 intersil7170_attach(sc);
186
187 aprint_normal("\n");
188
189 /*
190 * Can not hook up the ISR until cpu_initclocks()
191 * because hardclock is not ready until then.
192 * For now, the handler is _isr_autovec(), which
193 * will complain if it gets clock interrupts.
194 */
195 }
196
197 /*
198 * Set and/or clear the desired clock bits in the interrupt
199 * register. We have to be extremely careful that we do it
200 * in such a manner that we don't get ourselves lost.
201 * XXX: Watch out! It's really easy to break this!
202 */
203 void
set_clk_mode(u_char on,u_char off,int enable_clk)204 set_clk_mode(u_char on, u_char off, int enable_clk)
205 {
206 u_char interreg;
207
208 /*
209 * If we have not yet mapped the register,
210 * then we do not want to do any of this...
211 */
212 if (!interrupt_reg)
213 return;
214
215 #ifdef DIAGNOSTIC
216 /* Assertion: were are at splhigh! */
217 if ((getsr() & PSL_IPL) < PSL_IPL7)
218 panic("set_clk_mode: bad ipl");
219 #endif
220
221 /*
222 * make sure that we are only playing w/
223 * clock interrupt register bits
224 */
225 on &= IREG_CLK_BITS;
226 off &= IREG_CLK_BITS;
227
228 /* First, turn off the "master" enable bit. */
229 single_inst_bclr_b(*interrupt_reg, IREG_ALL_ENAB);
230
231 /*
232 * Save the current interrupt register clock bits,
233 * and turn off/on the requested bits in the copy.
234 */
235 interreg = *interrupt_reg & IREG_CLK_BITS;
236 interreg &= ~off;
237 interreg |= on;
238
239 /* Clear the CLK5 and CLK7 bits to clear the flip-flops. */
240 single_inst_bclr_b(*interrupt_reg, IREG_CLK_BITS);
241
242 if (intersil_va) {
243 /*
244 * Then disable clock interrupts, and read the clock's
245 * interrupt register to clear any pending signals there.
246 */
247 intersil_clock->clk_cmd_reg =
248 INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE);
249 intersil_clear();
250 }
251
252 /* Set the requested bits in the interrupt register. */
253 single_inst_bset_b(*interrupt_reg, interreg);
254
255 /* Turn the clock back on (maybe) */
256 if (intersil_va && enable_clk)
257 intersil_clock->clk_cmd_reg =
258 INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
259
260 /* Finally, turn the "master" enable back on. */
261 single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB);
262 }
263
264 /*
265 * Set up the real-time clock (enable clock interrupts).
266 * Leave stathz 0 since there is no secondary clock available.
267 * Note that clock interrupts MUST STAY DISABLED until here.
268 */
269 void
cpu_initclocks(void)270 cpu_initclocks(void)
271 {
272 int s;
273
274 s = splhigh();
275
276 /* Install isr (in locore.s) that calls clock_intr(). */
277 vec_set_entry(VECI_INTRAV0 + CLOCK_PRI, (void *)_isr_clock);
278
279 /* Now enable the clock at level 5 in the interrupt reg. */
280 set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1);
281
282 splx(s);
283 }
284
285 /*
286 * This doesn't need to do anything, as we have only one timer and
287 * profhz==stathz==hz.
288 */
289 void
setstatclockrate(int newhz)290 setstatclockrate(int newhz)
291 {
292
293 /* nothing */
294 }
295
296 /*
297 * This is called by the "custom" interrupt handler.
298 * Note that we can get ZS interrupts while this runs,
299 * and zshard may touch the interrupt_reg, so we must
300 * be careful to use the single_inst_* macros to modify
301 * the interrupt register atomically.
302 */
303 void
clock_intr(struct clockframe cf)304 clock_intr(struct clockframe cf)
305 {
306
307 intr_depth++;
308
309 /* Read the clock interrupt register. */
310 intersil_clear();
311
312 /* Pulse the clock intr. enable low. */
313 single_inst_bclr_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
314 single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
315
316 /* Read the clock intr. reg. AGAIN! */
317 intersil_clear();
318
319 m68k_count_intr(CLOCK_PRI);
320
321 { /* Entertainment! */
322 #ifdef LED_IDLE_CHECK
323 /* With this option, LEDs move only when CPU is idle. */
324 extern char _Idle[]; /* locore.s */
325 if (cf.cf_pc == (long)_Idle)
326 #endif
327 leds_intr();
328 }
329
330 /* Call common clock interrupt handler. */
331 hardclock(&cf);
332
333 intr_depth--;
334 }
335