1 /* $NetBSD: zs.c,v 1.26 2023/12/12 23:38:11 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Zilog Z8530 Dual UART driver (machine-dependent part)
34 *
35 * Runs two serial lines per chip using slave drivers.
36 * Plain tty/async lines use the zs_async slave.
37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
38 */
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.26 2023/12/12 23:38:11 andvar Exp $");
42
43 #include "opt_ddb.h"
44 #include "opt_kgdb.h"
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/conf.h>
49 #include <sys/device.h>
50 #include <sys/file.h>
51 #include <sys/ioctl.h>
52 #include <sys/kernel.h>
53 #include <sys/proc.h>
54 #include <sys/tty.h>
55 #include <sys/time.h>
56 #include <sys/syslog.h>
57 #include <sys/intr.h>
58
59 #include <machine/autoconf.h>
60 #include <machine/promlib.h>
61 #include <machine/cpu.h>
62 #include <machine/eeprom.h>
63 #include <machine/psl.h>
64 #include <machine/z8530var.h>
65
66 #include <dev/cons.h>
67 #include <dev/ic/z8530reg.h>
68 #include <dev/sun/kbd_ms_ttyvar.h>
69
70 #include <ddb/db_active.h>
71 #include <ddb/db_output.h>
72
73 #include <sun2/dev/cons.h>
74
75 #include "ioconf.h"
76 #include "kbd.h" /* NKBD */
77 #include "ms.h" /* NMS */
78
79 /*
80 * Some warts needed by z8530tty.c -
81 * The default parity REALLY needs to be the same as the PROM uses,
82 * or you can not see messages done with printf during boot-up...
83 */
84 int zs_def_cflag = (CREAD | CS8 | HUPCL);
85
86 /* ZS channel used as the console device (if any) */
87 void *zs_conschan_get, *zs_conschan_put;
88
89 static uint8_t zs_init_reg[16] = {
90 0, /* 0: CMD (reset, etc.) */
91 0, /* 1: No interrupts yet. */
92 #ifdef ZS_INIT_IVECT
93 ZS_INIT_IVECT, /* 2: IVECT */
94 #else
95 0, /* 2: IVECT */
96 #endif
97 ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
98 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
99 ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
100 0, /* 6: TXSYNC/SYNCLO */
101 0, /* 7: RXSYNC/SYNCHI */
102 0, /* 8: alias for data port */
103 #ifdef ZS_INIT_IVECT
104 ZSWR9_MASTER_IE,
105 #else
106 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR,
107 #endif
108 0, /*10: Misc. TX/RX control bits */
109 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
110 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
111 0, /*13: BAUDHI (default=9600) */
112 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
113 ZSWR15_BREAK_IE,
114 };
115
116 /* Console ops */
117 static int zscngetc(dev_t);
118 static void zscnputc(dev_t, int);
119 static void zscnpollc(dev_t, int);
120
121 struct consdev zs_consdev = {
122 NULL,
123 NULL,
124 zscngetc,
125 zscnputc,
126 zscnpollc,
127 NULL,
128 };
129
130
131 /****************************************************************
132 * Autoconfig
133 ****************************************************************/
134
135 static int zs_print(void *, const char *name);
136
137 /* Interrupt handlers. */
138 int zscheckintr(void *);
139 static int zshard(void *);
140 static void zssoft(void *);
141
142 static int zs_get_speed(struct zs_chanstate *);
143
144 /*
145 * Attach a found zs.
146 *
147 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR
148 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE?
149 */
150 void
zs_attach(struct zsc_softc * zsc,struct zsdevice * zsd,int pri)151 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri)
152 {
153 struct zsc_attach_args zsc_args;
154 struct zs_chanstate *cs;
155 int channel;
156
157 memset(&zsc_args, 0, sizeof zsc_args);
158 if (zsd == NULL) {
159 aprint_error(": configuration incomplete\n");
160 return;
161 }
162
163 #if 0
164 /* we should use ipl2si(softpri) but it isn't exported */
165 aprint_normal(" softpri %d\n", _IPL_SOFT_LEVEL3);
166 #else
167 aprint_normal("\n");
168 #endif
169
170 /*
171 * Initialize software state for each channel.
172 */
173 for (channel = 0; channel < 2; channel++) {
174 struct zschan *zc;
175 device_t child;
176
177 zsc_args.channel = channel;
178 zsc_args.hwflags = 0;
179 cs = &zsc->zsc_cs_store[channel];
180 zsc->zsc_cs[channel] = cs;
181
182 zs_lock_init(cs);
183 cs->cs_channel = channel;
184 cs->cs_private = NULL;
185 cs->cs_ops = &zsops_null;
186 cs->cs_brg_clk = PCLK / 16;
187
188 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b;
189
190 zsc_args.consdev = NULL;
191 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit,
192 zsc->zsc_node,
193 channel);
194
195 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) {
196 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV;
197 zsc_args.consdev = &zs_consdev;
198 }
199
200 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) {
201 zs_conschan_get = zc;
202 }
203 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) {
204 zs_conschan_put = zc;
205 }
206
207 /* Children need to set cn_dev, etc */
208 cs->cs_reg_csr = &zc->zc_csr;
209 cs->cs_reg_data = &zc->zc_data;
210
211 memcpy(cs->cs_creg, zs_init_reg, 16);
212 memcpy(cs->cs_preg, zs_init_reg, 16);
213
214 /* XXX: Consult PROM properties for this?! */
215 cs->cs_defspeed = zs_get_speed(cs);
216 cs->cs_defcflag = zs_def_cflag;
217
218 /* Make these correspond to cs_defcflag (-crtscts) */
219 cs->cs_rr0_dcd = ZSRR0_DCD;
220 cs->cs_rr0_cts = 0;
221 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
222 cs->cs_wr5_rts = 0;
223
224 /*
225 * Clear the master interrupt enable.
226 * The INTENA is common to both channels,
227 * so just do it on the A channel.
228 */
229 if (channel == 0) {
230 zs_write_reg(cs, 9, 0);
231 }
232
233 /*
234 * Look for a child driver for this channel.
235 * The child attach will setup the hardware.
236 */
237 if ((child = config_found(zsc->zsc_dev, (void *)&zsc_args,
238 zs_print, CFARGS_NONE)) == NULL) {
239 /* No sub-driver. Just reset it. */
240 uint8_t reset = (channel == 0) ?
241 ZSWR9_A_RESET : ZSWR9_B_RESET;
242 zs_lock_chan(cs);
243 zs_write_reg(cs, 9, reset);
244 zs_unlock_chan(cs);
245 }
246 #if (NKBD > 0) || (NMS > 0)
247 /*
248 * If this was a zstty it has a keyboard
249 * property on it we need to attach the
250 * sunkbd and sunms line disciplines.
251 */
252 if (child
253 && device_is_a(child, "zstty")) {
254 struct kbd_ms_tty_attach_args kma;
255 struct zstty_softc {
256 /*
257 * The following are the only fields
258 * we need here
259 */
260 device_t zst_dev;
261 struct tty *zst_tty;
262 struct zs_chanstate *zst_cs;
263 } *zst = device_private(child);
264 struct tty *tp;
265
266 kma.kmta_tp = tp = zst->zst_tty;
267 if (tp != NULL) {
268 kma.kmta_dev = tp->t_dev;
269 kma.kmta_consdev = zsc_args.consdev;
270
271 /* Attach 'em if we got 'em. */
272 switch(zs_peripheral_type(zsc->zsc_promunit,
273 zsc->zsc_node,
274 channel)) {
275 case ZS_PERIPHERAL_SUNKBD:
276 #if (NKBD > 0)
277 kma.kmta_name = "keyboard";
278 config_found(child, (void *)&kma, NULL,
279 CFARGS_NONE);
280 #endif
281 break;
282 case ZS_PERIPHERAL_SUNMS:
283 #if (NMS > 0)
284 kma.kmta_name = "mouse";
285 config_found(child, (void *)&kma, NULL,
286 CFARGS_NONE);
287 #endif
288 break;
289 default:
290 break;
291 }
292 }
293 }
294 #endif
295 }
296
297 /*
298 * Now safe to install interrupt handlers.
299 */
300 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, zshard, zsc);
301 if ((zsc->zsc_softintr = softint_establish(SOFTINT_SERIAL,
302 zssoft, zsc)) == NULL)
303 panic("%s: could not establish soft interrupt", __func__);
304
305 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
306 device_xname(zsc->zsc_dev), "intr");
307
308
309 /*
310 * Set the master interrupt enable and interrupt vector.
311 * (common to both channels, do it on A)
312 */
313 cs = zsc->zsc_cs[0];
314 zs_lock_chan(cs);
315 /* interrupt vector */
316 zs_write_reg(cs, 2, zs_init_reg[2]);
317 /* master interrupt control (enable) */
318 zs_write_reg(cs, 9, zs_init_reg[9]);
319 zs_unlock_chan(cs);
320
321 }
322
323 static int
zs_print(void * aux,const char * name)324 zs_print(void *aux, const char *name)
325 {
326 struct zsc_attach_args *args = aux;
327
328 if (name != NULL)
329 aprint_normal("%s: ", name);
330
331 if (args->channel != -1)
332 aprint_normal(" channel %d", args->channel);
333
334 return (UNCONF);
335 }
336
337 static int
zshard(void * arg)338 zshard(void *arg)
339 {
340 struct zsc_softc *zsc = arg;
341 int rval;
342 uint8_t rr3;
343
344 rval = 0;
345 while ((rr3 = zsc_intr_hard(zsc))) {
346 /* Count up the interrupts. */
347 rval |= rr3;
348 zsc->zsc_intrcnt.ev_count++;
349 }
350 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) ||
351 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) &&
352 zsc->zsc_softintr) {
353 softint_schedule(zsc->zsc_softintr);
354 }
355 return (rval);
356 }
357
358 int
zscheckintr(void * arg)359 zscheckintr(void *arg)
360 {
361 struct zsc_softc *zsc;
362 int unit, rval;
363
364 rval = 0;
365 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) {
366
367 zsc = device_lookup_private(&zs_cd, unit);
368 if (zsc == NULL)
369 continue;
370 rval = (zshard((void *)zsc) || rval);
371 }
372 return (rval);
373 }
374
375
376 static void
zssoft(void * arg)377 zssoft(void *arg)
378 {
379 struct zsc_softc *zsc = arg;
380 int s;
381
382 /* Make sure we call the tty layer at spltty. */
383 s = spltty();
384 (void)zsc_intr_soft(zsc);
385
386 splx(s);
387 }
388
389
390 /*
391 * Compute the current baud rate given a ZS channel.
392 */
393 static int
zs_get_speed(struct zs_chanstate * cs)394 zs_get_speed(struct zs_chanstate *cs)
395 {
396 int tconst;
397
398 tconst = zs_read_reg(cs, 12);
399 tconst |= zs_read_reg(cs, 13) << 8;
400 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
401 }
402
403 /*
404 * MD functions for setting the baud rate and control modes.
405 */
406 int
zs_set_speed(struct zs_chanstate * cs,int bps)407 zs_set_speed(struct zs_chanstate *cs, int bps)
408 {
409 int tconst, real_bps;
410
411 if (bps == 0)
412 return (0);
413
414 #ifdef DIAGNOSTIC
415 if (cs->cs_brg_clk == 0)
416 panic("zs_set_speed");
417 #endif
418
419 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
420 if (tconst < 0)
421 return (EINVAL);
422
423 /* Convert back to make sure we can do it. */
424 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
425
426 /* XXX - Allow some tolerance here? */
427 if (real_bps != bps)
428 return (EINVAL);
429
430 cs->cs_preg[12] = tconst;
431 cs->cs_preg[13] = tconst >> 8;
432
433 /* Caller will stuff the pending registers. */
434 return (0);
435 }
436
437 int
zs_set_modes(struct zs_chanstate * cs,int cflag)438 zs_set_modes(struct zs_chanstate *cs, int cflag /* bits per second */)
439 {
440
441 /*
442 * Output hardware flow control on the chip is horrendous:
443 * if carrier detect drops, the receiver is disabled, and if
444 * CTS drops, the transmitter is stopped IN MID CHARACTER!
445 * Therefore, NEVER set the HFC bit, and instead use the
446 * status interrupt to detect CTS changes.
447 */
448 zs_lock_chan(cs);
449 cs->cs_rr0_pps = 0;
450 if ((cflag & (CLOCAL | MDMBUF)) != 0) {
451 cs->cs_rr0_dcd = 0;
452 if ((cflag & MDMBUF) == 0)
453 cs->cs_rr0_pps = ZSRR0_DCD;
454 } else
455 cs->cs_rr0_dcd = ZSRR0_DCD;
456 if ((cflag & CRTSCTS) != 0) {
457 cs->cs_wr5_dtr = ZSWR5_DTR;
458 cs->cs_wr5_rts = ZSWR5_RTS;
459 cs->cs_rr0_cts = ZSRR0_CTS;
460 } else if ((cflag & CDTRCTS) != 0) {
461 cs->cs_wr5_dtr = 0;
462 cs->cs_wr5_rts = ZSWR5_DTR;
463 cs->cs_rr0_cts = ZSRR0_CTS;
464 } else if ((cflag & MDMBUF) != 0) {
465 cs->cs_wr5_dtr = 0;
466 cs->cs_wr5_rts = ZSWR5_DTR;
467 cs->cs_rr0_cts = ZSRR0_DCD;
468 } else {
469 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
470 cs->cs_wr5_rts = 0;
471 cs->cs_rr0_cts = 0;
472 }
473 zs_unlock_chan(cs);
474
475 /* Caller will stuff the pending registers. */
476 return (0);
477 }
478
479
480 /*
481 * Read or write the chip with suitable delays.
482 */
483
484 uint8_t
zs_read_reg(struct zs_chanstate * cs,uint8_t reg)485 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
486 {
487 uint8_t val;
488
489 *cs->cs_reg_csr = reg;
490 ZS_DELAY();
491 val = *cs->cs_reg_csr;
492 ZS_DELAY();
493 return (val);
494 }
495
496 void
zs_write_reg(struct zs_chanstate * cs,uint8_t reg,uint8_t val)497 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
498 {
499 *cs->cs_reg_csr = reg;
500 ZS_DELAY();
501 *cs->cs_reg_csr = val;
502 ZS_DELAY();
503 }
504
505 uint8_t
zs_read_csr(struct zs_chanstate * cs)506 zs_read_csr(struct zs_chanstate *cs)
507 {
508 uint8_t val;
509
510 val = *cs->cs_reg_csr;
511 ZS_DELAY();
512 return (val);
513 }
514
515 void
zs_write_csr(struct zs_chanstate * cs,uint8_t val)516 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
517 {
518 *cs->cs_reg_csr = val;
519 ZS_DELAY();
520 }
521
522 uint8_t
zs_read_data(struct zs_chanstate * cs)523 zs_read_data(struct zs_chanstate *cs)
524 {
525 uint8_t val;
526
527 val = *cs->cs_reg_data;
528 ZS_DELAY();
529 return (val);
530 }
531
532 void
zs_write_data(struct zs_chanstate * cs,uint8_t val)533 zs_write_data(struct zs_chanstate *cs, uint8_t val)
534 {
535 *cs->cs_reg_data = val;
536 ZS_DELAY();
537 }
538
539 /****************************************************************
540 * Console support functions (Sun specific!)
541 * Note: this code is allowed to know about the layout of
542 * the chip registers, and uses that to keep things simple.
543 * XXX - I think I like the mvme167 code better. -gwr
544 ****************************************************************/
545
546 extern void Debugger(void);
547
548 /*
549 * Handle user request to enter kernel debugger.
550 */
551 void
zs_abort(struct zs_chanstate * cs)552 zs_abort(struct zs_chanstate *cs)
553 {
554 volatile struct zschan *zc = zs_conschan_get;
555 int rr0;
556
557 /* Wait for end of break to avoid PROM abort. */
558 /* XXX - Limit the wait? */
559 do {
560 rr0 = zc->zc_csr;
561 ZS_DELAY();
562 } while (rr0 & ZSRR0_BREAK);
563
564 #if defined(KGDB)
565 zskgdb(cs);
566 #elif defined(DDB)
567 if (!db_active)
568 Debugger();
569 else
570 /* Debugger is probably hozed */
571 callrom();
572 #else
573 printf("stopping on keyboard abort\n");
574 callrom();
575 #endif
576 }
577
578 /*
579 * Polled input char.
580 */
581 int
zs_getc(void * arg)582 zs_getc(void *arg)
583 {
584 volatile struct zschan *zc = arg;
585 int s, c, rr0;
586
587 s = splhigh();
588 /* Wait for a character to arrive. */
589 do {
590 rr0 = zc->zc_csr;
591 ZS_DELAY();
592 } while ((rr0 & ZSRR0_RX_READY) == 0);
593
594 c = zc->zc_data;
595 ZS_DELAY();
596 splx(s);
597
598 /*
599 * This is used by the kd driver to read scan codes,
600 * so don't translate '\r' ==> '\n' here...
601 */
602 return (c);
603 }
604
605 /*
606 * Polled output char.
607 */
608 void
zs_putc(void * arg,int c)609 zs_putc(void *arg, int c)
610 {
611 volatile struct zschan *zc = arg;
612 int s, rr0;
613
614 s = splhigh();
615
616 /* Wait for transmitter to become ready. */
617 do {
618 rr0 = zc->zc_csr;
619 ZS_DELAY();
620 } while ((rr0 & ZSRR0_TX_READY) == 0);
621
622 /*
623 * Send the next character.
624 * Now you'd think that this could be followed by a ZS_DELAY()
625 * just like all the other chip accesses, but it turns out that
626 * the `transmit-ready' interrupt isn't de-asserted until
627 * some period of time after the register write completes
628 * (more than a couple instructions). So to avoid stray
629 * interrupts we put in the 2us delay regardless of CPU model.
630 */
631 zc->zc_data = c;
632 delay(2);
633
634 splx(s);
635 }
636
637 /*****************************************************************/
638
639 /*
640 * Polled console input putchar.
641 */
642 static int
zscngetc(dev_t dev)643 zscngetc(dev_t dev)
644 {
645 return (zs_getc(zs_conschan_get));
646 }
647
648 /*
649 * Polled console output putchar.
650 */
651 static void
zscnputc(dev_t dev,int c)652 zscnputc(dev_t dev, int c)
653 {
654 zs_putc(zs_conschan_put, c);
655 }
656
657 int swallow_zsintrs;
658
659 static void
zscnpollc(dev_t dev,int on)660 zscnpollc(dev_t dev, int on)
661 {
662 /*
663 * Need to tell zs driver to acknowledge all interrupts or we get
664 * annoying spurious interrupt messages. This is because mucking
665 * with spl() levels during polling does not prevent interrupts from
666 * being generated.
667 */
668
669 if (on) swallow_zsintrs++;
670 else swallow_zsintrs--;
671 }
672