1 /* $NetBSD: ffb.c,v 1.68 2023/12/20 05:33:58 thorpej Exp $ */
2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */
3
4 /*
5 * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Jason L. Wright
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.68 2023/12/20 05:33:58 thorpej Exp $");
37
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/device.h>
43 #include <sys/conf.h>
44 #include <sys/ioctl.h>
45 #include <sys/mman.h>
46
47 #include <sys/bus.h>
48 #include <machine/autoconf.h>
49 #include <machine/openfirm.h>
50 #include <machine/vmparam.h>
51
52 #include <dev/wscons/wsconsio.h>
53 #include <dev/sun/fbio.h>
54 #include <dev/sun/fbvar.h>
55
56 #include <dev/wsfont/wsfont.h>
57 #include <dev/wscons/wsdisplay_vconsvar.h>
58
59 #include <prop/proplib.h>
60
61 #include <dev/i2c/i2cvar.h>
62 #include <dev/i2c/i2c_bitbang.h>
63 #include <dev/i2c/ddcvar.h>
64
65 #include <sparc64/dev/ffbreg.h>
66 #include <sparc64/dev/ffbvar.h>
67
68 #include "opt_wsdisplay_compat.h"
69 #include "opt_ffb.h"
70
71 #ifndef WS_DEFAULT_BG
72 /* Sun -> background should be white */
73 #define WS_DEFAULT_BG 0xf
74 #endif
75
76 #ifdef FFB_SYNC
77 #define SYNC ffb_ras_wait(sc)
78 #else
79 #define SYNC
80 #endif
81
82 /* Debugging */
83 #if !defined FFB_DEBUG
84 #define FFB_DEBUG 0
85 #endif
86 #define DPRINTF(x) if (ffb_debug) printf x
87 /* Patchable */
88 extern int ffb_debug;
89 #if FFB_DEBUG > 0
90 int ffb_debug = 1;
91 #else
92 int ffb_debug = 0;
93 #endif
94
95 extern struct cfdriver ffb_cd;
96
97 struct wsscreen_descr ffb_stdscreen = {
98 "sunffb",
99 0, 0, /* will be filled in -- XXX shouldn't, it's global. */
100 0,
101 0, 0,
102 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE |
103 WSSCREEN_RESIZE,
104 NULL /* modecookie */
105 };
106
107 const struct wsscreen_descr *ffb_scrlist[] = {
108 &ffb_stdscreen,
109 /* XXX other formats? */
110 };
111
112 struct wsscreen_list ffb_screenlist = {
113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *),
114 ffb_scrlist
115 };
116
117 static struct vcons_screen ffb_console_screen;
118
119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *);
120 static int ffb_blank(struct ffb_softc *, u_long, u_int *);
121 paddr_t ffb_mmap(void *, void *, off_t, int);
122 void ffb_ras_fifo_wait(struct ffb_softc *, int);
123 void ffb_ras_wait(struct ffb_softc *);
124 void ffb_ras_init(struct ffb_softc *);
125 void ffb_ras_copyrows(void *, int, int, int);
126 void ffb_ras_erasecols(void *, int, int, int, long int);
127 void ffb_ras_eraserows(void *, int, int, long int);
128 void ffb_ras_fill(struct ffb_softc *);
129 void ffb_ras_invert(struct ffb_softc *);
130 static void ffb_ras_setfg(struct ffb_softc *, int32_t);
131 static void ffb_ras_setbg(struct ffb_softc *, int32_t);
132
133 void ffb_clearscreen(struct ffb_softc *);
134 void ffb_init_screen(void *, struct vcons_screen *, int,
135 long *);
136 int ffb_allocattr(void *, int, int, int, long *);
137 void ffb_putchar_mono(void *, int, int, u_int, long);
138 void ffb_putchar_aa(void *, int, int, u_int, long);
139 void ffb_cursor(void *, int, int, int);
140
141 /* frame buffer generic driver */
142 static void ffbfb_unblank(device_t);
143 dev_type_open(ffbfb_open);
144 dev_type_close(ffbfb_close);
145 dev_type_ioctl(ffbfb_ioctl);
146 dev_type_mmap(ffbfb_mmap);
147
148 static struct fbdriver ffb_fbdriver = {
149 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll,
150 ffbfb_mmap, nokqfilter
151 };
152
153 struct wsdisplay_accessops ffb_accessops = {
154 .ioctl = ffb_ioctl,
155 .mmap = ffb_mmap,
156 };
157
158 /* I2C glue */
159 static int ffb_i2c_send_start(void *, int);
160 static int ffb_i2c_send_stop(void *, int);
161 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int);
162 static int ffb_i2c_read_byte(void *, uint8_t *, int);
163 static int ffb_i2c_write_byte(void *, uint8_t, int);
164
165 /* I2C bitbang glue */
166 static void ffb_i2cbb_set_bits(void *, uint32_t);
167 static void ffb_i2cbb_set_dir(void *, uint32_t);
168 static uint32_t ffb_i2cbb_read(void *);
169
170 static const struct i2c_bitbang_ops ffb_i2cbb_ops = {
171 ffb_i2cbb_set_bits,
172 ffb_i2cbb_set_dir,
173 ffb_i2cbb_read,
174 {
175 FFB_DAC_CFG_MPDATA_SDA,
176 FFB_DAC_CFG_MPDATA_SCL,
177 0,
178 0
179 }
180 };
181
182 void ffb_attach_i2c(struct ffb_softc *);
183
184 /* Video mode setting */
185 int ffb_tgc_disable(struct ffb_softc *);
186 void ffb_get_pclk(int, uint32_t *, int *);
187 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *);
188
189
190 void
ffb_attach(device_t self)191 ffb_attach(device_t self)
192 {
193 struct ffb_softc *sc = device_private(self);
194 struct wsemuldisplaydev_attach_args waa;
195 struct rasops_info *ri;
196 long defattr;
197 const char *model, *out_dev;
198 int btype;
199 uint32_t dac;
200 int maxrow;
201 u_int blank = WSDISPLAYIO_VIDEO_ON;
202 char buf[6+1];
203 int i, try_edid;
204 prop_data_t data;
205
206 printf(":");
207
208 if (sc->sc_type == FFB_CREATOR) {
209 btype = prom_getpropint(sc->sc_node, "board_type", 0);
210 if ((btype & 7) == 3)
211 printf(" Creator3D");
212 else
213 printf(" Creator");
214 } else {
215 printf(" Elite3D");
216 btype = 0;
217 }
218
219 model = prom_getpropstring(sc->sc_node, "model");
220 if (model == NULL || strlen(model) == 0)
221 model = "unknown";
222
223 sc->sc_depth = 24;
224 sc->sc_linebytes = 8192;
225 /* We might alter these during EDID mode setting */
226 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0);
227 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0);
228
229 sc->sc_locked = 0;
230 sc->sc_mode = WSDISPLAYIO_MODE_EMUL;
231
232 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0)
233 ? strtoul(buf, NULL, 10)
234 : 34;
235
236 /* collect DAC version, as Elite3D cursor enable bit is reversed */
237 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID);
238 dac = DAC_READ(sc, FFB_DAC_VALUE);
239 sc->sc_dacrev = (dac >> 28) & 0xf;
240
241 if (sc->sc_type == FFB_AFB) {
242 sc->sc_dacrev = 10;
243 sc->sc_needredraw = 0;
244 } else {
245 /* see what kind of DAC we have */
246 int pnum = (dac & 0x0ffff000) >> 12;
247 if (pnum == 0x236e) {
248 sc->sc_needredraw = 0;
249 } else {
250 sc->sc_needredraw = 1;
251 }
252 }
253 printf(", model %s, dac %u\n", model, sc->sc_dacrev);
254 if (sc->sc_needredraw)
255 printf("%s: found old DAC, enabling redraw on unblank\n",
256 device_xname(sc->sc_dev));
257
258 /* Check if a console resolution "<device>:r<res>" is set. */
259 if (sc->sc_console) {
260 out_dev = prom_getpropstring(sc->sc_node, "output-device");
261 if (out_dev != NULL && strlen(out_dev) != 0 &&
262 strstr(out_dev, ":r") != NULL)
263 try_edid = 0;
264 else
265 try_edid = 1;
266 } else
267 try_edid = 1;
268
269 #if FFB_DEBUG > 0
270 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC);
271 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE));
272 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL);
273 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE));
274 #endif
275 ffb_attach_i2c(sc);
276
277 /* Need to set asynchronous blank during DDC write/read */
278 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL);
279 dac = DAC_READ(sc, FFB_DAC_VALUE);
280 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL);
281 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK);
282
283 /* Some monitors don't respond first time */
284 i = 0;
285 while (sc->sc_edid_data[1] == 0 && i++ < 3)
286 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN);
287
288 /* Remove asynchronous blank */
289 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL);
290 DAC_WRITE(sc, FFB_DAC_VALUE, dac);
291
292 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) {
293 sort_modes(sc->sc_edid_info.edid_modes,
294 &sc->sc_edid_info.edid_preferred_mode,
295 sc->sc_edid_info.edid_nmodes);
296 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev)));
297 for (i = 0; i < EDID_DATA_LEN; i++) {
298 if (i && !(i % 32))
299 DPRINTF(("\n "));
300 if (i && !(i % 4))
301 DPRINTF((" "));
302 DPRINTF(("%02x", sc->sc_edid_data[i]));
303 }
304 DPRINTF(("\n"));
305 if (ffb_debug)
306 edid_print(&sc->sc_edid_info);
307
308 data = prop_data_create_copy(sc->sc_edid_data, EDID_DATA_LEN);
309 prop_dictionary_set(device_properties(self), "EDID", data);
310 prop_object_release(data);
311
312 if (try_edid)
313 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) {
314 if (ffb_set_vmode(sc,
315 &(sc->sc_edid_info.edid_modes[i]), btype,
316 &(sc->sc_width), &(sc->sc_height)))
317 break;
318 }
319 } else {
320 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev)));
321 }
322
323 ffb_ras_init(sc);
324
325 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank);
326
327 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags &
328 FFB_CFFLAG_NOACCEL) == 0);
329
330 wsfont_init();
331
332 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops);
333 sc->vd.init_screen = ffb_init_screen;
334 ri = &ffb_console_screen.scr_ri;
335
336 /* we mess with ffb_console_screen only once */
337 if (sc->sc_console) {
338 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC;
339 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr);
340 SCREEN_VISIBLE((&ffb_console_screen));
341 /*
342 * XXX we shouldn't use a global variable for the console
343 * screen
344 */
345 sc->vd.active = &ffb_console_screen;
346 } else {
347 if (ffb_console_screen.scr_ri.ri_rows == 0) {
348 /* do some minimal setup to avoid weirdnesses later */
349 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr);
350 } else
351 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr);
352 }
353
354 ffb_stdscreen.nrows = ri->ri_rows;
355 ffb_stdscreen.ncols = ri->ri_cols;
356 ffb_stdscreen.textops = &ri->ri_ops;
357
358 sc->sc_fb.fb_driver = &ffb_fbdriver;
359 sc->sc_fb.fb_type.fb_cmsize = 0;
360 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes;
361 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR;
362 sc->sc_fb.fb_type.fb_width = sc->sc_width;
363 sc->sc_fb.fb_type.fb_depth = sc->sc_depth;
364 sc->sc_fb.fb_type.fb_height = sc->sc_height;
365 sc->sc_fb.fb_device = sc->sc_dev;
366 fb_attach(&sc->sc_fb, sc->sc_console);
367
368 ffb_clearscreen(sc);
369
370 if (sc->sc_console) {
371 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr);
372 vcons_replay_msgbuf(&ffb_console_screen);
373 }
374
375 waa.console = sc->sc_console;
376 waa.scrdata = &ffb_screenlist;
377 waa.accessops = &ffb_accessops;
378 waa.accesscookie = &sc->vd;
379 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint, CFARGS_NONE);
380 }
381
382 void
ffb_attach_i2c(struct ffb_softc * sc)383 ffb_attach_i2c(struct ffb_softc *sc)
384 {
385
386 /* Fill in the i2c tag */
387 iic_tag_init(&sc->sc_i2c);
388 sc->sc_i2c.ic_cookie = sc;
389 sc->sc_i2c.ic_send_start = ffb_i2c_send_start;
390 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop;
391 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer;
392 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte;
393 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte;
394 }
395
396 int
ffb_ioctl(void * v,void * vs,u_long cmd,void * data,int flags,struct lwp * l)397 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l)
398 {
399 struct vcons_data *vd = v;
400 struct ffb_softc *sc = vd->cookie;
401 struct wsdisplay_fbinfo *wdf;
402 struct vcons_screen *ms = vd->active;
403
404 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n",
405 device_xname(sc->sc_dev),
406 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "",
407 (char)IOCGROUP(cmd), cmd & 0xff));
408
409 switch (cmd) {
410 case FBIOGTYPE:
411 *(struct fbtype *)data = sc->sc_fb.fb_type;
412 break;
413 case FBIOGATTR:
414 #define fba ((struct fbgattr *)data)
415 fba->real_type = sc->sc_fb.fb_type.fb_type;
416 fba->owner = 0; /* XXX ??? */
417 fba->fbtype = sc->sc_fb.fb_type;
418 fba->sattr.flags = 0;
419 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type;
420 fba->sattr.dev_specific[0] = -1;
421 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type;
422 fba->emu_types[1] = -1;
423 #undef fba
424 break;
425
426 case FBIOGETCMAP:
427 case FBIOPUTCMAP:
428 return EIO;
429
430 case FBIOGVIDEO:
431 case FBIOSVIDEO:
432 return ffb_blank(sc, cmd == FBIOGVIDEO?
433 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO,
434 (u_int *)data);
435 break;
436 case FBIOGCURSOR:
437 case FBIOSCURSOR:
438 /* the console driver is not using the hardware cursor */
439 break;
440 case FBIOGCURPOS:
441 printf("%s: FBIOGCURPOS not implemented\n",
442 device_xname(sc->sc_dev));
443 return EIO;
444 case FBIOSCURPOS:
445 printf("%s: FBIOSCURPOS not implemented\n",
446 device_xname(sc->sc_dev));
447 return EIO;
448 case FBIOGCURMAX:
449 printf("%s: FBIOGCURMAX not implemented\n",
450 device_xname(sc->sc_dev));
451 return EIO;
452
453 case WSDISPLAYIO_GTYPE:
454 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB;
455 break;
456 case WSDISPLAYIO_SMODE:
457 {
458 if (sc->sc_mode != *(u_int *)data) {
459 sc->sc_mode = *(u_int *)data;
460 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) &&
461 (sc->sc_locked == 0)) {
462 ffb_ras_init(sc);
463 vcons_redraw_screen(ms);
464 } else {
465 ffb_ras_wait(sc);
466 }
467 }
468 }
469 break;
470 case WSDISPLAYIO_GINFO:
471 wdf = (void *)data;
472 wdf->height = sc->sc_height;
473 wdf->width = sc->sc_width;
474 wdf->depth = 32;
475 wdf->cmsize = 256; /* XXX */
476 break;
477 #ifdef WSDISPLAYIO_LINEBYTES
478 case WSDISPLAYIO_LINEBYTES:
479 *(u_int *)data = sc->sc_linebytes;
480 break;
481 #endif
482 case WSDISPLAYIO_GETCMAP:
483 break;/* XXX */
484
485 case WSDISPLAYIO_PUTCMAP:
486 break;/* XXX */
487
488 case WSDISPLAYIO_SVIDEO:
489 case WSDISPLAYIO_GVIDEO:
490 return(ffb_blank(sc, cmd, (u_int *)data));
491 break;
492
493 case WSDISPLAYIO_GCURPOS:
494 case WSDISPLAYIO_SCURPOS:
495 case WSDISPLAYIO_GCURMAX:
496 case WSDISPLAYIO_GCURSOR:
497 case WSDISPLAYIO_SCURSOR:
498 return EIO; /* not supported yet */
499 break;
500
501 case WSDISPLAYIO_GET_EDID: {
502 struct wsdisplayio_edid_info *d = data;
503 return wsdisplayio_get_edid(sc->sc_dev, d);
504 }
505
506 case WSDISPLAYIO_GET_FBINFO: {
507 struct wsdisplayio_fbinfo *fbi = data;
508 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi);
509 }
510
511 default:
512 return EPASSTHROUGH;
513 }
514
515 return (0);
516 }
517
518 /* blank/unblank the screen */
519 static int
ffb_blank(struct ffb_softc * sc,u_long cmd,u_int * data)520 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data)
521 {
522 struct vcons_screen *ms = sc->vd.active;
523 u_int val;
524
525 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC);
526 val = DAC_READ(sc, FFB_DAC_VALUE);
527
528 switch (cmd) {
529 case WSDISPLAYIO_GVIDEO:
530 *data = val & 1;
531 return(0);
532 break;
533 case WSDISPLAYIO_SVIDEO:
534 if (*data == WSDISPLAYIO_VIDEO_OFF)
535 val &= ~1;
536 else if (*data == WSDISPLAYIO_VIDEO_ON)
537 val |= 1;
538 else
539 return(EINVAL);
540 break;
541 default:
542 return(EINVAL);
543 }
544
545 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC);
546 DAC_WRITE(sc, FFB_DAC_VALUE, val);
547
548 if ((val & 1) && sc->sc_needredraw) {
549 if (ms != NULL) {
550 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) &&
551 (sc->sc_locked == 0)) {
552 ffb_ras_init(sc);
553 vcons_redraw_screen(ms);
554 }
555 }
556 }
557
558 return(0);
559 }
560
561 paddr_t
ffb_mmap(void * vsc,void * vs,off_t off,int prot)562 ffb_mmap(void *vsc, void *vs, off_t off, int prot)
563 {
564 struct vcons_data *vd = vsc;
565 struct ffb_softc *sc = vd->cookie;
566 int i;
567
568 switch (sc->sc_mode) {
569 case WSDISPLAYIO_MODE_MAPPED:
570 for (i = 0; i < sc->sc_nreg; i++) {
571 /* Before this set? */
572 if (off < sc->sc_addrs[i])
573 continue;
574 /* After this set? */
575 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i]))
576 continue;
577
578 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i],
579 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR));
580 }
581 break;
582 #ifdef WSDISPLAYIO_MODE_DUMBFB
583 case WSDISPLAYIO_MODE_DUMBFB:
584 if (sc->sc_nreg < FFB_REG_DFB24)
585 break;
586 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24])
587 return (bus_space_mmap(sc->sc_bt,
588 sc->sc_addrs[FFB_REG_DFB24], off, prot,
589 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE));
590 break;
591 #endif
592 }
593 return (-1);
594 }
595
596 void
ffb_ras_fifo_wait(struct ffb_softc * sc,int n)597 ffb_ras_fifo_wait(struct ffb_softc *sc, int n)
598 {
599 int32_t cache = sc->sc_fifo_cache;
600
601 if (cache < n) {
602 do {
603 cache = FBC_READ(sc, FFB_FBC_UCSR);
604 cache = (cache & FBC_UCSR_FIFO_MASK) - 8;
605 } while (cache < n);
606 }
607 sc->sc_fifo_cache = cache - n;
608 }
609
610 void
ffb_ras_wait(struct ffb_softc * sc)611 ffb_ras_wait(struct ffb_softc *sc)
612 {
613 uint32_t ucsr, r;
614
615 while (1) {
616 ucsr = FBC_READ(sc, FFB_FBC_UCSR);
617 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0)
618 break;
619 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL);
620 if (r != 0)
621 FBC_WRITE(sc, FFB_FBC_UCSR, r);
622 }
623 }
624
625 void
ffb_ras_init(struct ffb_softc * sc)626 ffb_ras_init(struct ffb_softc *sc)
627 {
628 uint32_t fbc;
629
630 if (sc->sc_width > 1280) {
631 DPRINTF(("ffb_ras_init: high resolution.\n"));
632 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON |
633 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON;
634 } else {
635 DPRINTF(("ffb_ras_init: standard resolution.\n"));
636 fbc = FFB_FBC_XE_OFF;
637 }
638 ffb_ras_fifo_wait(sc, 7);
639 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID)));
640 FBC_WRITE(sc, FFB_FBC_WID, 0x0);
641 FBC_WRITE(sc, FFB_FBC_PPC,
642 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS |
643 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST |
644 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID);
645
646 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH |
647 FFB_FBC_RGBE_MASK;
648 DPRINTF(("%s: fbc is %08x\n", __func__, fbc));
649 FBC_WRITE(sc, FFB_FBC_FBC, fbc);
650 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW);
651 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE);
652 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff);
653 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000);
654 ffb_ras_fifo_wait(sc, 5);
655 sc->sc_fg_cache = 0;
656 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache);
657 sc->sc_bg_cache = 0;
658 FBC_WRITE(sc, FFB_FBC_BG, sc->sc_bg_cache);
659 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE |
660 FFB_BLENDC_DF_ONE_M_A |
661 FFB_BLENDC_SF_A);
662 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0);
663 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0);
664 ffb_ras_wait(sc);
665 }
666
667 void
ffb_ras_eraserows(void * cookie,int row,int n,long attr)668 ffb_ras_eraserows(void *cookie, int row, int n, long attr)
669 {
670 struct rasops_info *ri = cookie;
671 struct vcons_screen *scr = ri->ri_hw;
672 struct ffb_softc *sc = scr->scr_cookie;
673
674 if (row < 0) {
675 n += row;
676 row = 0;
677 }
678 if (row + n > ri->ri_rows)
679 n = ri->ri_rows - row;
680 if (n <= 0)
681 return;
682
683 ffb_ras_fill(sc);
684 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]);
685 ffb_ras_fifo_wait(sc, 4);
686 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) {
687 FBC_WRITE(sc, FFB_FBC_BY, 0);
688 FBC_WRITE(sc, FFB_FBC_BX, 0);
689 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height);
690 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width);
691 ri->ri_flg &= ~RI_CURSOR;
692 } else {
693 row *= ri->ri_font->fontheight;
694 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row);
695 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin);
696 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight);
697 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth);
698 }
699 SYNC;
700 }
701
702 void
ffb_ras_erasecols(void * cookie,int row,int col,int n,long attr)703 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr)
704 {
705 struct rasops_info *ri = cookie;
706 struct vcons_screen *scr = ri->ri_hw;
707 struct ffb_softc *sc = scr->scr_cookie;
708
709 if ((row < 0) || (row >= ri->ri_rows))
710 return;
711 if (col < 0) {
712 n += col;
713 col = 0;
714 }
715 if (col + n > ri->ri_cols)
716 n = ri->ri_cols - col;
717 if (n <= 0)
718 return;
719
720 n *= ri->ri_font->fontwidth;
721 col *= ri->ri_font->fontwidth;
722 row *= ri->ri_font->fontheight;
723
724 ffb_ras_fill(sc);
725 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]);
726 ffb_ras_fifo_wait(sc, 4);
727 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row);
728 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col);
729 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight);
730 FBC_WRITE(sc, FFB_FBC_BW, n);
731 SYNC;
732 }
733
734 void
ffb_ras_fill(struct ffb_softc * sc)735 ffb_ras_fill(struct ffb_softc *sc)
736 {
737 ffb_ras_fifo_wait(sc, 3);
738 FBC_WRITE(sc, FFB_FBC_PPC,
739 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS |
740 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST |
741 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID);
742 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW);
743 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE);
744 SYNC;
745 }
746
747 void
ffb_ras_invert(struct ffb_softc * sc)748 ffb_ras_invert(struct ffb_softc *sc)
749 {
750 ffb_ras_fifo_wait(sc, 3);
751 FBC_WRITE(sc, FFB_FBC_PPC,
752 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS |
753 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST |
754 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID);
755 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT);
756 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE);
757 SYNC;
758 }
759
760 void
ffb_ras_copyrows(void * cookie,int src,int dst,int n)761 ffb_ras_copyrows(void *cookie, int src, int dst, int n)
762 {
763 struct rasops_info *ri = cookie;
764 struct vcons_screen *scr = ri->ri_hw;
765 struct ffb_softc *sc = scr->scr_cookie;
766
767 if (dst == src)
768 return;
769 if (src < 0) {
770 n += src;
771 src = 0;
772 }
773 if ((src + n) > ri->ri_rows)
774 n = ri->ri_rows - src;
775 if (dst < 0) {
776 n += dst;
777 dst = 0;
778 }
779 if ((dst + n) > ri->ri_rows)
780 n = ri->ri_rows - dst;
781 if (n <= 0)
782 return;
783 n *= ri->ri_font->fontheight;
784 src *= ri->ri_font->fontheight;
785 dst *= ri->ri_font->fontheight;
786
787 ffb_ras_fifo_wait(sc, 9);
788 FBC_WRITE(sc, FFB_FBC_PPC,
789 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS |
790 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST |
791 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID);
792 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8));
793 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL);
794 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src);
795 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin);
796 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst);
797 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin);
798 FBC_WRITE(sc, FFB_FBC_BH, n);
799 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth);
800 SYNC;
801 }
802
803 static void
ffb_ras_setfg(struct ffb_softc * sc,int32_t fg)804 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg)
805 {
806 ffb_ras_fifo_wait(sc, 1);
807 if (fg == sc->sc_fg_cache)
808 return;
809 sc->sc_fg_cache = fg;
810 FBC_WRITE(sc, FFB_FBC_FG, fg);
811 SYNC;
812 }
813
814 static void
ffb_ras_setbg(struct ffb_softc * sc,int32_t bg)815 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg)
816 {
817 ffb_ras_fifo_wait(sc, 1);
818 if (bg == sc->sc_bg_cache)
819 return;
820 sc->sc_bg_cache = bg;
821 FBC_WRITE(sc, FFB_FBC_BG, bg);
822 SYNC;
823 }
824
825 /* frame buffer generic driver support functions */
826 static void
ffbfb_unblank(device_t dev)827 ffbfb_unblank(device_t dev)
828 {
829 struct ffb_softc *sc = device_private(dev);
830 struct vcons_screen *ms = sc->vd.active;
831 u_int on = 1;
832 int redraw = 0;
833
834 ffb_ras_init(sc);
835 if (sc->sc_locked) {
836 sc->sc_locked = 0;
837 redraw = 1;
838 }
839
840 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on);
841 #if 0
842 if ((sc->vd.active != &ffb_console_screen) &&
843 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) {
844 /*
845 * force-switch to the console screen.
846 * Caveat: the higher layer will think we're still on the
847 * other screen
848 */
849
850 SCREEN_INVISIBLE(sc->vd.active);
851 sc->vd.active = &ffb_console_screen;
852 SCREEN_VISIBLE(sc->vd.active);
853 ms = sc->vd.active;
854 redraw = 1;
855 }
856 #endif
857 if (redraw) {
858 vcons_redraw_screen(ms);
859 }
860 }
861
862 int
ffbfb_open(dev_t dev,int flags,int mode,struct lwp * l)863 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l)
864 {
865 struct ffb_softc *sc;
866
867 sc = device_lookup_private(&ffb_cd, minor(dev));
868 if (sc == NULL)
869 return ENXIO;
870
871 sc->sc_locked = 1;
872 return 0;
873 }
874
875 int
ffbfb_close(dev_t dev,int flags,int mode,struct lwp * l)876 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l)
877 {
878 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev));
879 struct vcons_screen *ms = sc->vd.active;
880
881 sc->sc_locked = 0;
882 if (ms != NULL) {
883 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) &&
884 (sc->sc_locked == 0)) {
885 ffb_ras_init(sc);
886 vcons_redraw_screen(ms);
887 }
888 }
889 return 0;
890 }
891
892 int
ffbfb_ioctl(dev_t dev,u_long cmd,void * data,int flags,struct lwp * l)893 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
894 {
895 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev));
896
897 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l);
898 }
899
900 paddr_t
ffbfb_mmap(dev_t dev,off_t off,int prot)901 ffbfb_mmap(dev_t dev, off_t off, int prot)
902 {
903 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev));
904 uint64_t size;
905 int i, reg;
906 off_t o;
907
908 /*
909 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h),
910 * which we map to an index into the "reg" property, and use
911 * our copy of the firmware data as arguments for the real
912 * mapping.
913 */
914 static struct { unsigned long voff; int reg; long flags; } map[] = {
915 { 0x00000000, FFB_REG_SFB8R, BUS_SPACE_MAP_PREFETCHABLE },
916 { 0x00400000, FFB_REG_SFB8G, BUS_SPACE_MAP_PREFETCHABLE },
917 { 0x00800000, FFB_REG_SFB8B, BUS_SPACE_MAP_PREFETCHABLE },
918 { 0x00c00000, FFB_REG_SFB8X, BUS_SPACE_MAP_PREFETCHABLE },
919 { 0x01000000, FFB_REG_SFB32, BUS_SPACE_MAP_PREFETCHABLE },
920 { 0x02000000, FFB_REG_SFB64, BUS_SPACE_MAP_PREFETCHABLE },
921 { 0x04000000, FFB_REG_FBC, 0 },
922 { 0x04004000, FFB_REG_DFB8R, BUS_SPACE_MAP_PREFETCHABLE },
923 { 0x04404000, FFB_REG_DFB8G, BUS_SPACE_MAP_PREFETCHABLE },
924 { 0x04804000, FFB_REG_DFB8B, BUS_SPACE_MAP_PREFETCHABLE },
925 { 0x04c04000, FFB_REG_DFB8X, BUS_SPACE_MAP_PREFETCHABLE },
926 { 0x05004000, FFB_REG_DFB24, BUS_SPACE_MAP_PREFETCHABLE },
927 { 0x06004000, FFB_REG_DFB32, BUS_SPACE_MAP_PREFETCHABLE },
928 { 0x07004000, FFB_REG_DFB422A, BUS_SPACE_MAP_PREFETCHABLE },
929 { 0x0bc06000, FFB_REG_DAC, 0 },
930 { 0x0bc08000, FFB_REG_PROM, 0 },
931 { 0x0bc18000, 0, 0 }
932 };
933
934 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */
935 if (off == 0x0bc18000)
936 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM],
937 0x00200000, prot, BUS_SPACE_MAP_LINEAR);
938
939 /*
940 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should
941 * probably mmap them only on afb boards
942 */
943 if ((off >= 0x0bc04000) && (off < 0x0bc06000))
944 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM],
945 0x00610000 + (off - 0x0bc04000), prot,
946 BUS_SPACE_MAP_LINEAR);
947
948 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0]))
949
950 /* the map is ordered by voff */
951 for (i = 0; i < NELEMS(map)-1; i++) {
952 reg = map[i].reg;
953 /* the number of entries in reg seems to vary */
954 if (reg < sc->sc_nreg) {
955 size = uimin((map[i + 1].voff - map[i].voff),
956 sc->sc_sizes[reg]);
957 if ((off >= map[i].voff) &&
958 (off < (map[i].voff + size))) {
959 o = off - map[i].voff;
960 return bus_space_mmap(sc->sc_bt,
961 sc->sc_addrs[reg], o, prot,
962 BUS_SPACE_MAP_LINEAR | map[i].flags);
963 }
964 }
965 }
966
967 return -1;
968 }
969
970 void
ffb_clearscreen(struct ffb_softc * sc)971 ffb_clearscreen(struct ffb_softc *sc)
972 {
973 struct rasops_info *ri = &ffb_console_screen.scr_ri;
974 ffb_ras_fill(sc);
975 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]);
976 ffb_ras_fifo_wait(sc, 4);
977 FBC_WRITE(sc, FFB_FBC_BY, 0);
978 FBC_WRITE(sc, FFB_FBC_BX, 0);
979 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height);
980 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width);
981 }
982
983 void
ffb_cursor(void * cookie,int on,int row,int col)984 ffb_cursor(void *cookie, int on, int row, int col)
985 {
986 struct rasops_info *ri = cookie;
987 struct vcons_screen *scr;
988 struct ffb_softc *sc;
989 int x, y, wi, he;
990
991 if (cookie != NULL) {
992 scr = ri->ri_hw;
993 sc = scr->scr_cookie;
994
995 wi = ri->ri_font->fontwidth;
996 he = ri->ri_font->fontheight;
997
998 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) {
999
1000 if (ri->ri_flg & RI_CURSOR) {
1001
1002 /* remove cursor */
1003 x = ri->ri_ccol * wi + ri->ri_xorigin;
1004 y = ri->ri_crow * he + ri->ri_yorigin;
1005
1006 ffb_ras_invert(sc);
1007 ffb_ras_fifo_wait(sc, 4);
1008 FBC_WRITE(sc, FFB_FBC_BY, y);
1009 FBC_WRITE(sc, FFB_FBC_BX, x);
1010 FBC_WRITE(sc, FFB_FBC_BH, he);
1011 FBC_WRITE(sc, FFB_FBC_BW, wi);
1012
1013 ri->ri_flg &= ~RI_CURSOR;
1014 }
1015 ri->ri_crow = row;
1016 ri->ri_ccol = col;
1017 if (on)
1018 {
1019 x = ri->ri_ccol * wi + ri->ri_xorigin;
1020 y = ri->ri_crow * he + ri->ri_yorigin;
1021
1022 ffb_ras_invert(sc);
1023 ffb_ras_fifo_wait(sc, 4);
1024 FBC_WRITE(sc, FFB_FBC_BY, y);
1025 FBC_WRITE(sc, FFB_FBC_BX, x);
1026 FBC_WRITE(sc, FFB_FBC_BH, he);
1027 FBC_WRITE(sc, FFB_FBC_BW, wi);
1028
1029 ri->ri_flg |= RI_CURSOR;
1030 }
1031 } else {
1032 ri->ri_crow = row;
1033 ri->ri_ccol = col;
1034 ri->ri_flg &= ~RI_CURSOR;
1035 }
1036 }
1037 }
1038
1039 /* mono bitmap font */
1040 void
ffb_putchar_mono(void * cookie,int row,int col,u_int c,long attr)1041 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr)
1042 {
1043 struct rasops_info *ri = cookie;
1044 struct vcons_screen *scr = ri->ri_hw;
1045 struct wsdisplay_font *font = PICK_FONT(ri, c);
1046 struct ffb_softc *sc = scr->scr_cookie;
1047 void *data;
1048 uint32_t fg, bg;
1049 int i;
1050 int x, y, wi, he;
1051
1052 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL)
1053 return;
1054
1055 wi = font->fontwidth;
1056 he = font->fontheight;
1057
1058 if (!CHAR_IN_FONT(c, font))
1059 return;
1060
1061 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
1062 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
1063 x = ri->ri_xorigin + col * wi;
1064 y = ri->ri_yorigin + row * he;
1065
1066 data = WSFONT_GLYPH(c, font);
1067
1068 ffb_ras_setbg(sc, bg);
1069 ffb_ras_setfg(sc, fg);
1070 ffb_ras_fifo_wait(sc, 4);
1071 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW);
1072 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x);
1073 FBC_WRITE(sc, FFB_FBC_FONTW, wi);
1074 FBC_WRITE(sc, FFB_FBC_PPC,
1075 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS |
1076 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST |
1077 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID);
1078
1079 switch (font->stride) {
1080 case 1: {
1081 uint8_t *data8 = data;
1082 uint32_t reg;
1083 if (attr & WSATTR_UNDERLINE) {
1084 for (i = 0; i < he - 2; i++) {
1085 reg = *data8;
1086 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24);
1087 data8++;
1088 }
1089 FBC_WRITE(sc, FFB_FBC_FONT, 0xff000000);
1090 data8++;
1091 reg = *data8;
1092 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24);
1093 } else {
1094 for (i = 0; i < he; i++) {
1095 reg = *data8;
1096 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24);
1097 data8++;
1098 }
1099 }
1100 break;
1101 }
1102 case 2: {
1103 uint16_t *data16 = data;
1104 uint32_t reg;
1105 if (attr & WSATTR_UNDERLINE) {
1106 for (i = 0; i < he - 2; i++) {
1107 reg = *data16;
1108 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16);
1109 data16++;
1110 }
1111 FBC_WRITE(sc, FFB_FBC_FONT, 0xffff0000);
1112 data16++;
1113 reg = *data16;
1114 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16);
1115 } else {
1116 for (i = 0; i < he; i++) {
1117 reg = *data16;
1118 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16);
1119 data16++;
1120 }
1121 }
1122 break;
1123 }
1124 }
1125 }
1126
1127 /* alpha font */
1128 void
ffb_putchar_aa(void * cookie,int row,int col,u_int c,long attr)1129 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr)
1130 {
1131 struct rasops_info *ri = cookie;
1132 struct vcons_screen *scr = ri->ri_hw;
1133 struct wsdisplay_font *font = PICK_FONT(ri, c);
1134 struct ffb_softc *sc = scr->scr_cookie;
1135 volatile uint32_t *dest, *ddest;
1136 uint8_t *data8;
1137 uint32_t fg, bg;
1138 int i;
1139 int x, y, wi, he;
1140 uint32_t alpha = 0x80;
1141 int j;
1142
1143 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL)
1144 return;
1145
1146 wi = font->fontwidth;
1147 he = font->fontheight;
1148
1149 if (!CHAR_IN_FONT(c, font))
1150 return;
1151
1152 bg = ri->ri_devcmap[(attr >> 16) & 0xf];
1153 fg = ri->ri_devcmap[(attr >> 24) & 0xf];
1154 x = ri->ri_xorigin + col * wi;
1155 y = ri->ri_yorigin + row * he;
1156
1157 data8 = WSFONT_GLYPH(c, font);
1158
1159 /* first we erase the background */
1160 ffb_ras_fill(sc);
1161 ffb_ras_setfg(sc, bg);
1162 ffb_ras_fifo_wait(sc, 4);
1163 FBC_WRITE(sc, FFB_FBC_BY, y);
1164 FBC_WRITE(sc, FFB_FBC_BX, x);
1165 FBC_WRITE(sc, FFB_FBC_BH, he);
1166 FBC_WRITE(sc, FFB_FBC_BW, wi);
1167
1168 /* if we draw a space we're done */
1169 if (c == ' ') goto out;
1170
1171 /* now enable alpha blending */
1172 ffb_ras_setfg(sc, fg);
1173 ffb_ras_fifo_wait(sc, 2);
1174 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW);
1175
1176 FBC_WRITE(sc, FFB_FBC_PPC,
1177 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS |
1178 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST |
1179 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR);
1180 /*
1181 * we have to wait for both the rectangle drawing op above and the
1182 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture
1183 */
1184 ffb_ras_wait(sc);
1185
1186 /* ... and draw the character */
1187 dest = sc->sc_sfb32 + (y << 11) + x;
1188 for (i = 0; i < he; i++) {
1189 ddest = dest;
1190 for (j = 0; j < wi; j++) {
1191 alpha = *data8;
1192 /*
1193 * We set the colour source to constant above so we only
1194 * have to write the alpha channel here and the colour
1195 * comes from the FG register. It would be nice if we
1196 * could just use the SFB8X aperture and memcpy() the
1197 * alpha map line by line but for some strange reason
1198 * that will take colour info from the framebuffer even
1199 * if we set the FBC_PPC_CS_CONST bit above.
1200 */
1201 *ddest = alpha << 24;
1202 data8++;
1203 ddest++;
1204 }
1205 dest += 2048;
1206 }
1207 out:
1208 /* check if we need to draw an underline */
1209 if (attr & WSATTR_UNDERLINE) {
1210 dest = sc->sc_sfb32 + ((y + he - 2) << 11) + x;
1211 for (i = 0; i < wi; i++) {
1212 *dest = 0xa0000000;
1213 dest++;
1214 }
1215 }
1216 }
1217
1218 int
ffb_allocattr(void * cookie,int fg,int bg,int flags,long * attrp)1219 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp)
1220 {
1221 if ((fg == 0) && (bg == 0))
1222 {
1223 fg = WS_DEFAULT_FG;
1224 bg = WS_DEFAULT_BG;
1225 }
1226 if (flags & WSATTR_REVERSE) {
1227 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16;
1228 } else
1229 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16;
1230 if (flags & WSATTR_UNDERLINE)
1231 *attrp |= WSATTR_UNDERLINE;
1232 return 0;
1233 }
1234
1235 void
ffb_init_screen(void * cookie,struct vcons_screen * scr,int existing,long * defattr)1236 ffb_init_screen(void *cookie, struct vcons_screen *scr,
1237 int existing, long *defattr)
1238 {
1239 struct ffb_softc *sc = cookie;
1240 struct rasops_info *ri = &scr->scr_ri;
1241
1242 ri->ri_depth = 32;
1243 ri->ri_width = sc->sc_width;
1244 ri->ri_height = sc->sc_height;
1245 ri->ri_stride = sc->sc_linebytes;
1246 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA | RI_PREFER_ALPHA;
1247
1248 /*
1249 * we can't accelerate copycols() so instead of falling back to
1250 * software use vcons' putchar() based implementation
1251 */
1252 scr->scr_flags |= VCONS_NO_COPYCOLS | VCONS_LOADFONT;
1253
1254 #ifdef VCONS_DRAW_INTR
1255 scr->scr_flags |= VCONS_DONT_READ;
1256 #endif
1257 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits));
1258
1259 /* explicitly request BGR in case the default changes */
1260 ri->ri_rnum = 8;
1261 ri->ri_gnum = 8;
1262 ri->ri_bnum = 8;
1263 ri->ri_rpos = 0;
1264 ri->ri_gpos = 8;
1265 ri->ri_bpos = 16;
1266
1267 rasops_init(ri, 0, 0);
1268 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight,
1269 sc->sc_width / ri->ri_font->fontwidth);
1270 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE |
1271 WSSCREEN_REVERSE | WSSCREEN_RESIZE;
1272
1273 /* enable acceleration */
1274 ri->ri_ops.copyrows = ffb_ras_copyrows;
1275 ri->ri_ops.eraserows = ffb_ras_eraserows;
1276 ri->ri_ops.erasecols = ffb_ras_erasecols;
1277 ri->ri_ops.cursor = ffb_cursor;
1278 ri->ri_ops.allocattr = ffb_allocattr;
1279 if (FONT_IS_ALPHA(ri->ri_font)) {
1280 ri->ri_ops.putchar = ffb_putchar_aa;
1281 } else
1282 ri->ri_ops.putchar = ffb_putchar_mono;
1283 }
1284
1285 /* I2C bitbanging */
ffb_i2cbb_set_bits(void * cookie,uint32_t bits)1286 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits)
1287 {
1288 struct ffb_softc *sc = cookie;
1289
1290 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA);
1291 DAC_WRITE(sc, FFB_DAC_VALUE, bits);
1292 }
1293
ffb_i2cbb_set_dir(void * cookie,uint32_t dir)1294 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir)
1295 {
1296 /* Nothing to do */
1297 }
1298
ffb_i2cbb_read(void * cookie)1299 static uint32_t ffb_i2cbb_read(void *cookie)
1300 {
1301 struct ffb_softc *sc = cookie;
1302 uint32_t bits;
1303
1304 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE);
1305 bits = DAC_READ(sc, FFB_DAC_VALUE);
1306
1307 return bits;
1308 }
1309
1310 /* higher level I2C stuff */
1311 static int
ffb_i2c_send_start(void * cookie,int flags)1312 ffb_i2c_send_start(void *cookie, int flags)
1313 {
1314 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops));
1315 }
1316
1317 static int
ffb_i2c_send_stop(void * cookie,int flags)1318 ffb_i2c_send_stop(void *cookie, int flags)
1319 {
1320
1321 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops));
1322 }
1323
1324 static int
ffb_i2c_initiate_xfer(void * cookie,i2c_addr_t addr,int flags)1325 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
1326 {
1327 /*
1328 * for some reason i2c_bitbang_initiate_xfer left-shifts
1329 * the I2C-address and then sets the direction bit
1330 */
1331 return (i2c_bitbang_initiate_xfer(cookie, addr, flags,
1332 &ffb_i2cbb_ops));
1333 }
1334
1335 static int
ffb_i2c_read_byte(void * cookie,uint8_t * valp,int flags)1336 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags)
1337 {
1338 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops));
1339 }
1340
1341 static int
ffb_i2c_write_byte(void * cookie,uint8_t val,int flags)1342 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags)
1343 {
1344 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops));
1345 }
1346
1347
1348 #define TVC_READ_LIMIT 100000
1349 int
ffb_tgc_disable(struct ffb_softc * sc)1350 ffb_tgc_disable(struct ffb_softc *sc)
1351 {
1352 int i;
1353
1354 /* Is the timing generator disabled? */
1355 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC);
1356 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE))
1357 return 1;
1358
1359 /* If not, disable it when the vertical counter reaches 0 */
1360 for (i = 0; i < TVC_READ_LIMIT; i++) {
1361 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC);
1362 if (!DAC_READ(sc, FFB_DAC_VALUE)) {
1363 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC);
1364 DAC_WRITE(sc, FFB_DAC_VALUE, 0);
1365 return 1;
1366 }
1367 }
1368 return 0;
1369 }
1370
1371 /*
1372 * PLL Control Register values:
1373 * M)ultiplier = bits 0:6 + 1
1374 * D)ivisor = bits 7:10 + 1
1375 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8)
1376 * Frequency = 13.5 * M / D / P
1377 */
1378 #define FFB_PLL_FREQ 13500000
1379 void
ffb_get_pclk(int request,uint32_t * pll,int * diff)1380 ffb_get_pclk(int request, uint32_t *pll, int *diff)
1381 {
1382 int m, d, p, f, hex = 0, curdiff;
1383
1384 *diff = 100000000;
1385
1386 for (m = 32; m <= 80; m++) {
1387 for (d = 4; d <= 11; d++) {
1388 for (p = 1; p <= 8; p = p << 1) {
1389 switch (p) {
1390 case 1:
1391 hex = 0x4000 + (d << 7) + m;
1392 break;
1393 case 2:
1394 hex = 0x4800 + (d << 7) + m;
1395 break;
1396 case 4:
1397 hex = 0x5000 + (d << 7) + m;
1398 break;
1399 case 8:
1400 hex = 0x6000 + (d << 7) + m;
1401 break;
1402 }
1403 f = 13500000 * m / d / p;
1404 if (f == request) {
1405 *diff = 0;
1406 *pll = hex;
1407 return;
1408 } else {
1409 curdiff = abs(request - f);
1410 if (curdiff < *diff) {
1411 *diff = curdiff;
1412 *pll = hex;
1413 }
1414 }
1415 }
1416 }
1417 }
1418 }
1419
1420 /*
1421 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498
1422 * and in the Connexant BT497A/498A documentation.
1423 *
1424 * VESA timings to FFB register conversion:
1425 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4
1426 * VBE = VBS - vres = (sync pulse - 1) + back porch
1427 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres
1428 * VSE = sync pulse - 1
1429 * VSS = (sync pulse - 1) + back porch + vres + front porch
1430 * HRE = HSS - HSE - 1
1431 * HBE = (sync pulse + back porch) / x - 1
1432 * HBS = (sync pulse + back porch + hres) / x - 1
1433 * HSE = sync pulse / x - 1
1434 * HSS = (sync pulse + back porch + hres + front porch) / x - 1
1435 * HCE = HBS - 4
1436 * HCS = HBE - 4
1437 * EPE = EIE = EIS = 0 (for all non-interlaced modes)
1438 *
1439 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the
1440 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024
1441 *
1442 * Note, that the timing generator should be disabled and re-enabled when the
1443 * the timing parameter registers are being programmed. Stopping the timing
1444 * generator should only be done when the vertical counter is zero.
1445 */
1446 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y))
1447 int
ffb_set_vmode(struct ffb_softc * sc,struct videomode * mode,int btype,int * hres,int * vres)1448 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype,
1449 int *hres, int *vres)
1450 {
1451 int diff;
1452 uint32_t fp, sp, bp, x;
1453 uint32_t pll, pfc, ucl, dcl, tgc;
1454 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs;
1455 uint32_t epe, eie, eis;
1456 uint32_t fbcfg0;
1457
1458 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay,
1459 DIVIDE(DIVIDE(mode->dot_clock * 1000,
1460 mode->htotal), mode->vtotal)));
1461 DPRINTF((" (%d %d %d %d %d %d %d",
1462 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal,
1463 mode->vsync_start, mode->vsync_end, mode->vtotal));
1464 DPRINTF((" %s%sH %s%sV)\n",
1465 mode->flags & VID_PHSYNC ? "+" : "",
1466 mode->flags & VID_NHSYNC ? "-" : "",
1467 mode->flags & VID_PVSYNC ? "+" : "",
1468 mode->flags & VID_NVSYNC ? "-" : ""));
1469
1470 /* We don't handle interlaced or doublescan (yet) */
1471 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN))
1472 return 0;
1473
1474 /* Only Creator3D can be set to > 1280x1024 */
1475 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) ||
1476 sc->sc_type == FFB_AFB)
1477 && (mode->hdisplay > 1280 || mode->vdisplay > 1024))
1478 return 0;
1479 /* Creator3D can be set to <= 1920x1360 */
1480 if (mode->hdisplay > 1920 || mode->vdisplay > 1360)
1481 return 0;
1482
1483 /*
1484 * Look for a matching pixel clock and set PLL Control.
1485 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the
1486 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090)
1487 * does not work. So, use the PROM value instead.
1488 */
1489 if (mode->hdisplay == 640 && mode->vdisplay == 480 &&
1490 mode->dot_clock == 25175) {
1491 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n"));
1492 mode->dot_clock = 25125;
1493 }
1494 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff);
1495 if (diff > 250000)
1496 return 0;
1497
1498 /* Pixel Format Control, User Control and FBC Configuration. */
1499 if (mode->hdisplay > 1280) {
1500 pfc = FFB_DAC_PIX_FMT_821;
1501 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C;
1502 x = 4;
1503 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF;
1504 } else {
1505 pfc = FFB_DAC_PIX_FMT_421;
1506 /* Only Creator3D and Elite3D can have double-buffer */
1507 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)))
1508 ucl = 0;
1509 else
1510 ucl = FFB_DAC_USR_CTRL_DOUBLE;
1511 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8);
1512 x = 2;
1513 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF;
1514 }
1515
1516 /* DAC Control and Timing Generator Control */
1517 if (mode->flags & VID_PVSYNC)
1518 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC;
1519 else
1520 dcl = 0;
1521 tgc = 0;
1522 #define EDID_VID_INP sc->sc_edid_info.edid_video_input
1523 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) {
1524 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS;
1525 tgc = FFB_DAC_TGC_EQUAL_DISABLE;
1526 } else {
1527 dcl |= FFB_DAC_DAC_CTRL_SYNC_G;
1528 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS)
1529 tgc |= FFB_DAC_TGC_VSYNC_DISABLE;
1530 else
1531 tgc = FFB_DAC_TGC_EQUAL_DISABLE;
1532 }
1533 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK)
1534 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE;
1535 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE |
1536 FFB_DAC_TGC_MASTER_ENABLE);
1537
1538 /* Vertical timing */
1539 fp = mode->vsync_start - mode->vdisplay;
1540 sp = mode->vsync_end - mode->vsync_start;
1541 bp = mode->vtotal - mode->vsync_end;
1542
1543 vbe = sp - 1 + bp;
1544 vbs = sp - 1 + bp + mode->vdisplay;
1545 vse = sp - 1;
1546 vss = sp - 1 + bp + mode->vdisplay + fp;
1547
1548 /* Horizontal timing */
1549 fp = mode->hsync_start - mode->hdisplay;
1550 sp = mode->hsync_end - mode->hsync_start;
1551 bp = mode->htotal - mode->hsync_end;
1552
1553 hbe = (sp + bp) / x - 1;
1554 hbs = (sp + bp + mode->hdisplay) / x - 1;
1555 hse = sp / x - 1;
1556 hss = (sp + bp + mode->hdisplay + fp) / x -1;
1557 hre = hss - hse - 1;
1558 hce = hbs - 4;
1559 hcs = hbe - 4;
1560
1561 /* Equalisation (interlaced modes) */
1562 epe = 0;
1563 eie = 0;
1564 eis = 0;
1565
1566 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n",
1567 pll, pfc, ucl, dcl, tgc));
1568 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss));
1569 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n",
1570 hre, hbe, hbs, hse, hss, hce, hcs));
1571 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis));
1572
1573 if (!ffb_tgc_disable(sc)) {
1574 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n"));
1575 return 0;
1576 }
1577
1578 /*
1579 * Program the mode registers.
1580 * Program the timing generator last, as that re-enables output.
1581 * Note, that a read to/write from a register increments the
1582 * register address to the next register automatically.
1583 */
1584 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL);
1585 DAC_WRITE(sc, FFB_DAC_VALUE, pll);
1586 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT);
1587 DAC_WRITE(sc, FFB_DAC_VALUE, pfc);
1588 DAC_WRITE(sc, FFB_DAC_VALUE, ucl);
1589 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL);
1590 DAC_WRITE(sc, FFB_DAC_VALUE, dcl);
1591
1592 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE);
1593 DAC_WRITE(sc, FFB_DAC_VALUE, vbe);
1594 DAC_WRITE(sc, FFB_DAC_VALUE, vbs);
1595 DAC_WRITE(sc, FFB_DAC_VALUE, vse);
1596 DAC_WRITE(sc, FFB_DAC_VALUE, vss);
1597
1598 DAC_WRITE(sc, FFB_DAC_VALUE, hre);
1599 DAC_WRITE(sc, FFB_DAC_VALUE, hbe);
1600 DAC_WRITE(sc, FFB_DAC_VALUE, hbs);
1601 DAC_WRITE(sc, FFB_DAC_VALUE, hse);
1602 DAC_WRITE(sc, FFB_DAC_VALUE, hss);
1603 DAC_WRITE(sc, FFB_DAC_VALUE, hce);
1604 DAC_WRITE(sc, FFB_DAC_VALUE, hcs);
1605
1606 DAC_WRITE(sc, FFB_DAC_VALUE, epe);
1607 DAC_WRITE(sc, FFB_DAC_VALUE, eie);
1608 DAC_WRITE(sc, FFB_DAC_VALUE, eis);
1609
1610 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0);
1611
1612 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC);
1613 DAC_WRITE(sc, FFB_DAC_VALUE, tgc);
1614 DPRINTF(("new tgc: %08x\n", tgc));
1615
1616 *hres = mode->hdisplay;
1617 *vres = mode->vdisplay;
1618
1619 printf("%s: video mode set to %d x %d @ %dHz\n",
1620 device_xname(sc->sc_dev),
1621 mode->hdisplay, mode->vdisplay,
1622 DIVIDE(DIVIDE(mode->dot_clock * 1000,
1623 mode->htotal), mode->vtotal));
1624
1625 return 1;
1626 }
1627