1 /* $NetBSD: pci_machdep.c,v 1.22 2023/12/20 05:33:19 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000 Matthew R. Green
5 * Copyright (c) 2001 Valeriy E. Ushakov
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /*
33 * Machine-dependent PCI bits for PCI controller in microSPARC-IIep.
34 * References are to the microSPARC-IIep manual unless noted otherwise.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.22 2023/12/20 05:33:19 thorpej Exp $");
39
40 #if defined(DEBUG) && !defined(SPARC_PCI_DEBUG)
41 #define SPARC_PCI_DEBUG
42 #endif
43
44 #ifdef SPARC_PCI_DEBUG
45 #define SPDB_CONF 0x01
46 #define SPDB_INTR 0x04
47 #define SPDB_INTMAP 0x08
48 #define SPDB_INTFIX 0x10
49 #define SPDB_PROBE 0x20
50 int sparc_pci_debug = 0;
51 #define DPRINTF(l, s) do { \
52 if (sparc_pci_debug & (l)) \
53 printf s; \
54 } while (/* CONSTCOND */ 0)
55 #else
56 #define DPRINTF(l, s)
57 #endif
58
59 #include <sys/types.h>
60 #include <sys/param.h>
61 #include <sys/time.h>
62 #include <sys/systm.h>
63 #include <sys/errno.h>
64 #include <sys/device.h>
65
66 #include <sys/bus.h>
67 #include <machine/autoconf.h>
68
69 #include <machine/ctlreg.h>
70 #include <sparc/sparc/asm.h>
71
72 #include <dev/pci/pcivar.h>
73 #include <dev/pci/pcireg.h>
74
75 #include <dev/ofw/ofw_pci.h>
76
77 #include <sparc/sparc/msiiepreg.h>
78 #include <sparc/sparc/msiiepvar.h>
79
80 /*
81 * Table 9-1 (p. 129).
82 * Configuration space access. This goes via MMU bypass ASI.
83 */
84 #define PCI_MODE1_ADDRESS_REG_PA 0x30080000
85 #define PCI_MODE1_DATA_REG_PA 0x300a0000
86
87 /*
88 * Footnote 1 in Table 9-1 (p. 129):
89 *
90 * Three least significant bits of the configuration data space
91 * access must match those of the configuration address space access.
92 */
93 #define PCI_MODE1_DATA_REG_MASK 0x7
94
95
96 /*
97 * PROMs in ms-IIep systems just lie about PCI and EBus interrupts, so
98 * we just hardcode the wiring based on the model we are running on.
99 * Probably we can do some forth hacking in boot loader's prompatch
100 * (that's what it was introduced for), but for now it's way more
101 * simple to just hardcode it here.
102 * XXX: Unknown mappings for PCI slots set to line 8.
103 */
104
105 struct mspcic_pci_intr_wiring {
106 u_int mpiw_bus;
107 u_int mpiw_device;
108 u_int mpiw_function;
109 pci_intr_line_t mpiw_line[4]; /* Int A (0) - Int D (3) */
110 };
111
112 static struct mspcic_pci_intr_wiring krups_pci_intr_wiring[] = {
113 { 0, 0, 1, { 1, 0, 0, 0 } }, /* ethernet */
114 { 0, 1, 0, { 2, 0, 0, 0 } }, /* vga */
115 };
116
117 static struct mspcic_pci_intr_wiring espresso_pci_intr_wiring[] = {
118 { 0, 0, 1, { 1, 0, 0, 0 } }, /* ethernet */
119 { 0, 1, 0, { 2, 0, 0, 0 } }, /* vga */
120 { 0, 2, 0, { 6, 7, 8, 8 } }, /* pci slot1 */
121 { 0, 2, 1, { 6, 7, 8, 8 } }, /* pci slot1 */
122 { 0, 2, 2, { 6, 7, 8, 8 } }, /* pci slot1 */
123 { 0, 2, 3, { 6, 7, 8, 8 } }, /* pci slot1 */
124 { 0, 2, 4, { 6, 7, 8, 8 } }, /* pci slot1 */
125 { 0, 2, 5, { 6, 7, 8, 8 } }, /* pci slot1 */
126 { 0, 2, 6, { 6, 7, 8, 8 } }, /* pci slot1 */
127 { 0, 2, 7, { 6, 7, 8, 8 } }, /* pci slot1 */
128 { 0, 3, 0, { 7, 8, 8, 8 } }, /* pci slot2 */
129 { 0, 3, 1, { 7, 8, 8, 8 } }, /* pci slot2 */
130 { 0, 3, 2, { 7, 8, 8, 8 } }, /* pci slot2 */
131 { 0, 3, 3, { 7, 8, 8, 8 } }, /* pci slot2 */
132 { 0, 3, 4, { 7, 8, 8, 8 } }, /* pci slot2 */
133 { 0, 3, 5, { 7, 8, 8, 8 } }, /* pci slot2 */
134 { 0, 3, 6, { 7, 8, 8, 8 } }, /* pci slot2 */
135 { 0, 3, 7, { 7, 8, 8, 8 } }, /* pci slot2 */
136 { 0, 7, 0, { 4, 0, 0, 0 } }, /* isa */
137 { 0, 16, 0, { 5, 0, 0, 0 } }, /* eide */
138 { 0, 20, 0, { 5, 0, 0, 0 } }, /* usb */
139 };
140
141 struct mspcic_known_model {
142 const char *model;
143 struct mspcic_pci_intr_wiring *map;
144 int mapsize;
145 };
146
147 #define MSPCIC_MODEL_WIRING(name,map) \
148 { name, map, sizeof(map)/sizeof(map[0]) }
149
150 static struct mspcic_known_model mspcic_known_models[] = {
151 MSPCIC_MODEL_WIRING("SUNW,501-4267", krups_pci_intr_wiring),
152 MSPCIC_MODEL_WIRING("SUNW,375-0059", espresso_pci_intr_wiring),
153 { NULL, NULL, 0}
154 };
155
156
157 static struct mspcic_pci_intr_wiring *wiring_map;
158 static int wiring_map_size;
159
160
161 void
pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)162 pci_attach_hook(device_t parent, device_t self,
163 struct pcibus_attach_args *pba)
164 {
165 struct mspcic_known_model *p;
166 char buf[32];
167 char *model;
168
169 /* We only need to run once (root PCI bus is 0) */
170 if (pba->pba_bus != 0)
171 return;
172
173 model = prom_getpropstringA(prom_findroot(), "model",
174 buf, sizeof(buf));
175 if (model == NULL)
176 panic("pci_attach_hook: no \"model\" property");
177
178 printf(": model %s", model);
179
180 for (p = mspcic_known_models; p->model != NULL; ++p)
181 if (strcmp(model, p->model) == 0) {
182 printf(": interrupt wiring known");
183 wiring_map = p->map;
184 wiring_map_size = p->mapsize;
185 return;
186 }
187
188 /* not found */
189 printf(": don't know how interrupts are wired\n");
190 panic("pci_attach_hook: unknown model %s", model);
191 }
192
193
194 int
pci_bus_maxdevs(pci_chipset_tag_t pc,int busno)195 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
196 {
197
198 return 32;
199 }
200
201
202 pcitag_t
pci_make_tag(pci_chipset_tag_t pc,int b,int d,int f)203 pci_make_tag(pci_chipset_tag_t pc, int b, int d, int f)
204 {
205 struct mspcic_softc *sc = (struct mspcic_softc *)pc->cookie;
206 pcitag_t tag;
207 int node, len;
208 #ifdef SPARC_PCI_DEBUG
209 char name[80];
210
211 memset(name, 0, sizeof(name));
212 #endif
213 tag = PCITAG_CREATE(-1, b, d, f);
214 if (b >= 256 || d >= 32 || f >= 8) {
215 printf("pci_make_tag: bad request %d/%d/%d\n", b, d, f);
216 return tag; /* a dead one */
217 }
218
219 /*
220 * XXX: OFW 3.11 doesn't have "bus-range" property on its
221 * "/pci" node. As a workaround we start with the first child
222 * of "/pci" instead of matching the bus number against the
223 * "bus-range" of the "/pci" node.
224 *
225 * Traverse all peers until we find the node.
226 */
227 for (node = OF_child(sc->sc_node); node != 0; node = OF_peer(node)) {
228 struct ofw_pci_register reg;
229 uint32_t busrange[2];
230 int class;
231 pcireg_t busdata;
232 pcitag_t bustag;
233
234 #ifdef SPARC_PCI_DEBUG
235 if (sparc_pci_debug & SPDB_PROBE) {
236 OF_getprop(node, "name", &name, sizeof(name));
237 printf("> checking node %x %s\n", node, name);
238 }
239 #endif
240 /*
241 * Check for PCI-PCI bridges. If the device we want is
242 * in the bus-range for that bridge, work our way down.
243 */
244 while ((OF_getprop(node, "bus-range", (void *)&busrange,
245 sizeof(busrange)) == sizeof(busrange))
246 && (b >= busrange[0] && b <= busrange[1]))
247 {
248 /* go down one level */
249 node = OF_child(node);
250 #ifdef SPARC_PCI_DEBUG
251 if (sparc_pci_debug & SPDB_PROBE) {
252 OF_getprop(node, "name", &name, sizeof(name));
253 printf("> going down to node %x %s\n",
254 node, name);
255 }
256 #endif
257 }
258
259 /*
260 * We only really need the first `reg' property.
261 *
262 * For simplicity, we'll query the `reg' when we
263 * need it. Otherwise we could malloc() it, but
264 * that gets more complicated.
265 */
266 len = OF_getproplen(node, "reg");
267 OF_getprop(node, "reg", (void *)®, sizeof(reg));
268
269 /*
270 * Check for (OFW unconfigured) bridges that we fixed up.
271 * We'll set this top-level bridge's node in the tag,
272 * so that we can use it later for interrupt wiring.
273 */
274 if (b > 0) {
275 len = OF_getproplen(node, "class-code");
276 if (!len)
277 continue;
278 OF_getprop(node, "class-code", &class, len);
279 if (IS_PCI_BRIDGE(class)) {
280 bustag = PCITAG_CREATE(node,
281 OFW_PCI_PHYS_HI_BUS(reg.phys_hi),
282 OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi),
283 OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi));
284 busdata = pci_conf_read(NULL, bustag,
285 PCI_BRIDGE_BUS_REG);
286 if (b != ((busdata >> 8) & 0xff))
287 continue;
288
289 #ifdef SPARC_PCI_DEBUG
290 if (sparc_pci_debug & SPDB_PROBE) {
291 OF_getprop(node, "name", &name,
292 sizeof(name));
293 printf("> matched device behind node "
294 "%x %s (bus %d)\n", node, name, b);
295 }
296 #endif
297 } else
298 continue;
299 } else {
300 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
301 continue;
302 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
303 continue;
304 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
305 continue;
306 }
307
308 /* Got a match */
309 tag = PCITAG_CREATE(node, b, d, f);
310 DPRINTF(SPDB_PROBE, ("> found node %x %s\n", node, name));
311 return tag;
312 }
313
314 /* No device found - return a dead tag */
315 return tag;
316 }
317
318
319 void
pci_decompose_tag(pci_chipset_tag_t pc,pcitag_t tag,int * bp,int * dp,int * fp)320 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
321 int *bp, int *dp, int *fp)
322 {
323
324 if (bp != NULL)
325 *bp = PCITAG_BUS(tag);
326 if (dp != NULL)
327 *dp = PCITAG_DEV(tag);
328 if (fp != NULL)
329 *fp = PCITAG_FUN(tag);
330 }
331
332
333 pcireg_t
pci_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)334 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
335 {
336 uint32_t mode1_addr;
337 uint32_t mode1_data_reg_pa;
338 uint32_t val;
339
340 DPRINTF(SPDB_CONF,
341 ("pci_conf_read: tag=%x.%x (%d/%d/%d), reg=%02x; ",
342 PCITAG_NODE(tag), PCITAG_OFFSET(tag),
343 PCITAG_BUS(tag), PCITAG_DEV(tag), PCITAG_FUN(tag),
344 reg));
345
346 #ifdef DIAGNOSTIC
347 if (reg & 0x3)
348 panic("pci_conf_read: reg %x unaligned", reg);
349 #endif
350
351 if (PCITAG_NODE(tag) == -1) {
352 DPRINTF(SPDB_CONF, ("\n"));
353 return ~0;
354 }
355
356 if ((unsigned int)reg >= PCI_CONF_SIZE)
357 return ~0;
358
359 mode1_addr = PCITAG_OFFSET(tag) | reg;
360 mode1_data_reg_pa = PCI_MODE1_DATA_REG_PA
361 | (reg & PCI_MODE1_DATA_REG_MASK);
362
363 sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, htole32(mode1_addr));
364 val = le32toh(lda(mode1_data_reg_pa, ASI_BYPASS));
365
366 DPRINTF(SPDB_CONF, ("reading %08x\n", val));
367
368 return val;
369 }
370
371
372 void
pci_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)373 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
374 {
375 uint32_t mode1_addr;
376 uint32_t mode1_data_reg_pa;
377
378 DPRINTF(SPDB_CONF,
379 ("pci_conf_write: tag=%x.%x (%d/%d/%d); reg=%02x; ",
380 PCITAG_NODE(tag), PCITAG_OFFSET(tag),
381 PCITAG_BUS(tag), PCITAG_DEV(tag), PCITAG_FUN(tag),
382 reg));
383
384 #ifdef DIAGNOSTIC
385 if (reg & 0x3)
386 panic("pci_conf_write: reg %x unaligned", reg);
387 #endif
388
389 if (PCITAG_NODE(tag) == -1) {
390 DPRINTF(SPDB_CONF, ("\n"));
391 return;
392 }
393
394 if ((unsigned int)reg >= PCI_CONF_SIZE)
395 return;
396
397 mode1_addr = PCITAG_OFFSET(tag) | reg;
398 mode1_data_reg_pa = PCI_MODE1_DATA_REG_PA
399 | (reg & PCI_MODE1_DATA_REG_MASK);
400
401 DPRINTF(SPDB_CONF, ("writing %08x\n", data));
402
403 sta(PCI_MODE1_ADDRESS_REG_PA, ASI_BYPASS, htole32(mode1_addr));
404 sta(mode1_data_reg_pa, ASI_BYPASS, htole32(data));
405 }
406
407
408 /* ======================================================================
409 *
410 * PCI bus interrupt manipulation functions
411 */
412
413 int
pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)414 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
415 {
416 int i, node;
417 pcitag_t tag;
418 pcireg_t val;
419 pci_intr_pin_t pin;
420
421 DPRINTF(SPDB_INTMAP,
422 ("pci_intr_map(%d/%d/%d) -> ",
423 pa->pa_bus, pa->pa_device, pa->pa_function));
424
425 tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device,
426 pa->pa_function);
427 node = PCITAG_NODE(tag);
428 val = pci_conf_read(NULL, tag, PCI_INTERRUPT_REG);
429 pin = PCI_INTERRUPT_PIN(val);
430
431 /*
432 * Pin should be A(1) to D(4) - use values 0 to 3 respectively to
433 * represent them. Built-in devices might show pin 0, so assume
434 * pin A for those - the static wiring map has the correct line.
435 */
436 if (pin)
437 pin -= 1;
438
439 for (i = 0; i < wiring_map_size; ++i) {
440 struct mspcic_pci_intr_wiring *w = &wiring_map[i];
441
442 /* Device on PCI bus 0 */
443 if (pa->pa_bus == w->mpiw_bus
444 && pa->pa_device == w->mpiw_device
445 && pa->pa_function == w->mpiw_function)
446 {
447 if (w->mpiw_line[pin] > 7) {
448 DPRINTF(SPDB_INTMAP, ("not mapped\n"));
449 return -1;
450 }
451 DPRINTF(SPDB_INTMAP, ("pin %c line %d\n", 'A' + pin,
452 w->mpiw_line[pin]));
453 *ihp = w->mpiw_line[pin];
454 return 0;
455 /* Device on other PCI bus - find top-level bridge device */
456 } else if (pa->pa_bus) {
457 struct ofw_pci_register reg;
458
459 OF_getprop(node, "reg", (void *)®, sizeof(reg));
460 if (OFW_PCI_PHYS_HI_BUS(reg.phys_hi) == w->mpiw_bus
461 && OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)
462 == w->mpiw_device
463 && OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)
464 == w->mpiw_function) {
465 int j;
466
467 /* PCI bridge interrupt swizzle */
468 for (j = 0; j < PCI_INTERRUPT_LINE(val); j++)
469 pin = (pin + (pa->pa_device % 4)) % 4;
470
471 if (w->mpiw_line[pin] > 7) {
472 DPRINTF(SPDB_INTMAP, ("pin %c "
473 "not mapped\n", pin));
474 return -1;
475 }
476 DPRINTF(SPDB_INTMAP, ("pin %c line %d "
477 "via bridge (%d/%d/%d) depth %d\n",
478 'A' + pin, w->mpiw_line[pin],
479 w->mpiw_bus, w->mpiw_device,
480 w->mpiw_function,
481 PCI_INTERRUPT_LINE(val)));
482 *ihp = w->mpiw_line[pin];
483 return 0;
484 }
485 }
486 }
487
488 DPRINTF(SPDB_INTMAP, ("not found\n"));
489 return -1;
490 }
491
492
493 const char *
pci_intr_string(pci_chipset_tag_t pc,pci_intr_handle_t ih,char * buf,size_t len)494 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf,
495 size_t len)
496 {
497 int pil;
498
499 pil = mspcic_assigned_interrupt(ih);
500 snprintf(buf, len, "line %d (pil %d)", ih, pil);
501 return buf;
502 }
503
504
505 const struct evcnt *
pci_intr_evcnt(pci_chipset_tag_t pc,pci_intr_handle_t ih)506 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
507 {
508
509 /* XXX for now, no evcnt parent reported */
510 return NULL;
511 }
512
513 int
pci_intr_setattr(pci_chipset_tag_t pc,pci_intr_handle_t * ih,int attr,uint64_t data)514 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
515 int attr, uint64_t data)
516 {
517
518 switch (attr) {
519 case PCI_INTR_MPSAFE:
520 return 0;
521 default:
522 return ENODEV;
523 }
524 }
525
526 void *
pci_intr_establish(pci_chipset_tag_t pc,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg)527 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih,
528 int level, int (*func)(void *), void *arg)
529 {
530 struct mspcic_softc *sc = (struct mspcic_softc *)pc->cookie;
531 void *cookie;
532
533 DPRINTF(SPDB_INTR,
534 ("pci_intr_establish(line %d, ipl %d)\n", ih, level));
535
536 cookie = bus_intr_establish(sc->sc_memt, ih, level, func, arg);
537
538 /*
539 * TODO: to implement pci_intr_disestablish we need to capture
540 * the 'intrhand' returned by bus_intr_establish above and the
541 * pil the handler was established for, but we don't need to
542 * disestablish pci interrupts for now (and I doubt we will),
543 * so why bother.
544 */
545
546 DPRINTF(SPDB_INTR,
547 ("pci_intr_establish: returning handle %p\n", cookie));
548 return cookie;
549 }
550
551
552 void
pci_intr_disestablish(pci_chipset_tag_t pc,void * cookie)553 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
554 {
555
556 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
557 panic("pci_intr_disestablish: not implemented");
558 }
559