1 /* $NetBSD: vlpci.c,v 1.13 2022/01/21 19:12:28 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2017 Jonathan A. Kollasch
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: vlpci.c,v 1.13 2022/01/21 19:12:28 thorpej Exp $");
31
32 #include "opt_pci.h"
33 #include "pci.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/device.h>
38 #include <sys/extent.h>
39 #include <sys/mutex.h>
40 #include <uvm/uvm.h>
41 #include <machine/pio.h>
42 #include <machine/pmap.h>
43 #include <machine/ofw.h>
44
45 #include <dev/isa/isavar.h>
46
47 #include <dev/ofw/openfirm.h>
48
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pciconf.h>
51 #include <arm/pci_machdep.h>
52
53 #include <shark/ofw/vlpci.h>
54
55 #define VLPCI_ADDON_DEV_NO 6
56 #define VLPCI_IRQ 10
57
58 #define VLPCI_PCI_MEM_BASE 0x02000000
59 #define VLPCI_PCI_MEM_SZ 1048576
60
61 #define VLPCI_VL_MEM_BASE 0x08000000
62 #define VLPCI_VL_MEM_SZ 4194304
63
64 static int vlpci_match(device_t, struct cfdata *, void *);
65 static void vlpci_attach(device_t, device_t, void *);
66
67 static void vlpci_pc_attach_hook(device_t, device_t,
68 struct pcibus_attach_args *);
69 static int vlpci_pc_bus_maxdevs(void *, int);
70 static pcitag_t vlpci_pc_make_tag(void *, int, int, int);
71 static void vlpci_pc_decompose_tag(void *, pcitag_t, int *, int *, int *);
72 static pcireg_t vlpci_pc_conf_read(void *, pcitag_t, int);
73 static void vlpci_pc_conf_write(void *, pcitag_t, int, pcireg_t);
74
75 static int vlpci_pc_intr_map(const struct pci_attach_args *,
76 pci_intr_handle_t *);
77 static const char * vlpci_pc_intr_string(void *, pci_intr_handle_t, char *,
78 size_t);
79 static const struct evcnt * vlpci_pc_intr_evcnt(void *, pci_intr_handle_t);
80 static void * vlpci_pc_intr_establish(void *, pci_intr_handle_t, int,
81 int (*)(void *), void *, const char *);
82 static void vlpci_pc_intr_disestablish(void *, void *);
83
84 #ifdef __HAVE_PCI_CONF_HOOK
85 static int vlpci_pc_conf_hook(void *, int, int, int, pcireg_t);
86 #endif
87 static void vlpci_pc_conf_interrupt(void *, int, int, int, int, int *);
88
89 struct vlpci_softc {
90 device_t sc_dev;
91 kmutex_t sc_lock;
92 bus_space_handle_t sc_conf_ioh;
93 bus_space_handle_t sc_reg_ioh;
94 struct arm32_pci_chipset sc_pc;
95 };
96
97 CFATTACH_DECL_NEW(vlpci, sizeof(struct vlpci_softc),
98 vlpci_match, vlpci_attach, NULL, NULL);
99
100 static const struct device_compatible_entry compat_data[] = {
101 { .compat = "via,vt82c505" },
102 DEVICE_COMPAT_EOL
103 };
104
105 vaddr_t vlpci_mem_vaddr = 0;
106 paddr_t vlpci_mem_paddr;
107 struct bus_space vlpci_memt;
108
109 static void
regwrite_1(struct vlpci_softc * const sc,uint8_t off,uint8_t val)110 regwrite_1(struct vlpci_softc * const sc, uint8_t off, uint8_t val)
111 {
112
113 mutex_spin_enter(&sc->sc_lock);
114 bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_IDX_OFF,
115 off);
116 bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_DATA_OFF,
117 val);
118 mutex_spin_exit(&sc->sc_lock);
119 }
120
121 static uint8_t
regread_1(struct vlpci_softc * const sc,uint8_t off)122 regread_1(struct vlpci_softc * const sc, uint8_t off)
123 {
124 uint8_t reg;
125
126 mutex_spin_enter(&sc->sc_lock);
127 bus_space_write_1(&isa_io_bs_tag, sc->sc_reg_ioh, VLPCI_INTREG_IDX_OFF,
128 off);
129 reg = bus_space_read_1(&isa_io_bs_tag, sc->sc_reg_ioh,
130 VLPCI_INTREG_DATA_OFF);
131 mutex_spin_exit(&sc->sc_lock);
132 return reg;
133 }
134
135 static void
vlpci_dump_window(struct vlpci_softc * sc,int num)136 vlpci_dump_window(struct vlpci_softc *sc, int num)
137 {
138 int regaddr = VLPCI_PCI_WND_HIADDR_REG(num);
139 uint32_t addr, size;
140 uint8_t attr;
141
142 addr = regread_1(sc, regaddr) << 24;
143 addr |= regread_1(sc, regaddr + 1) << 16;
144 attr = regread_1(sc, regaddr + 2);
145 size = 0x00010000 << __SHIFTOUT(attr, VLPCI_PCI_WND_ATTR_SZ);
146 printf("memory window #%d at %08x size %08x flags %x\n", num, addr,
147 size, attr);
148 }
149
150 static int
vlpci_map(void * t,bus_addr_t bpa,bus_size_t size,int cacheable,bus_space_handle_t * bshp)151 vlpci_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable,
152 bus_space_handle_t *bshp)
153 {
154
155 *bshp = vlpci_mem_vaddr - VLPCI_PCI_MEM_BASE + bpa;
156 printf("%s: %08lx -> %08lx\n", __func__, bpa, *bshp);
157 return(0);
158 }
159
160 static paddr_t
vlpci_mmap(void * cookie,bus_addr_t addr,off_t off,int prot,int flags)161 vlpci_mmap(void *cookie, bus_addr_t addr, off_t off, int prot,
162 int flags)
163 {
164 paddr_t ret;
165
166 ret = vlpci_mem_paddr + addr + off;
167
168 if (flags & BUS_SPACE_MAP_PREFETCHABLE)
169 return (arm_btop(ret) | ARM32_MMAP_WRITECOMBINE);
170 else
171 return arm_btop(ret);
172 }
173
174 static void
vlpci_steer_irq(struct vlpci_softc * const sc)175 vlpci_steer_irq(struct vlpci_softc * const sc)
176 {
177 const unsigned int_ctl[] = {
178 VLPCI_INT_CTL_INTA, VLPCI_INT_CTL_INTB,
179 VLPCI_INT_CTL_INTC, VLPCI_INT_CTL_INTD
180 };
181 uint8_t val;
182
183 for (size_t i = 0; i < __arraycount(int_ctl); i++) {
184 val = regread_1(sc, VLPCI_INT_CTL_REG(int_ctl[i]));
185 val &= ~VLPCI_INT_CTL_INT2IRQ(int_ctl[i]);
186 val |= VLPCI_INT_CTL_ENA(int_ctl[i]);
187 val |= __SHIFTIN(VLPCI_INT_CTL_IRQ(VLPCI_IRQ),
188 VLPCI_INT_CTL_INT2IRQ(int_ctl[i]));
189 regwrite_1(sc, VLPCI_INT_CTL_REG(int_ctl[i]), val);
190 }
191 }
192
193 static int
vlpci_match(device_t parent,struct cfdata * match,void * aux)194 vlpci_match(device_t parent, struct cfdata *match, void *aux)
195 {
196 struct ofbus_attach_args * const oba = aux;
197
198 /* beat generic ofbus */
199 return of_compatible_match(oba->oba_phandle, compat_data) * 2;
200 }
201
202 static void
vlpci_attach(device_t parent,device_t self,void * aux)203 vlpci_attach(device_t parent, device_t self, void *aux)
204 {
205 struct ofbus_attach_args * const oba = aux;
206 struct vlpci_softc * const sc = device_private(self);
207 pci_chipset_tag_t const pc = &sc->sc_pc;
208 struct pcibus_attach_args pba;
209 pcitag_t tag;
210 pcireg_t cmd;
211
212 aprint_normal("\n");
213
214 sc->sc_dev = self;
215 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
216 memset(&pba, 0, sizeof(pba));
217
218 if (bus_space_map(&isa_io_bs_tag, VLPCI_INTREG_BASE, VLPCI_INTREG_SZ,
219 0, &sc->sc_reg_ioh) != 0) {
220 aprint_error_dev(self, "failed to map internal reg port\n");
221 return;
222 }
223 if (bus_space_map(&isa_io_bs_tag, VLPCI_CFGREG_BASE, VLPCI_CFGREG_SZ,
224 0, &sc->sc_conf_ioh) != 0) {
225 aprint_error_dev(self, "failed to map configuration port\n");
226 return;
227 }
228
229 /* Enable VLB/PCI bridge */
230 regwrite_1(sc, VLPCI_MISC_1_REG, VLPCI_MISC_1_LOCAL_PIN |
231 VLPCI_MISC_1_COMPAT_ISA_BOFF);
232 regwrite_1(sc, VLPCI_MISC_CTL_REG, __SHIFTIN(VLPCI_MISC_CTL_HIADDR_DIS,
233 VLPCI_MISC_CTL_HIADDR) | VLPCI_MISC_CTL_IOCHCK_PIN);
234 regwrite_1(sc, VLPCI_CFG_MISC_CTL_REG,
235 __SHIFTIN(VLPCI_CFG_MISC_CTL_INT_CTL_CONV,
236 VLPCI_CFG_MISC_CTL_INT_CTL) | VLPCI_CFG_MISC_CTL_LREQI_LGNTO_PIN);
237 regwrite_1(sc, VLPCI_IRQ_MODE_REG, 0x00); /* don't do per-INTx conversions */
238 vlpci_steer_irq(sc);
239 /*
240 * XXX
241 * set memory size to 255MB, so the bridge knows which cycles go to RAM
242 * shark's RAM is in the upper half of the lower 256MB, part of the
243 * lower half is occupied by the graphics chip
244 * ... or that's the theory. OF puts PCI BARS at 0x02000000 which
245 * overlaps with when we do this and pci memory access doesn't work.
246 */
247 regwrite_1(sc, VLPCI_OBD_MEM_SZ_REG, 1);
248
249 regwrite_1(sc, VLPCI_BUF_CTL_REG, VLPCI_BUF_CTL_PCI_DYN_ACC_DEC);
250 regwrite_1(sc, VLPCI_VL_TIM_REG, VLPCI_VL_TIM_OBD_MEM_1ST_DAT);
251 printf("reg 0x83 %02x\n", regread_1(sc, VLPCI_VL_TIM_REG));
252
253 #if 1
254 /* program window #0 to 0x08000000 */
255 regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_1),
256 VLPCI_PCI_WND_HIADDR_MEM(VLPCI_VL_MEM_BASE));
257 regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_1),
258 VLPCI_PCI_WND_LOADDR_MEM(VLPCI_VL_MEM_BASE));
259 regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_1),
260 VLPCI_PCI_WND_ATTR_VL |
261 __SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_VL_MEM_SZ),
262 VLPCI_PCI_WND_ATTR_SZ));
263 #else
264 regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_1), 0x00);
265 regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_1), 0x00);
266 regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_1), 0x00);
267 #endif
268
269 vlpci_mem_paddr = VLPCI_PCI_MEM_BASE; /* get from OF! */
270
271 /*
272 * we map in 1MB at 0x02000000, so program window #1 accordingly
273 */
274 regwrite_1(sc, VLPCI_PCI_WND_HIADDR_REG(VLPCI_PCI_WND_NO_2),
275 VLPCI_PCI_WND_HIADDR_MEM(vlpci_mem_paddr));
276 regwrite_1(sc, VLPCI_PCI_WND_LOADDR_REG(VLPCI_PCI_WND_NO_2),
277 VLPCI_PCI_WND_LOADDR_MEM(vlpci_mem_paddr));
278 regwrite_1(sc, VLPCI_PCI_WND_ATTR_REG(VLPCI_PCI_WND_NO_2),
279 VLPCI_PCI_WND_ATTR_PCI |
280 __SHIFTIN(VLPCI_PCI_WND_ATTR_SZ_MEM(VLPCI_PCI_MEM_SZ),
281 VLPCI_PCI_WND_ATTR_SZ));
282
283 /* now map in some of the memory space */
284 printf("vlpci_mem_vaddr %08lx\n", vlpci_mem_vaddr);
285 memcpy(&vlpci_memt, &isa_io_bs_tag, sizeof(struct bus_space));
286 vlpci_memt.bs_cookie = (void *)vlpci_mem_vaddr;
287 vlpci_memt.bs_map = vlpci_map;
288 vlpci_memt.bs_mmap = vlpci_mmap;
289
290 pc->pc_conf_v = sc;
291 pc->pc_attach_hook = vlpci_pc_attach_hook;
292 pc->pc_bus_maxdevs = vlpci_pc_bus_maxdevs;
293 pc->pc_make_tag = vlpci_pc_make_tag;
294 pc->pc_decompose_tag = vlpci_pc_decompose_tag;
295 pc->pc_conf_read = vlpci_pc_conf_read;
296 pc->pc_conf_write = vlpci_pc_conf_write;
297
298 pc->pc_intr_v = sc;
299 pc->pc_intr_map = vlpci_pc_intr_map;
300 pc->pc_intr_string = vlpci_pc_intr_string;
301 pc->pc_intr_evcnt = vlpci_pc_intr_evcnt;
302 pc->pc_intr_establish = vlpci_pc_intr_establish;
303 pc->pc_intr_disestablish = vlpci_pc_intr_disestablish;
304
305 #ifdef __HAVE_PCI_CONF_HOOK
306 pc->pc_conf_hook = vlpci_pc_conf_hook;
307 #endif
308 pc->pc_conf_interrupt = vlpci_pc_conf_interrupt;
309
310 /* try to assure IO space is enabled on the default device-function */
311 tag = vlpci_pc_make_tag(sc, 0, VLPCI_ADDON_DEV_NO, 0);
312 cmd = vlpci_pc_conf_read(sc, tag, PCI_COMMAND_STATUS_REG);
313 vlpci_pc_conf_write(sc, tag, PCI_COMMAND_STATUS_REG,
314 cmd | PCI_COMMAND_IO_ENABLE);
315
316 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
317 pba.pba_iot = &isa_io_bs_tag;
318 pba.pba_memt = &vlpci_memt;
319 pba.pba_dmat = &isa_bus_dma_tag;
320 pba.pba_pc = &sc->sc_pc;
321 pba.pba_bus = 0;
322
323 printf("dma %lx %lx, %lx\n", isa_bus_dma_tag._ranges[0].dr_sysbase,
324 isa_bus_dma_tag._ranges[0].dr_busbase,
325 isa_bus_dma_tag._ranges[0].dr_len);
326
327 vlpci_dump_window(sc, VLPCI_PCI_WND_NO_1);
328 vlpci_dump_window(sc, VLPCI_PCI_WND_NO_2);
329 vlpci_dump_window(sc, VLPCI_PCI_WND_NO_3);
330
331 config_found(self, &pba, pcibusprint,
332 CFARGS(.devhandle = device_handle(self)));
333 }
334
335 static void
vlpci_pc_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)336 vlpci_pc_attach_hook(device_t parent, device_t self,
337 struct pcibus_attach_args *pba)
338 {
339 }
340
341 static int
vlpci_pc_bus_maxdevs(void * v,int busno)342 vlpci_pc_bus_maxdevs(void *v, int busno)
343 {
344
345 return busno == 0 ? 32 : 0;
346 }
347
348 static pcitag_t
vlpci_pc_make_tag(void * v,int b,int d,int f)349 vlpci_pc_make_tag(void *v, int b, int d, int f)
350 {
351
352 return (b << 16) | (d << 11) | (f << 8);
353 }
354
355 static void
vlpci_pc_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)356 vlpci_pc_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
357 {
358
359 if (bp)
360 *bp = (tag >> 16) & 0xff;
361 if (dp)
362 *dp = (tag >> 11) & 0x1f;
363 if (fp)
364 *fp = (tag >> 8) & 0x7;
365 }
366
367 static pcireg_t
vlpci_pc_conf_read(void * v,pcitag_t tag,int offset)368 vlpci_pc_conf_read(void *v, pcitag_t tag, int offset)
369 {
370 struct vlpci_softc * const sc = v;
371 pcireg_t ret;
372
373 KASSERT((offset & 3) == 0);
374
375 if (offset >= PCI_CONF_SIZE)
376 return 0xffffffff;
377
378 mutex_spin_enter(&sc->sc_lock);
379 bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh,
380 VLPCI_CFGREG_ADDR_OFF, 0x80000000UL|tag|offset);
381 ret = bus_space_read_4(&isa_io_bs_tag, sc->sc_conf_ioh,
382 VLPCI_CFGREG_DATA_OFF);
383 mutex_spin_exit(&sc->sc_lock);
384
385 #if 0
386 device_printf(sc->sc_dev, "%s tag %x offset %x ret %x\n",
387 __func__, (unsigned int)tag, offset, ret);
388 #endif
389
390 return ret;
391 }
392
393 static void
vlpci_pc_conf_write(void * v,pcitag_t tag,int offset,pcireg_t val)394 vlpci_pc_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
395 {
396 struct vlpci_softc * const sc = v;
397
398 KASSERT((offset & 3) == 0);
399
400 if (offset >= PCI_CONF_SIZE)
401 return;
402
403 #if 0
404 device_printf(sc->sc_dev, "%s tag %x offset %x val %x\n",
405 __func__, (unsigned int)tag, offset, val);
406 #endif
407
408 mutex_spin_enter(&sc->sc_lock);
409 bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh,
410 VLPCI_CFGREG_ADDR_OFF, 0x80000000UL|tag|offset);
411 bus_space_write_4(&isa_io_bs_tag, sc->sc_conf_ioh,
412 VLPCI_CFGREG_DATA_OFF, val);
413 mutex_spin_exit(&sc->sc_lock);
414 }
415
416 static int
vlpci_pc_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ih)417 vlpci_pc_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih)
418 {
419
420 switch (pa->pa_intrpin) {
421 default:
422 case 0:
423 return EINVAL;
424 case 1:
425 case 2:
426 case 3:
427 case 4:
428 *ih = VLPCI_IRQ;
429 return 0;
430 }
431 }
432
433 static const char *
vlpci_pc_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)434 vlpci_pc_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
435 {
436
437 if (ih == PCI_INTERRUPT_PIN_NONE)
438 return NULL;
439 snprintf(buf, len, "irq %llu", ih);
440 return buf;
441 }
442
443 static const struct evcnt *
vlpci_pc_intr_evcnt(void * v,pci_intr_handle_t ih)444 vlpci_pc_intr_evcnt(void *v, pci_intr_handle_t ih)
445 {
446
447 return NULL;
448 }
449
450 static void *
vlpci_pc_intr_establish(void * v,pci_intr_handle_t pih,int ipl,int (* callback)(void *),void * arg,const char * foo)451 vlpci_pc_intr_establish(void *v, pci_intr_handle_t pih, int ipl,
452 int (*callback)(void *), void *arg, const char *foo)
453 {
454
455 if (pih == 0)
456 return NULL;
457
458 return isa_intr_establish(NULL, pih, IST_LEVEL, ipl, callback, arg);
459 }
460
461 static void
vlpci_pc_intr_disestablish(void * v,void * w)462 vlpci_pc_intr_disestablish(void *v, void *w)
463 {
464
465 return isa_intr_disestablish(NULL, v);
466 }
467
468 #ifdef __HAVE_PCI_CONF_HOOK
469 static int
vlpci_pc_conf_hook(void * v,int b,int d,int f,pcireg_t id)470 vlpci_pc_conf_hook(void *v, int b, int d, int f, pcireg_t id)
471 {
472
473 return PCI_CONF_DEFAULT /*& ~PCI_CONF_ENABLE_BM*/;
474 }
475 #endif
476
477 static void
vlpci_pc_conf_interrupt(void * v,int bus,int dev,int ipin,int swiz,int * ilinep)478 vlpci_pc_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz,
479 int *ilinep)
480 {
481
482 *ilinep = 0xff; /* XXX */
483 }
484