1 /* $NetBSD: zs.c,v 1.43 2023/10/24 20:37:16 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross and Wayne Knowles
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Zilog Z8530 Dual UART driver (machine-dependent part)
34 *
35 * Runs two serial lines per chip using slave drivers.
36 * Plain tty/async lines use the zs_async slave.
37 */
38
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.43 2023/10/24 20:37:16 andvar Exp $");
41
42 #include "opt_ddb.h"
43 #include "opt_kgdb.h"
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/conf.h>
48 #include <sys/device.h>
49 #include <sys/file.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/proc.h>
53 #include <sys/tty.h>
54 #include <sys/time.h>
55 #include <sys/syslog.h>
56 #include <sys/cpu.h>
57 #include <sys/intr.h>
58
59 #include <machine/machtype.h>
60 #include <machine/autoconf.h>
61 #include <machine/z8530var.h>
62
63 #include <dev/cons.h>
64 #include <dev/ic/z8530reg.h>
65
66 #include <sgimips/hpc/hpcvar.h>
67 #include <sgimips/hpc/hpcreg.h>
68
69 #include <dev/arcbios/arcbios.h>
70 #include <dev/arcbios/arcbiosvar.h>
71
72 #include "ioconf.h"
73
74 /*
75 * Some warts needed by z8530tty.c -
76 * The default parity REALLY needs to be the same as the PROM uses,
77 * or you can not see messages done with printf during boot-up...
78 */
79 int zs_def_cflag = (CREAD | CS8 | HUPCL);
80
81 #define PCLK 3672000 /* PCLK pin input clock rate */
82
83 #ifndef ZS_DEFSPEED
84 #define ZS_DEFSPEED 9600
85 #endif
86
87 /*
88 * Define interrupt levels.
89 */
90 #define ZSHARD_PRI 64
91
92 /* SGI shouldn't need ZS_DELAY() as recovery time is done in hardware? */
93 #define ZS_DELAY() delay(3)
94
95 /* The layout of this is hardware-dependent (padding, order). */
96 struct zschan {
97 uint8_t pad1[3];
98 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */
99 uint8_t pad2[3];
100 volatile uint8_t zc_data; /* data */
101 };
102
103 struct zsdevice {
104 struct zschan zs_chan_b;
105 struct zschan zs_chan_a;
106 };
107
108 /* Return the byte offset of element within a structure */
109 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el)
110
111 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a)
112 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b)
113 #define ZS_REG_CSR 0
114 #define ZS_REG_DATA 1
115 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B};
116
117 static void zscnprobe (struct consdev *);
118 static void zscninit (struct consdev *);
119 static int zscngetc (dev_t);
120 static void zscnputc (dev_t, int);
121 static void zscnpollc (dev_t, int);
122 #ifdef KGDB
123 void zskgdb (struct zs_chanstate *);
124 #endif
125
126 static int cons_port;
127
128 struct consdev zs_cn = {
129 zscnprobe,
130 zscninit,
131 zscngetc,
132 zscnputc,
133 zscnpollc,
134 NULL,
135 NULL,
136 NULL,
137 NODEV,
138 CN_NORMAL
139 };
140
141 /* Flags from cninit() */
142 static int zs_consunit = -1;
143 static int zs_conschan = -1;
144
145 /* Default speed for all channels */
146 static int zs_defspeed = ZS_DEFSPEED;
147 static volatile int zssoftpending;
148
149 static uint8_t zs_init_reg[16] = {
150 0, /* 0: CMD (reset, etc.) */
151 0, /* 1: No interrupts yet. */
152 ZSHARD_PRI, /* 2: IVECT */
153 ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
154 ZSWR4_CLK_X16 | ZSWR4_ONESB,
155 ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
156 0, /* 6: TXSYNC/SYNCLO */
157 0, /* 7: RXSYNC/SYNCHI */
158 0, /* 8: alias for data port */
159 ZSWR9_MASTER_IE,
160 0, /*10: Misc. TX/RX control bits */
161 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA,
162 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */
163 0, /*13: BAUDHI (default=9600) */
164 ZSWR14_BAUD_ENA,
165 ZSWR15_BREAK_IE,
166 };
167
168
169 /****************************************************************
170 * Autoconfig
171 ****************************************************************/
172
173 /* Definition of the driver for autoconfig. */
174 static int zs_hpc_match(device_t, cfdata_t, void *);
175 static void zs_hpc_attach(device_t, device_t, void *);
176 static int zs_print(void *, const char *name);
177
178 CFATTACH_DECL_NEW(zsc_hpc, sizeof(struct zsc_softc),
179 zs_hpc_match, zs_hpc_attach, NULL, NULL);
180
181 static int zshard (void *);
182 void zssoft (void *);
183 static int zs_get_speed (struct zs_chanstate *);
184 struct zschan *zs_get_chan_addr (int zs_unit, int channel);
185 int zs_getc (void *);
186 void zs_putc (void *, int);
187
188 /*
189 * Is the zs chip present?
190 */
191 static int
zs_hpc_match(device_t parent,cfdata_t cf,void * aux)192 zs_hpc_match(device_t parent, cfdata_t cf, void *aux)
193 {
194 struct hpc_attach_args *ha = aux;
195
196 if (strcmp(ha->ha_name, cf->cf_name) == 0)
197 return (1);
198
199 return (0);
200 }
201
202 /*
203 * Attach a found zs.
204 *
205 * Match slave number to zs unit number, so that misconfiguration will
206 * not set up the keyboard as ttya, etc.
207 */
208 static void
zs_hpc_attach(device_t parent,device_t self,void * aux)209 zs_hpc_attach(device_t parent, device_t self, void *aux)
210 {
211 struct zsc_softc *zsc = device_private(self);
212 struct hpc_attach_args *haa = aux;
213 struct zsc_attach_args zsc_args;
214 struct zs_chanstate *cs;
215 struct zs_channel *ch;
216 int zs_unit, channel, err, s;
217 const char *promconsdev;
218
219 promconsdev = arcbios_GetEnvironmentVariable("ConsoleOut");
220
221 zsc->zsc_dev = self;
222 zsc->zsc_bustag = haa->ha_st;
223 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
224 haa->ha_devoff, 0x10,
225 &zsc->zsc_base)) != 0) {
226 aprint_error(": unable to map 85c30 registers, error = %d\n",
227 err);
228 return;
229 }
230
231 zs_unit = device_unit(self);
232 aprint_normal("\n");
233
234 /*
235 * Initialize software state for each channel.
236 *
237 * Done in reverse order of channels since the first serial port
238 * is actually attached to the *second* channel, and vice versa.
239 * Doing it this way should force a 'zstty*' to attach zstty0 to
240 * channel 1 and zstty1 to channel 0. They couldn't have wired
241 * it up in a more sensible fashion, could they?
242 */
243 for (channel = 1; channel >= 0; channel--) {
244 zsc_args.channel = channel;
245 ch = &zsc->zsc_cs_store[channel];
246 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch;
247
248 zs_lock_init(cs);
249 cs->cs_reg_csr = NULL;
250 cs->cs_reg_data = NULL;
251 cs->cs_channel = channel;
252 cs->cs_private = NULL;
253 cs->cs_ops = &zsops_null;
254 cs->cs_brg_clk = PCLK / 16;
255
256 if (bus_space_subregion(zsc->zsc_bustag, zsc->zsc_base,
257 zs_chan_offset[channel],
258 sizeof(struct zschan),
259 &ch->cs_regs) != 0) {
260 aprint_error_dev(self, "cannot map regs\n");
261 return;
262 }
263 ch->cs_bustag = zsc->zsc_bustag;
264
265 memcpy(cs->cs_creg, zs_init_reg, 16);
266 memcpy(cs->cs_preg, zs_init_reg, 16);
267
268 zsc_args.hwflags = 0;
269 zsc_args.consdev = NULL;
270
271 if (zs_consunit == -1 && zs_conschan == -1) {
272 /*
273 * If this channel is being used by the PROM console,
274 * pass the generic zs driver a 'no reset' flag so the
275 * channel gets left in the appropriate state after
276 * attach.
277 *
278 * Note: the channel mappings are swapped.
279 */
280 if (promconsdev != NULL &&
281 strlen(promconsdev) == 9 &&
282 strncmp(promconsdev, "serial", 6) == 0 &&
283 (promconsdev[7] == '0' || promconsdev[7] == '1')) {
284 if (promconsdev[7] == '1' && channel == 0)
285 zsc_args.hwflags |= ZS_HWFLAG_NORESET;
286 else if (promconsdev[7] == '0' && channel == 1)
287 zsc_args.hwflags |= ZS_HWFLAG_NORESET;
288 }
289 }
290
291 /* If console, don't stomp speed, let zstty know */
292 if (zs_unit == zs_consunit && channel == zs_conschan) {
293 zsc_args.consdev = &zs_cn;
294 zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
295
296 cs->cs_defspeed = zs_get_speed(cs);
297 } else
298 cs->cs_defspeed = zs_defspeed;
299
300 cs->cs_defcflag = zs_def_cflag;
301
302 /* Make these correspond to cs_defcflag (-crtscts) */
303 cs->cs_rr0_dcd = ZSRR0_DCD;
304 cs->cs_rr0_cts = 0;
305 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
306 cs->cs_wr5_rts = 0;
307
308 /*
309 * Clear the master interrupt enable.
310 * The INTENA is common to both channels,
311 * so just do it on the A channel.
312 */
313 if (channel == 0) {
314 zs_write_reg(cs, 9, 0);
315 }
316 /*
317 * Look for a child driver for this channel.
318 * The child attach will setup the hardware.
319 */
320 if (!config_found(self, (void *)&zsc_args, zs_print,
321 CFARGS_NONE)) {
322 /* No sub-driver. Just reset it. */
323 uint8_t reset = (channel == 0) ?
324 ZSWR9_A_RESET : ZSWR9_B_RESET;
325
326 s = splhigh();
327 zs_write_reg(cs, 9, reset);
328 splx(s);
329 }
330 }
331
332
333 zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc);
334 cpu_intr_establish(haa->ha_irq, IPL_TTY, zshard, NULL);
335
336 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
337 device_xname(self), "intr");
338
339 /*
340 * Set the master interrupt enable and interrupt vector.
341 * (common to both channels, do it on A)
342 */
343 cs = zsc->zsc_cs[0];
344 s = splhigh();
345 /* interrupt vector */
346 zs_write_reg(cs, 2, zs_init_reg[2]);
347 /* master interrupt control (enable) */
348 zs_write_reg(cs, 9, zs_init_reg[9]);
349 splx(s);
350 }
351
352 static int
zs_print(void * aux,const char * name)353 zs_print(void *aux, const char *name)
354 {
355 struct zsc_attach_args *args = aux;
356
357 if (name != NULL)
358 aprint_normal("%s: ", name);
359
360 if (args->channel != -1)
361 aprint_normal(" channel %d", args->channel);
362
363 return UNCONF;
364 }
365
366 /*
367 * Our ZS chips all share a common, autovectored interrupt,
368 * so we have to look at all of them on each interrupt.
369 */
370 static int
zshard(void * arg)371 zshard(void *arg)
372 {
373 register struct zsc_softc *zsc;
374 register int rr3, unit, rval, softreq;
375
376 rval = 0;
377 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
378 zsc = device_lookup_private(&zsc_cd, unit);
379 if (zsc == NULL)
380 continue;
381
382 zsc->zsc_intrcnt.ev_count++;
383 while ((rr3 = zsc_intr_hard(zsc))) {
384 rval |= rr3;
385 }
386
387 softreq = zsc->zsc_cs[0]->cs_softreq;
388 softreq |= zsc->zsc_cs[1]->cs_softreq;
389 if (softreq && (zssoftpending == 0)) {
390 zssoftpending = 1;
391 softint_schedule(zsc->sc_si);
392 }
393 }
394 return rval;
395 }
396
397 /*
398 * Similar scheme as for zshard (look at all of them)
399 */
400 void
zssoft(void * arg)401 zssoft(void *arg)
402 {
403 register struct zsc_softc *zsc;
404 register int s, unit;
405
406 /* This is not the only ISR on this IPL. */
407 if (zssoftpending == 0)
408 return;
409
410 /*
411 * The soft intr. bit will be set by zshard only if
412 * the variable zssoftpending is zero. The order of
413 * these next two statements prevents our clearing
414 * the soft intr bit just after zshard has set it.
415 */
416 /*isr_soft_clear(ZSSOFT_PRI);*/
417 zssoftpending = 0;
418
419 /* Make sure we call the tty layer at spltty. */
420 s = spltty();
421 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
422 zsc = device_lookup_private(&zsc_cd, unit);
423 if (zsc == NULL)
424 continue;
425 (void) zsc_intr_soft(zsc);
426 }
427 splx(s);
428 return;
429 }
430
431
432 /*
433 * Compute the current baud rate given a ZS channel.
434 */
435 static int
zs_get_speed(struct zs_chanstate * cs)436 zs_get_speed(struct zs_chanstate *cs)
437 {
438 int tconst;
439
440 tconst = zs_read_reg(cs, 12);
441 tconst |= zs_read_reg(cs, 13) << 8;
442 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
443 }
444
445 /*
446 * MD functions for setting the baud rate and control modes.
447 */
448 int
zs_set_speed(struct zs_chanstate * cs,int bps)449 zs_set_speed(struct zs_chanstate *cs, int bps)
450 {
451 int tconst;
452
453 #if 0
454 while (!(zs_read_csr(cs) & ZSRR0_TX_READY))
455 {/*nop*/}
456 #endif
457 /* Wait for transmit buffer to empty */
458 if (bps == 0) {
459 return (0);
460 }
461
462 #ifdef DIAGNOSTIC
463 if (cs->cs_brg_clk == 0)
464 panic("zs_set_speed");
465 #endif
466
467 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
468 if (tconst < 0)
469 return (EINVAL);
470
471 #if 0
472 /* Convert back to make sure we can do it. */
473 int real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
474
475 /* XXX - Allow some tolerance here? */
476 if (real_bps != bps)
477 return (EINVAL);
478 #endif
479
480 cs->cs_preg[12] = tconst;
481 cs->cs_preg[13] = tconst >> 8;
482
483 /* Caller will stuff the pending registers. */
484 return (0);
485 }
486
487 int
zs_set_modes(struct zs_chanstate * cs,int cflag)488 zs_set_modes(struct zs_chanstate *cs, int cflag)
489 {
490 int s;
491
492 /*
493 * Output hardware flow control on the chip is horrendous:
494 * if carrier detect drops, the receiver is disabled, and if
495 * CTS drops, the transmitter is stopped IN MID CHARACTER!
496 * Therefore, NEVER set the HFC bit, and instead use the
497 * status interrupt to detect CTS changes.
498 */
499 s = splzs();
500 cs->cs_rr0_pps = 0;
501 if ((cflag & (CLOCAL | MDMBUF)) != 0) {
502 cs->cs_rr0_dcd = 0;
503 if ((cflag & MDMBUF) == 0)
504 cs->cs_rr0_pps = ZSRR0_DCD;
505 } else
506 cs->cs_rr0_dcd = ZSRR0_DCD;
507 if ((cflag & CRTSCTS) != 0) {
508 cs->cs_wr5_dtr = ZSWR5_DTR;
509 cs->cs_wr5_rts = ZSWR5_RTS;
510 cs->cs_rr0_cts = ZSRR0_CTS;
511 } else if ((cflag & MDMBUF) != 0) {
512 cs->cs_wr5_dtr = 0;
513 cs->cs_wr5_rts = ZSWR5_DTR;
514 cs->cs_rr0_cts = ZSRR0_DCD;
515 } else {
516 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
517 cs->cs_wr5_rts = 0;
518 cs->cs_rr0_cts = 0;
519 }
520 splx(s);
521
522 /* Caller will stuff the pending registers. */
523 return (0);
524 }
525
526
527 /*
528 * Read or write the chip with suitable delays.
529 */
530
531 uint8_t
zs_read_reg(struct zs_chanstate * cs,uint8_t reg)532 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
533 {
534 uint8_t val;
535 struct zs_channel *zsc = (struct zs_channel *)cs;
536
537 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
538 (ZS_REG_CSR << 2) + 3, reg);
539 ZS_DELAY();
540 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs,
541 (ZS_REG_CSR << 2) + 3);
542 ZS_DELAY();
543 return val;
544 }
545
546 void
zs_write_reg(struct zs_chanstate * cs,uint8_t reg,uint8_t val)547 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
548 {
549 struct zs_channel *zsc = (struct zs_channel *)cs;
550
551 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
552 (ZS_REG_CSR << 2) + 3, reg);
553 ZS_DELAY();
554 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
555 (ZS_REG_CSR << 2) + 3, val);
556 ZS_DELAY();
557 }
558
559 uint8_t
zs_read_csr(struct zs_chanstate * cs)560 zs_read_csr(struct zs_chanstate *cs)
561 {
562 struct zs_channel *zsc = (struct zs_channel *)cs;
563 uint8_t val;
564
565 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs,
566 (ZS_REG_CSR << 2) + 3);
567 ZS_DELAY();
568 return val;
569 }
570
571 void
zs_write_csr(struct zs_chanstate * cs,uint8_t val)572 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
573 {
574 struct zs_channel *zsc = (struct zs_channel *)cs;
575
576 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
577 (ZS_REG_CSR << 2) + 3, val);
578 ZS_DELAY();
579 }
580
581 uint8_t
zs_read_data(struct zs_chanstate * cs)582 zs_read_data(struct zs_chanstate *cs)
583 {
584 struct zs_channel *zsc = (struct zs_channel *)cs;
585 uint8_t val;
586
587 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs,
588 (ZS_REG_DATA << 2) + 3);
589 ZS_DELAY();
590 return val;
591 }
592
593 void
zs_write_data(struct zs_chanstate * cs,uint8_t val)594 zs_write_data(struct zs_chanstate *cs, uint8_t val)
595 {
596 struct zs_channel *zsc = (struct zs_channel *)cs;
597
598 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs,
599 (ZS_REG_DATA << 2) + 3, val);
600 ZS_DELAY();
601 }
602
603 void
zs_abort(struct zs_chanstate * cs)604 zs_abort(struct zs_chanstate *cs)
605 {
606 #if defined(KGDB)
607 zskgdb(cs);
608 #elif defined(DDB)
609 Debugger();
610 #endif
611 }
612
613
614 /*********************************************************/
615 /* Polled character I/O functions for console and KGDB */
616 /*********************************************************/
617
618 struct zschan *
zs_get_chan_addr(int zs_unit,int channel)619 zs_get_chan_addr(int zs_unit, int channel)
620 {
621 static int dumped_addr = 0;
622 struct zsdevice *addr;
623 struct zschan *zc;
624
625 switch (mach_type) {
626 case MACH_SGI_IP12:
627 if (zs_unit == 2 && (mach_subtype == MACH_SGI_IP12_4D_3X ||
628 mach_subtype == MACH_SGI_IP12_VIP12)) {
629 addr = (struct zsdevice *)
630 MIPS_PHYS_TO_KSEG1(0x1fb80d20);
631 break;
632 }
633
634 /* FALLTHROUGH */
635 case MACH_SGI_IP20:
636 if (zs_unit == 0) {
637 addr = (struct zsdevice *)
638 MIPS_PHYS_TO_KSEG1(0x1fb80d00);
639 } else if (zs_unit == 1) {
640 addr = (struct zsdevice *)
641 MIPS_PHYS_TO_KSEG1(0x1fb80d10);
642 } else {
643 panic("zs_get_chan_addr: bad zs_unit %d\n", zs_unit);
644 }
645 break;
646
647 case MACH_SGI_IP22:
648 if (zs_unit != 0)
649 panic("zs_get_chan_addr zs_unit != 0 on IP%d",
650 mach_type);
651
652 addr = (struct zsdevice *) MIPS_PHYS_TO_KSEG1(0x1fbd9830);
653 break;
654
655 default:
656 panic("zs_get_chan_addr: unsupported IP%d", mach_type);
657 }
658
659 /*
660 * We need to swap serial ports to match reality on
661 * non-keyboard channels.
662 */
663 if (mach_type == MACH_SGI_IP22) {
664 if (channel == 0)
665 zc = &addr->zs_chan_b;
666 else
667 zc = &addr->zs_chan_a;
668 } else {
669 if (zs_unit == 0) {
670 if (channel == 0)
671 zc = &addr->zs_chan_a;
672 else
673 zc = &addr->zs_chan_b;
674 } else {
675 if (channel == 0)
676 zc = &addr->zs_chan_b;
677 else
678 zc = &addr->zs_chan_a;
679 }
680 }
681
682 if (dumped_addr == 0) {
683 dumped_addr++;
684 aprint_debug("zs unit %d, channel %d had address %p\n",
685 zs_unit, channel, zc);
686 }
687
688 return (zc);
689 }
690
691 int
zs_getc(void * arg)692 zs_getc(void *arg)
693 {
694 register volatile struct zschan *zc = arg;
695 register int s, c, rr0;
696
697 s = splzs();
698 /* Wait for a character to arrive. */
699 do {
700 rr0 = zc->zc_csr;
701 ZS_DELAY();
702 } while ((rr0 & ZSRR0_RX_READY) == 0);
703
704 c = zc->zc_data;
705 ZS_DELAY();
706 splx(s);
707
708 return (c);
709 }
710
711 /*
712 * Polled output char.
713 */
714 void
zs_putc(void * arg,int c)715 zs_putc(void *arg, int c)
716 {
717 register volatile struct zschan *zc = arg;
718 register int s, rr0;
719
720 s = splzs();
721 /* Wait for transmitter to become ready. */
722 do {
723 rr0 = zc->zc_csr;
724 ZS_DELAY();
725 } while ((rr0 & ZSRR0_TX_READY) == 0);
726
727 zc->zc_data = c;
728 wbflush();
729 ZS_DELAY();
730 splx(s);
731 }
732
733 /***************************************************************/
734 void
zscnprobe(struct consdev * cn)735 zscnprobe(struct consdev *cn)
736 {
737 }
738
739 void
zscninit(struct consdev * cn)740 zscninit(struct consdev *cn)
741 {
742 extern const struct cdevsw zstty_cdevsw;
743 const char* consdev;
744
745 if ((consdev = arcbios_GetEnvironmentVariable("ConsoleOut")) == NULL)
746 panic("zscninit without valid ARCS ConsoleOut setting!");
747
748 if (strlen(consdev) != 9 ||
749 strncmp(consdev, "serial", 6) != 0)
750 panic("zscninit with ARCS console not set to serial!");
751
752 cons_port = consdev[7] - '0';
753
754 #if 0
755 /*
756 * If your IP12 serial console goes missing after consinit(),
757 * try flipping this the other way 'round. If there are some
758 * IP12 machines that actually require this, we'll be in for
759 * a lot of funnies once again...
760 */
761 if (mach_type == MACH_SGI_IP12)
762 cons_port = 1 - cons_port;
763 #endif
764
765 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port);
766 cn->cn_pri = CN_REMOTE;
767
768 /* Mark this unit as the console */
769 zs_consunit = 0;
770
771 /* SGI hardware wires serial port 1 to channel B, port 2 to A */
772 if (cons_port == 0)
773 zs_conschan = 1;
774 else
775 zs_conschan = 0;
776 }
777
778 int
zscngetc(dev_t dev)779 zscngetc(dev_t dev)
780 {
781 struct zschan *zs;
782
783 switch (mach_type) {
784 case MACH_SGI_IP12:
785 case MACH_SGI_IP20:
786 zs = zs_get_chan_addr(1, cons_port);
787 break;
788
789 case MACH_SGI_IP22:
790 default:
791 zs = zs_get_chan_addr(0, cons_port);
792 break;
793 }
794
795 return zs_getc(zs);
796 }
797
798 void
zscnputc(dev_t dev,int c)799 zscnputc(dev_t dev, int c)
800 {
801 struct zschan *zs;
802
803 switch (mach_type) {
804 case MACH_SGI_IP12:
805 case MACH_SGI_IP20:
806 zs = zs_get_chan_addr(1, cons_port);
807 break;
808
809 case MACH_SGI_IP22:
810 default:
811 zs = zs_get_chan_addr(0, cons_port);
812 break;
813 }
814
815 zs_putc(zs, c);
816 }
817
818 void
zscnpollc(dev_t dev,int on)819 zscnpollc(dev_t dev, int on)
820 {
821 }
822