xref: /netbsd-src/sys/arch/powerpc/fpu/fpu_implode.c (revision 8f5a4424de12726e89aef4f82f75ded907f22012)
1 /*	$NetBSD: fpu_implode.c,v 1.24 2022/09/14 05:55:08 rin Exp $ */
2 
3 /*
4  * Copyright (c) 1992, 1993
5  *	The Regents of the University of California.  All rights reserved.
6  *
7  * This software was developed by the Computer Systems Engineering group
8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9  * contributed to Berkeley.
10  *
11  * All advertising materials mentioning features or use of this software
12  * must display the following acknowledgement:
13  *	This product includes software developed by the University of
14  *	California, Lawrence Berkeley Laboratory.
15  *
16  * Redistribution and use in source and binary forms, with or without
17  * modification, are permitted provided that the following conditions
18  * are met:
19  * 1. Redistributions of source code must retain the above copyright
20  *    notice, this list of conditions and the following disclaimer.
21  * 2. Redistributions in binary form must reproduce the above copyright
22  *    notice, this list of conditions and the following disclaimer in the
23  *    documentation and/or other materials provided with the distribution.
24  * 3. Neither the name of the University nor the names of its contributors
25  *    may be used to endorse or promote products derived from this software
26  *    without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  *	@(#)fpu_implode.c	8.1 (Berkeley) 6/11/93
41  */
42 
43 /*
44  * FPU subroutines: `implode' internal format numbers into the machine's
45  * `packed binary' format.
46  */
47 
48 #include <sys/cdefs.h>
49 __KERNEL_RCSID(0, "$NetBSD: fpu_implode.c,v 1.24 2022/09/14 05:55:08 rin Exp $");
50 
51 #include <sys/types.h>
52 #include <sys/systm.h>
53 
54 #include <powerpc/instr.h>
55 #include <machine/fpu.h>
56 #include <machine/ieee.h>
57 #include <machine/reg.h>
58 
59 #include <powerpc/fpu/fpu_arith.h>
60 #include <powerpc/fpu/fpu_emu.h>
61 #include <powerpc/fpu/fpu_extern.h>
62 
63 static int round(struct fpemu *, struct fpn *, int *);
64 static int toinf(struct fpemu *, int);
65 static int round_int(struct fpn *, int *, int, int, int);
66 
67 static u_int fpu_ftoi(struct fpemu *, struct fpn *, int *, int);
68 static uint64_t fpu_ftox(struct fpemu *, struct fpn *, int *, int);
69 static u_int fpu_ftos(struct fpemu *, struct fpn *, int *);
70 static uint64_t fpu_ftod(struct fpemu *, struct fpn *, int *);
71 
72 /*
73  * Round a number (algorithm from Motorola MC68882 manual, modified for
74  * our internal format).  Set inexact exception if rounding is required.
75  * Return true iff we rounded up.
76  *
77  * After rounding, we discard the guard and round bits by shifting right
78  * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
79  * This saves effort later.
80  *
81  * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
82  * responsibility to fix this if necessary.
83  */
84 static int
round(struct fpemu * fe,struct fpn * fp,int * cx)85 round(struct fpemu *fe, struct fpn *fp, int *cx)
86 {
87 	u_int m0, m1, m2, m3;
88 	int gr, s;
89 	FPU_DECL_CARRY;
90 
91 	m0 = fp->fp_mant[0];
92 	m1 = fp->fp_mant[1];
93 	m2 = fp->fp_mant[2];
94 	m3 = fp->fp_mant[3];
95 	gr = m3 & 3;
96 	s = fp->fp_sticky;
97 
98 	/* mant >>= FP_NG */
99 	m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
100 	m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
101 	m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
102 	m0 >>= FP_NG;
103 
104 	if ((gr | s) == 0)	/* result is exact: no rounding needed */
105 		goto rounddown;
106 
107 	*cx |= FPSCR_FI;	/* inexact */
108 
109 	/* Go to rounddown to round down; break to round up. */
110 	switch ((fe->fe_fpscr) & FPSCR_RN) {
111 
112 	case FSR_RD_RN:
113 	default:
114 		/*
115 		 * Round only if guard is set (gr & 2).  If guard is set,
116 		 * but round & sticky both clear, then we want to round
117 		 * but have a tie, so round to even, i.e., add 1 iff odd.
118 		 */
119 		if ((gr & 2) == 0)
120 			goto rounddown;
121 		if ((gr & 1) || fp->fp_sticky || (m3 & 1))
122 			break;
123 		goto rounddown;
124 
125 	case FSR_RD_RZ:
126 		/* Round towards zero, i.e., down. */
127 		goto rounddown;
128 
129 	case FSR_RD_RM:
130 		/* Round towards -Inf: up if negative, down if positive. */
131 		if (fp->fp_sign)
132 			break;
133 		goto rounddown;
134 
135 	case FSR_RD_RP:
136 		/* Round towards +Inf: up if positive, down otherwise. */
137 		if (!fp->fp_sign)
138 			break;
139 		goto rounddown;
140 	}
141 
142 	/* Bump low bit of mantissa, with carry. */
143 	*cx |= FPSCR_FR;
144 
145 	FPU_ADDS(m3, m3, 1);
146 	FPU_ADDCS(m2, m2, 0);
147 	FPU_ADDCS(m1, m1, 0);
148 	FPU_ADDC(m0, m0, 0);
149 	fp->fp_mant[0] = m0;
150 	fp->fp_mant[1] = m1;
151 	fp->fp_mant[2] = m2;
152 	fp->fp_mant[3] = m3;
153 	return (1);
154 
155 rounddown:
156 	fp->fp_mant[0] = m0;
157 	fp->fp_mant[1] = m1;
158 	fp->fp_mant[2] = m2;
159 	fp->fp_mant[3] = m3;
160 	return (0);
161 }
162 
163 /*
164  * For overflow: return true if overflow is to go to +/-Inf, according
165  * to the sign of the overflowing result.  If false, overflow is to go
166  * to the largest magnitude value instead.
167  */
168 static int
toinf(struct fpemu * fe,int sign)169 toinf(struct fpemu *fe, int sign)
170 {
171 	int inf;
172 
173 	/* look at rounding direction */
174 	switch ((fe->fe_fpscr) & FPSCR_RN) {
175 
176 	default:
177 	case FSR_RD_RN:		/* the nearest value is always Inf */
178 		inf = 1;
179 		break;
180 
181 	case FSR_RD_RZ:		/* toward 0 => never towards Inf */
182 		inf = 0;
183 		break;
184 
185 	case FSR_RD_RP:		/* toward +Inf iff positive */
186 		inf = sign == 0;
187 		break;
188 
189 	case FSR_RD_RM:		/* toward -Inf iff negative */
190 		inf = sign;
191 		break;
192 	}
193 	return (inf);
194 }
195 
196 static int
round_int(struct fpn * fp,int * cx,int rn,int sign,int odd)197 round_int(struct fpn *fp, int *cx, int rn, int sign, int odd)
198 {
199 	int g, rs;
200 
201 	g =   fp->fp_mant[3] & 0x80000000;
202 	rs = (fp->fp_mant[3] & 0x7fffffff) | fp->fp_sticky;
203 
204 	if ((g | rs) == 0)
205 		return 0;	/* exact */
206 
207 	*cx |= FPSCR_FI;
208 
209 	switch (rn) {
210 	case FSR_RD_RN:
211 		if (g && (rs | odd))
212 			break;
213 		return 0;
214 	case FSR_RD_RZ:
215 		return 0;
216 	case FSR_RD_RP:
217 		if (!sign)
218 			break;
219 		return 0;
220 	case FSR_RD_RM:
221 		if (sign)
222 			break;
223 		return 0;
224 	}
225 
226 	*cx |= FPSCR_FR;
227 	return 1;
228 }
229 
230 /*
231  * fpn -> int (int value returned as return value).
232  */
233 static u_int
fpu_ftoi(struct fpemu * fe,struct fpn * fp,int * cx,int rn)234 fpu_ftoi(struct fpemu *fe, struct fpn *fp, int *cx, int rn)
235 {
236 	u_int i;
237 	int sign, exp, tmp_cx;
238 
239 	sign = fp->fp_sign;
240 	switch (fp->fp_class) {
241 	case FPC_SNAN:
242 		*cx |= FPSCR_VXSNAN;
243 		/* FALLTHROUGH */
244 	case FPC_QNAN:
245 		sign = 1;
246 		break;
247 
248 	case FPC_ZERO:
249 		return (0);
250 
251 	case FPC_NUM:
252 		/*
253 		 * If exp >= 2^32, overflow.  Otherwise shift value right
254 		 * into last mantissa word (this will not exceed 0xffffffff),
255 		 * shifting any guard and round bits out into the sticky
256 		 * bit.  Then ``round'' towards zero, i.e., just set an
257 		 * inexact exception if sticky is set (see round()).
258 		 * If the result is > 0x80000000, or is positive and equals
259 		 * 0x80000000, overflow; otherwise the last fraction word
260 		 * is the result.
261 		 */
262 		if ((exp = fp->fp_exp) >= 32)
263 			break;
264 		/* NB: the following includes exp < 0 cases */
265 		(void)fpu_shr(fp, FP_NMANT - 32 - 1 - exp);
266 		i = fp->fp_mant[2];
267 		tmp_cx = 0;
268 		i += round_int(fp, &tmp_cx, rn, sign, i & 1);
269 		if (i >= ((u_int)0x80000000 + sign))
270 			break;
271 		*cx |= tmp_cx;
272 		return (sign ? -i : i);
273 
274 	case FPC_INF:
275 		break;
276 	}
277 	/* overflow: replace any inexact exception with invalid */
278 	*cx |= FPSCR_VXCVI;
279 	return (0x7fffffff + sign);
280 }
281 
282 /*
283  * fpn -> extended int (high bits of int value returned as return value).
284  */
285 static uint64_t
fpu_ftox(struct fpemu * fe,struct fpn * fp,int * cx,int rn)286 fpu_ftox(struct fpemu *fe, struct fpn *fp, int *cx, int rn)
287 {
288 	uint64_t i;
289 	int sign, exp, tmp_cx;
290 
291 	sign = fp->fp_sign;
292 	switch (fp->fp_class) {
293 	case FPC_SNAN:
294 		*cx |= FPSCR_VXSNAN;
295 		/* FALLTHROUGH */
296 	case FPC_QNAN:
297 		sign = 1;
298 		break;
299 
300 	case FPC_ZERO:
301 		return (0);
302 
303 	case FPC_NUM:
304 		/*
305 		 * If exp >= 2^64, overflow.  Otherwise shift value right
306 		 * into last mantissa word (this will not exceed 0xffffffffffffffff),
307 		 * shifting any guard and round bits out into the sticky
308 		 * bit.  Then ``round'' towards zero, i.e., just set an
309 		 * inexact exception if sticky is set (see round()).
310 		 * If the result is > 0x8000000000000000, or is positive and equals
311 		 * 0x8000000000000000, overflow; otherwise the last fraction word
312 		 * is the result.
313 		 */
314 		if ((exp = fp->fp_exp) >= 64)
315 			break;
316 		/* NB: the following includes exp < 0 cases */
317 		(void)fpu_shr(fp, FP_NMANT - 32 - 1 - exp);
318 		i = ((uint64_t)fp->fp_mant[1] << 32) | fp->fp_mant[2];
319 		tmp_cx = 0;
320 		i += round_int(fp, &tmp_cx, rn, sign, i & 1);
321 		if (i >= ((uint64_t)0x8000000000000000LL + sign))
322 			break;
323 		*cx |= tmp_cx;
324 		return (sign ? -i : i);
325 
326 	case FPC_INF:
327 		break;
328 	}
329 	/* overflow: replace any inexact exception with invalid */
330 	*cx |= FPSCR_VXCVI;
331 	return (0x7fffffffffffffffLL + sign);
332 }
333 
334 #define	FPRF_SIGN(sign)	((sign) ? FPSCR_FL : FPSCR_FG)
335 
336 /*
337  * fpn -> single (32 bit single returned as return value).
338  * We assume <= 29 bits in a single-precision fraction (1.f part).
339  */
340 static u_int
fpu_ftos(struct fpemu * fe,struct fpn * fp,int * cx)341 fpu_ftos(struct fpemu *fe, struct fpn *fp, int *cx)
342 {
343 	u_int sign = fp->fp_sign << 31;
344 	int exp;
345 
346 #define	SNG_EXP(e)	((e) << SNG_FRACBITS)	/* makes e an exponent */
347 #define	SNG_MASK	(SNG_EXP(1) - 1)	/* mask for fraction */
348 
349 	/* Take care of non-numbers first. */
350 	if (ISNAN(fp)) {
351 		*cx |= FPSCR_C | FPSCR_FU;
352 		/*
353 		 * Preserve upper bits of NaN, per SPARC V8 appendix N.
354 		 * Note that fp->fp_mant[0] has the quiet bit set,
355 		 * even if it is classified as a signalling NaN.
356 		 */
357 		(void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
358 		exp = SNG_EXP_INFNAN;
359 		goto done;
360 	}
361 	if (ISINF(fp)) {
362 		*cx |= FPRF_SIGN(sign) | FPSCR_FU;
363 		return (sign | SNG_EXP(SNG_EXP_INFNAN));
364 	}
365 	if (ISZERO(fp)) {
366 		*cx |= FPSCR_FE;
367 		if (sign)
368 			*cx |= FPSCR_C;
369 		return (sign);
370 	}
371 
372 	/*
373 	 * Normals (including subnormals).  Drop all the fraction bits
374 	 * (including the explicit ``implied'' 1 bit) down into the
375 	 * single-precision range.  If the number is subnormal, move
376 	 * the ``implied'' 1 into the explicit range as well, and shift
377 	 * right to introduce leading zeroes.  Rounding then acts
378 	 * differently for normals and subnormals: the largest subnormal
379 	 * may round to the smallest normal (1.0 x 2^minexp), or may
380 	 * remain subnormal.  In the latter case, signal an underflow
381 	 * if the result was inexact or if underflow traps are enabled.
382 	 *
383 	 * Rounding a normal, on the other hand, always produces another
384 	 * normal (although either way the result might be too big for
385 	 * single precision, and cause an overflow).  If rounding a
386 	 * normal produces 2.0 in the fraction, we need not adjust that
387 	 * fraction at all, since both 1.0 and 2.0 are zero under the
388 	 * fraction mask.
389 	 *
390 	 * Note that the guard and round bits vanish from the number after
391 	 * rounding.
392 	 */
393 	if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) {	/* subnormal */
394 		/* -NG for g,r; -SNG_FRACBITS-exp for fraction */
395 		(void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
396 		if (round(fe, fp, cx) && fp->fp_mant[3] == SNG_EXP(1)) {
397 			*cx |= FPRF_SIGN(sign);
398 			return (sign | SNG_EXP(1) | 0);
399 		}
400 		if (*cx & FPSCR_FI) {
401 			*cx |= FPSCR_UX;
402 			if (fp->fp_mant[3] == 0) {
403 				*cx |= FPSCR_FE;
404 				return sign;
405 			}
406 		}
407 		*cx |= FPSCR_C | FPRF_SIGN(sign);
408 		return (sign | SNG_EXP(0) | fp->fp_mant[3]);
409 	}
410 	/* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
411 	(void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
412 #ifdef DIAGNOSTIC
413 	if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
414 		panic("fpu_ftos");
415 #endif
416 	if (round(fe, fp, cx) && fp->fp_mant[3] == SNG_EXP(2))
417 		exp++;
418 	if (exp >= SNG_EXP_INFNAN) {
419 		*cx |= FPSCR_OX | FPSCR_FI;
420 		/* overflow to inf or to max single */
421 		if (toinf(fe, sign)) {
422 			*cx |= FPRF_SIGN(sign) | FPSCR_FU;
423 			return (sign | SNG_EXP(SNG_EXP_INFNAN));
424 		}
425 		*cx |= FPRF_SIGN(sign);
426 		return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
427 	}
428 	*cx |= FPRF_SIGN(sign);
429 done:
430 	/* phew, made it */
431 	return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
432 }
433 
434 /*
435  * fpn -> double.  Assumes <= 61 bits in double precision fraction.
436  *
437  * This code mimics fpu_ftos; see it for comments.
438  */
439 static uint64_t
fpu_ftod(struct fpemu * fe,struct fpn * fp,int * cx)440 fpu_ftod(struct fpemu *fe, struct fpn *fp, int *cx)
441 {
442 	u_int sign = fp->fp_sign << 31;
443 	int exp;
444 
445 #define	DBL_EXP(e)	((e) << (DBL_FRACBITS & 31))
446 #define	DBL_MASK	(DBL_EXP(1) - 1)
447 #define	HI_WORD(i)	((uint64_t)(i) << 32)
448 #define	LO_WORD(i)	((uint32_t)(i))
449 
450 	if (ISNAN(fp)) {
451 		*cx |= FPSCR_C | FPSCR_FU;
452 		(void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
453 		exp = DBL_EXP_INFNAN;
454 		goto done;
455 	}
456 	if (ISINF(fp)) {
457 		*cx |= FPRF_SIGN(sign) | FPSCR_FU;
458 		return HI_WORD(sign | DBL_EXP(DBL_EXP_INFNAN));
459 	}
460 	if (ISZERO(fp)) {
461 		*cx |= FPSCR_FE;
462 		if (sign)
463 			*cx |= FPSCR_C;
464 		return HI_WORD(sign);
465 	}
466 
467 	if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
468 		(void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
469 		if (round(fe, fp, cx) && fp->fp_mant[2] == DBL_EXP(1)) {
470 			*cx |= FPRF_SIGN(sign);
471 			return HI_WORD(sign | DBL_EXP(1) | 0);
472 		}
473 		if (*cx & FPSCR_FI) {
474 			*cx |= FPSCR_UX;
475 			if ((fp->fp_mant[2] & DBL_MASK) == 0 &&
476 			     fp->fp_mant[3] == 0) {
477 				*cx |= FPSCR_FE;
478 				return HI_WORD(sign);
479 			}
480 		}
481 		*cx |= FPSCR_C | FPRF_SIGN(sign);
482 		exp = 0;
483 		goto done;
484 	}
485 	(void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
486 	if (round(fe, fp, cx) && fp->fp_mant[2] == DBL_EXP(2))
487 		exp++;
488 	if (exp >= DBL_EXP_INFNAN) {
489 		*cx |= FPSCR_OX | FPSCR_FI;
490 		/* overflow to inf or to max double */
491 		if (toinf(fe, sign)) {
492 			*cx |= FPRF_SIGN(sign) | FPSCR_FU;
493 			return HI_WORD(sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
494 		}
495 		*cx |= FPRF_SIGN(sign);
496 		return HI_WORD(sign | DBL_EXP(DBL_EXP_INFNAN - 1) | DBL_MASK) |
497 		       LO_WORD(~0);
498 	}
499 	*cx |= FPRF_SIGN(sign);
500 done:
501 	return HI_WORD(sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)) |
502 	       LO_WORD(fp->fp_mant[3]);
503 }
504 
505 /*
506  * Implode an fpn, writing the result into the given space.
507  */
508 void
fpu_implode(struct fpemu * fe,struct fpn * fp,int type,uint64_t * p)509 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, uint64_t *p)
510 {
511 	u_int *hi, *lo;
512 	int cx, rn;
513 	bool fpscr;
514 
515 	hi = (u_int *)p;
516 	lo = hi + 1;
517 
518 	if (type & FTYPE_RD_RZ)
519 		rn = FSR_RD_RZ;
520 	else
521 		rn = fe->fe_fpscr & FPSCR_RN;
522 	fpscr = type & FTYPE_FPSCR;
523 	type &= ~FTYPE_FLAG_MASK;
524 
525 	cx = 0;
526 	switch (type) {
527 
528 	case FTYPE_LNG:
529 		/* FPRF is undefined. */
530 		*p = fpu_ftox(fe, fp, &cx, rn);
531 		DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n", *hi, *lo));
532 		break;
533 
534 	case FTYPE_INT:
535 		/* FPRF is undefined. */
536 		*hi = 0;
537 		*lo = fpu_ftoi(fe, fp, &cx, rn);
538 		DPRINTF(FPE_REG, ("fpu_implode: int %x\n", *lo));
539 		break;
540 
541 	case FTYPE_SNG:
542 		*hi = fpu_ftos(fe, fp, &cx);
543 		*lo = 0;
544 		DPRINTF(FPE_REG, ("fpu_implode: single %x\n", *hi));
545 		break;
546 
547 	case FTYPE_DBL:
548 		*p = fpu_ftod(fe, fp, &cx);
549 		DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n", *hi, *lo));
550 		break;
551 
552 	default:
553 		panic("fpu_implode: invalid type %d", type);
554 	}
555 
556 	if (fpscr) {
557 		fe->fe_fpscr &= ~(FPSCR_FR | FPSCR_FI | FPSCR_FPRF);
558 		fe->fe_cx |= cx;
559 		if (cx & FPSCR_FI)
560 			fe->fe_cx |= FPSCR_XX;
561 	}
562 }
563