1 /* $NetBSD: timerreg.h,v 1.8 2014/03/31 11:25:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * 16bit timer 0:3 34 * source: BUSCLK, H-BLNK 35 */ 36 37 #define EE_TIMER_MIN 0 38 #define EE_TIMER_MAX 3 39 #define LEGAL_TIMER(x) \ 40 (((x) >= EE_TIMER_MIN) && ((x) <= EE_TIMER_MAX)) 41 42 /* Register address. all registers are 32bit wide */ 43 #define TIMER_REGBASE 0x10000000 44 #define TIMER_REGSIZE 0x2000 45 #define TIMER_OFS 0x800 46 47 #define T_COUNT_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x))) 48 #define T_MODE_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \ 49 TIMER_OFS * (x) + 0x10)) 50 #define T_COMP_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \ 51 TIMER_OFS * (x) + 0x20)) 52 /* 53 * timer0, timer1 have `hold register'. 54 * (save T_COUNT when SBUS interrupt occurred) 55 */ 56 #define T_HOLD_REG(x) (TIMER_REGBASE + TIMER_OFS * (x) + 0x30) 57 58 #define T0_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000000) 59 #define T0_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000010) 60 #define T0_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000020) 61 #define T0_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000030) 62 #define T1_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000800) 63 #define T1_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000810) 64 #define T1_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000820) 65 #define T1_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000830) 66 #define T2_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001000) 67 #define T2_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001010) 68 #define T2_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001020) 69 #define T3_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001800) 70 #define T3_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001810) 71 #define T3_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001820) 72 73 /* 74 * Tn_MODE: mode, status register. 75 */ 76 #define T_MODE_CLKS_MASK 0x3 77 #define T_MODE_CLKS(x) ((x) & T_MODE_CLKS_MASK) 78 #define T_MODE_CLKS_CLR(x) ((x) & ~T_MODE_CLKS_MASK) 79 80 #define T_MODE_CLKS_BUSCLK1 0 /* 150 MHz */ 81 #define T_MODE_CLKS_BUSCLK16 1 /* 150 / 16 */ 82 #define T_MODE_CLKS_BUSCLK256 2 /* 150 / 256 */ 83 #define T_MODE_CLKS_HBLNK 3 /* H-Blank */ 84 85 /* Gate Function Enabled */ 86 #define T_MODE_GATE 0x00000004 87 /* Gate Selection */ 88 #define T_MODE_GATS_VBLNK 0x00000008 89 /* Gate Mode */ 90 #define T_MODE_GATM_MASK 0x3 91 #define T_MODE_GATM_SHIFT 4 92 #define T_MODE_GATM(x) (((x) >> T_MODE_GATM_SHIFT) & T_MODE_GATM_MASK) 93 #define T_MODE_GATM_CLR(x) \ 94 ((x) & ~(T_MODE_GATM_MASK << T_MODE_GATM_SHIFT)) 95 #define T_MODE_GATM_SET(x, val) \ 96 ((x) | (((val) << T_MODE_GATM_SHIFT) & \ 97 (T_MODE_GATM_MASK << T_MODE_GATM_SHIFT))) 98 #define T_MODE_GATM_LOW 0x0 99 #define T_MODE_GATM_POSEDGE 0x1 100 #define T_MODE_GATM_NEGEDGE 0x2 101 #define T_MODE_GATM_EDGE 0x3 102 103 /* Zero Return */ 104 #define T_MODE_ZRET 0x00000040 105 /* Count Up Enable */ 106 #define T_MODE_CUE 0x00000080 107 /* Compare-Interrupt Enable */ 108 #define T_MODE_CMPE 0x00000100 109 /* Overflow-Interrupt Enable */ 110 #define T_MODE_OVFE 0x00000200 111 /* Equal Flag (write clear) */ 112 #define T_MODE_EQUF 0x00000400 113 /* Overflow Flag (write clear) */ 114 #define T_MODE_OVFF 0x00000800 115 116 /* 117 * Tn_COUNT: counter register 118 */ 119 #define T_COUNT_MASK 0x0000ffff 120 #define T_COUNT(x) ((x) & T_COUNT_MASK) 121 122 /* 123 * Tn_COMP: compare register 124 */ 125 #define T_COMP_MASK 0x0000ffff 126 #define T_COMP(x) ((x) & T_COMP_MASK) 127 128 /* 129 * Tn_HOLD: hold register 130 */ 131 #define T_HOLD_MASK 0x0000ffff 132 #define T_HOLD(x) ((x) & T_HOLD_MASK) 133