1 /* $NetBSD: zs.c,v 1.38 2023/02/04 14:38:09 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Zilog Z8530 Dual UART driver (machine-dependent part)
34 *
35 * Runs two serial lines per chip using slave drivers.
36 * Plain tty/async lines use the zs_async slave.
37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
38 */
39
40 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56
41 * and then updated to reflect changes in 1.59
42 * by Darrin B Jewell <jewell@mit.edu> Mon Mar 30 20:24:46 1998
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.38 2023/02/04 14:38:09 tsutsui Exp $");
47
48 #include "opt_ddb.h"
49 #include "opt_kgdb.h"
50 #include "opt_serial.h"
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/conf.h>
55 #include <sys/device.h>
56 #include <sys/file.h>
57 #include <sys/ioctl.h>
58 #include <sys/kernel.h>
59 #include <sys/proc.h>
60 #include <sys/tty.h>
61 #include <sys/time.h>
62 #include <sys/syslog.h>
63 #include <sys/intr.h>
64 #include <sys/cpu.h>
65
66 #include <machine/autoconf.h>
67 #include <machine/psl.h>
68
69 #include <dev/cons.h>
70
71 #include <dev/ic/z8530reg.h>
72 #include <machine/z8530var.h>
73
74 #include <next68k/next68k/isr.h>
75
76 #include <next68k/dev/intiovar.h>
77 #include <next68k/dev/zs_cons.h>
78
79 #include "ioconf.h"
80 #include "zsc.h" /* NZSC */
81
82 #if (NZSC < 0)
83 #error "No serial controllers?"
84 #endif
85
86 /*
87 * Some warts needed by z8530tty.c -
88 * The default parity REALLY needs to be the same as the PROM uses,
89 * or you can not see messages done with printf during boot-up...
90 */
91 int zs_def_cflag = (CREAD | CS8 | HUPCL);
92
93 /*
94 * The NeXT provides a 3.686400 MHz clock to the ZS chips.
95 */
96 #define PCLK (9600 * 384) /* PCLK pin input clock rate */
97
98 #define ZS_DELAY() delay(2)
99
100 /* The layout of this is hardware-dependent (padding, order). */
101 struct zschan {
102 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */
103 uint8_t zc_xxx0;
104 volatile uint8_t zc_data; /* data */
105 uint8_t zc_xxx1;
106 };
107
108 /* Flags from cninit() */
109 static int zs_hwflags[2];
110
111 /* Default speed for each channel */
112 static int zs_defspeed[2] = {
113 9600, /* ttya */
114 9600, /* ttyb */
115 };
116
117 static uint8_t zs_init_reg[16] = {
118 0, /* 0: CMD (reset, etc.) */
119 0, /* 1: No interrupts yet. */
120 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */
121 ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
122 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
123 ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
124 0, /* 6: TXSYNC/SYNCLO */
125 0, /* 7: RXSYNC/SYNCHI */
126 0, /* 8: alias for data port */
127 ZSWR9_MASTER_IE,
128 0, /*10: Misc. TX/RX control bits */
129 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
130 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
131 0, /*13: BAUDHI (default=9600) */
132 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
133 ZSWR15_BREAK_IE,
134 };
135
136 struct zschan *
zs_get_chan_addr(int channel)137 zs_get_chan_addr(int channel)
138 {
139 char *addr;
140 struct zschan *zc;
141
142 addr = (void *)IIOV(NEXT_P_SCC);
143 if (channel == 0) {
144 /* handle the fact the ports are intertwined. */
145 zc = (struct zschan *)(addr + 1);
146 } else {
147 zc = (struct zschan *)(addr);
148 }
149 return (zc);
150 }
151
152
153 /****************************************************************
154 * Autoconfig
155 ****************************************************************/
156
157 /* Definition of the driver for autoconfig. */
158 static int zs_match(device_t, cfdata_t, void *);
159 static void zs_attach(device_t, device_t, void *);
160 static int zs_print(void *, const char *);
161
162 extern int zs_getc(void *);
163 extern void zs_putc(void *, int);
164
165 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
166 zs_match, zs_attach, NULL, NULL);
167
168 static int zs_attached;
169
170 /* Interrupt handlers. */
171 static int zshard(void *);
172
173 static int zs_get_speed(struct zs_chanstate *);
174
175 /*
176 * Is the zs chip present?
177 */
178 static int
zs_match(device_t parent,cfdata_t cf,void * aux)179 zs_match(device_t parent, cfdata_t cf, void *aux)
180 {
181 struct intio_attach_args *ia = aux;
182
183 if (zs_attached)
184 return 0;
185
186 ia->ia_addr = (void *)NEXT_P_SCC;
187
188 return 1;
189 }
190
191 /*
192 * Attach a found zs.
193 *
194 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR
195 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE?
196 */
197 static void
zs_attach(device_t parent,device_t self,void * aux)198 zs_attach(device_t parent, device_t self, void *aux)
199 {
200 struct zsc_softc *zsc = device_private(self);
201 struct zsc_attach_args zsc_args;
202 volatile struct zschan *zc;
203 struct zs_chanstate *cs;
204 int s, channel;
205
206 zs_attached = 1;
207
208 zsc->zsc_dev = self;
209 aprint_normal("\n");
210
211 /*
212 * Initialize software state for each channel.
213 */
214 for (channel = 0; channel < 2; channel++) {
215 zsc_args.channel = channel;
216 zsc_args.hwflags = zs_hwflags[channel];
217 cs = &zsc->zsc_cs_store[channel];
218 zsc->zsc_cs[channel] = cs;
219
220 zs_lock_init(cs);
221 cs->cs_channel = channel;
222 cs->cs_private = NULL;
223 cs->cs_ops = &zsops_null;
224 cs->cs_brg_clk = PCLK / 16;
225
226 zc = zs_get_chan_addr(channel);
227 cs->cs_reg_csr = &zc->zc_csr;
228 cs->cs_reg_data = &zc->zc_data;
229
230 memcpy(cs->cs_creg, zs_init_reg, 16);
231 memcpy(cs->cs_preg, zs_init_reg, 16);
232
233 /* XXX: Get these from the PROM properties! */
234 /* XXX: See the mvme167 code. Better. */
235 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
236 cs->cs_defspeed = zs_get_speed(cs);
237 else
238 cs->cs_defspeed = zs_defspeed[channel];
239 cs->cs_defcflag = zs_def_cflag;
240
241 /* Make these correspond to cs_defcflag (-crtscts) */
242 cs->cs_rr0_dcd = ZSRR0_DCD;
243 cs->cs_rr0_cts = 0;
244 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
245 cs->cs_wr5_rts = 0;
246
247 /*
248 * Clear the master interrupt enable.
249 * The INTENA is common to both channels,
250 * so just do it on the A channel.
251 */
252 if (channel == 0) {
253 zs_write_reg(cs, 9, 0);
254 }
255
256 /*
257 * Look for a child driver for this channel.
258 * The child attach will setup the hardware.
259 */
260 if (!config_found(self, (void *)&zsc_args, zs_print,
261 CFARGS_NONE)) {
262 /* No sub-driver. Just reset it. */
263 uint8_t reset = (channel == 0) ?
264 ZSWR9_A_RESET : ZSWR9_B_RESET;
265 s = splzs();
266 zs_write_reg(cs, 9, reset);
267 splx(s);
268 }
269 }
270
271 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0, NULL);
272 zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
273 (void (*)(void *))zsc_intr_soft, zsc);
274 INTR_ENABLE(NEXT_I_SCC);
275
276 /*
277 * Set the master interrupt enable and interrupt vector.
278 * (common to both channels, do it on A)
279 */
280 cs = zsc->zsc_cs[0];
281 s = splhigh();
282 /* interrupt vector */
283 zs_write_reg(cs, 2, zs_init_reg[2]);
284 /* master interrupt control (enable) */
285 zs_write_reg(cs, 9, zs_init_reg[9]);
286 splx(s);
287 }
288
289 static int
zs_print(void * aux,const char * name)290 zs_print(void *aux, const char *name)
291 {
292 struct zsc_attach_args *args = aux;
293
294 if (name != NULL)
295 aprint_normal("%s: ", name);
296
297 if (args->channel != -1)
298 aprint_normal(" channel %d", args->channel);
299
300 return (UNCONF);
301 }
302
303 static volatile int zssoftpending;
304
305 /*
306 * Our ZS chips all share a common, autovectored interrupt,
307 * so we have to look at all of them on each interrupt.
308 */
309 static int
zshard(void * arg)310 zshard(void *arg)
311 {
312 struct zsc_softc *zsc;
313 int unit, rr3, rval;
314
315 if (!INTR_OCCURRED(NEXT_I_SCC))
316 return 0;
317
318 rval = 0;
319 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
320 zsc = device_lookup_private(&zsc_cd, unit);
321 if (zsc == NULL)
322 continue;
323 rr3 = zsc_intr_hard(zsc);
324 /* Count up the interrupts. */
325 if (rr3) {
326 rval |= rr3;
327 zsc->zsc_intrcnt.ev_count++;
328 }
329 /* We are at splzs here, so no need to lock. */
330 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
331 softint_schedule(zsc->zsc_softintr_cookie);
332 }
333
334 return(1);
335 }
336
337 /*
338 * Compute the current baud rate given a ZS channel.
339 */
340 static int
zs_get_speed(struct zs_chanstate * cs)341 zs_get_speed(struct zs_chanstate *cs)
342 {
343 int tconst;
344
345 tconst = zs_read_reg(cs, 12);
346 tconst |= zs_read_reg(cs, 13) << 8;
347 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
348 }
349
350 /*
351 * MD functions for setting the baud rate and control modes.
352 */
353 int
zs_set_speed(struct zs_chanstate * cs,int bps)354 zs_set_speed(struct zs_chanstate *cs, int bps)
355 {
356 int tconst, real_bps;
357
358 if (bps == 0)
359 return (0);
360
361 #ifdef DIAGNOSTIC
362 if (cs->cs_brg_clk == 0)
363 panic("zs_set_speed");
364 #endif
365
366 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
367 if (tconst < 0)
368 return (EINVAL);
369
370 /* Convert back to make sure we can do it. */
371 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
372
373 /* XXX - Allow some tolerance here? */
374 if (real_bps != bps)
375 return (EINVAL);
376
377 cs->cs_preg[12] = tconst;
378 cs->cs_preg[13] = tconst >> 8;
379
380 /* Caller will stuff the pending registers. */
381 return (0);
382 }
383
384 int
zs_set_modes(struct zs_chanstate * cs,int cflag)385 zs_set_modes(struct zs_chanstate *cs, int cflag)
386 {
387 int s;
388
389 /*
390 * Output hardware flow control on the chip is horrendous:
391 * if carrier detect drops, the receiver is disabled, and if
392 * CTS drops, the transmitter is stopped IN MID CHARACTER!
393 * Therefore, NEVER set the HFC bit, and instead use the
394 * status interrupt to detect CTS changes.
395 */
396 s = splzs();
397 cs->cs_rr0_pps = 0;
398 if ((cflag & (CLOCAL | MDMBUF)) != 0) {
399 cs->cs_rr0_dcd = 0;
400 if ((cflag & MDMBUF) == 0)
401 cs->cs_rr0_pps = ZSRR0_DCD;
402 } else
403 cs->cs_rr0_dcd = ZSRR0_DCD;
404 if ((cflag & CRTSCTS) != 0) {
405 cs->cs_wr5_dtr = ZSWR5_DTR;
406 cs->cs_wr5_rts = ZSWR5_RTS;
407 cs->cs_rr0_cts = ZSRR0_CTS;
408 } else if ((cflag & CDTRCTS) != 0) {
409 cs->cs_wr5_dtr = 0;
410 cs->cs_wr5_rts = ZSWR5_DTR;
411 cs->cs_rr0_cts = ZSRR0_CTS;
412 } else if ((cflag & MDMBUF) != 0) {
413 cs->cs_wr5_dtr = 0;
414 cs->cs_wr5_rts = ZSWR5_DTR;
415 cs->cs_rr0_cts = ZSRR0_DCD;
416 } else {
417 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
418 cs->cs_wr5_rts = 0;
419 cs->cs_rr0_cts = 0;
420 }
421 splx(s);
422
423 /* Caller will stuff the pending registers. */
424 return (0);
425 }
426
427 /*
428 * Read or write the chip with suitable delays.
429 */
430
431 uint8_t
zs_read_reg(struct zs_chanstate * cs,uint8_t reg)432 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
433 {
434 uint8_t val;
435
436 *cs->cs_reg_csr = reg;
437 ZS_DELAY();
438 val = *cs->cs_reg_csr;
439 ZS_DELAY();
440 return (val);
441 }
442
443 void
zs_write_reg(struct zs_chanstate * cs,uint8_t reg,uint8_t val)444 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
445 {
446 *cs->cs_reg_csr = reg;
447 ZS_DELAY();
448 *cs->cs_reg_csr = val;
449 ZS_DELAY();
450 }
451
452 uint8_t
zs_read_csr(struct zs_chanstate * cs)453 zs_read_csr(struct zs_chanstate *cs)
454 {
455 uint8_t val;
456
457 val = *cs->cs_reg_csr;
458 ZS_DELAY();
459 return (val);
460 }
461
462 void
zs_write_csr(struct zs_chanstate * cs,uint8_t val)463 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
464 {
465 *cs->cs_reg_csr = val;
466 ZS_DELAY();
467 }
468
469 uint8_t
zs_read_data(struct zs_chanstate * cs)470 zs_read_data(struct zs_chanstate *cs)
471 {
472 uint8_t val;
473
474 val = *cs->cs_reg_data;
475 ZS_DELAY();
476 return (val);
477 }
478
479 void
zs_write_data(struct zs_chanstate * cs,uint8_t val)480 zs_write_data(struct zs_chanstate *cs, uint8_t val)
481 {
482 *cs->cs_reg_data = val;
483 ZS_DELAY();
484 }
485
486 /****************************************************************
487 * Console support functions (Sun specific!)
488 * Note: this code is allowed to know about the layout of
489 * the chip registers, and uses that to keep things simple.
490 * XXX - I think I like the mvme167 code better. -gwr
491 ****************************************************************/
492
493 extern void Debugger(void);
494 void *zs_conschan;
495 int zs_consunit = 0;
496
497 /*
498 * Handle user request to enter kernel debugger.
499 */
500 void
zs_abort(struct zs_chanstate * cs)501 zs_abort(struct zs_chanstate *cs)
502 {
503 #if defined(ZS_CONSOLE_ABORT)
504 volatile struct zschan *zc = zs_conschan;
505 int rr0;
506
507 /* Wait for end of break to avoid PROM abort. */
508 /* XXX - Limit the wait? */
509 do {
510 rr0 = zc->zc_csr;
511 ZS_DELAY();
512 } while (rr0 & ZSRR0_BREAK);
513
514 #if defined(KGDB)
515 zskgdb(cs);
516 #elif defined(DDB)
517 Debugger();
518 #else
519 /* XXX eventually, drop into next rom monitor here */
520 printf("stopping on keyboard abort not supported without DDB or KGDB\n");
521 #endif
522 #else /* !ZS_CONSOLE_ABORT */
523 return;
524 #endif
525 }
526
527 /*
528 * Polled input char.
529 */
530 int
zs_getc(void * arg)531 zs_getc(void *arg)
532 {
533 volatile struct zschan *zc = arg;
534 int s, c, rr0;
535
536 s = splhigh();
537 /* Wait for a character to arrive. */
538 do {
539 rr0 = zc->zc_csr;
540 ZS_DELAY();
541 } while ((rr0 & ZSRR0_RX_READY) == 0);
542
543 c = zc->zc_data;
544 ZS_DELAY();
545 splx(s);
546
547 /*
548 * This is used by the kd driver to read scan codes,
549 * so don't translate '\r' ==> '\n' here...
550 */
551 return (c);
552 }
553
554 /*
555 * Polled output char.
556 */
557 void
zs_putc(void * arg,int c)558 zs_putc(void *arg, int c)
559 {
560 volatile struct zschan *zc = arg;
561 int s, rr0;
562
563 s = splhigh();
564 /* Wait for transmitter to become ready. */
565 do {
566 rr0 = zc->zc_csr;
567 ZS_DELAY();
568 } while ((rr0 & ZSRR0_TX_READY) == 0);
569
570
571 zc->zc_data = c;
572 ZS_DELAY();
573
574 splx(s);
575 }
576
577 /*****************************************************************/
578
579 void zscninit(struct consdev *);
580 int zscngetc(dev_t);
581 void zscnputc(dev_t, int);
582 void zscnprobe(struct consdev *);
583
584 void
zscnprobe(struct consdev * cp)585 zscnprobe(struct consdev *cp)
586 {
587 extern const struct cdevsw zstty_cdevsw;
588 int maj;
589
590 maj = cdevsw_lookup_major(&zstty_cdevsw);
591 if (maj != -1) {
592 #ifdef SERCONSOLE
593 cp->cn_pri = CN_REMOTE;
594 #else
595 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */
596 #endif
597 zs_consunit = 0;
598 cp->cn_dev = makedev(maj, zs_consunit);
599 zs_conschan = zs_get_chan_addr(zs_consunit);
600 } else {
601 cp->cn_pri = CN_DEAD;
602 }
603 }
604
605 void
zscninit(struct consdev * cn)606 zscninit(struct consdev *cn)
607 {
608 struct zs_chanstate xcs;
609 struct zs_chanstate *cs;
610 volatile struct zschan *zc;
611 int tconst, s;
612
613 zs_hwflags[zs_consunit] = ZS_HWFLAG_CONSOLE;
614
615 /* Setup temporary chanstate. */
616 memset(&xcs, 0, sizeof(xcs));
617 cs = &xcs;
618 zc = zs_conschan;
619 cs->cs_reg_csr = &zc->zc_csr;
620 cs->cs_reg_data = &zc->zc_data;
621 cs->cs_channel = zs_consunit;
622 cs->cs_brg_clk = PCLK / 16;
623
624 memcpy(cs->cs_preg, zs_init_reg, 16);
625 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
626 cs->cs_preg[15] = ZSWR15_BREAK_IE;
627
628 tconst = BPS_TO_TCONST(cs->cs_brg_clk, zs_defspeed[zs_consunit]);
629 cs->cs_preg[12] = tconst;
630 cs->cs_preg[13] = tconst >> 8;
631
632 /*
633 * can't use zs_set_speed as we haven't set up the
634 * signal sources, and it's not worth it for now
635 */
636
637 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE;
638 /* no interrupts until later, after attach. */
639
640 s = splhigh();
641 zs_loadchannelregs(cs);
642 splx(s);
643
644 printf("\nNetBSD/next68k console\n");
645 }
646
647 /*
648 * Polled console input putchar.
649 */
650 int
zscngetc(dev_t dev)651 zscngetc(dev_t dev)
652 {
653 return (zs_getc(zs_conschan));
654 }
655
656 /*
657 * Polled console output putchar.
658 */
659 void
zscnputc(dev_t dev,int c)660 zscnputc(dev_t dev, int c)
661 {
662 zs_putc(zs_conschan, c);
663 }
664
665 /*****************************************************************/
666