1 /* $NetBSD: rmixl_pcie.c,v 1.16 2021/08/07 16:18:59 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2001 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * PCI configuration support for RMI XLS SoC
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: rmixl_pcie.c,v 1.16 2021/08/07 16:18:59 thorpej Exp $");
44
45 #include "opt_pci.h"
46 #include "pci.h"
47
48 #include <sys/cdefs.h>
49
50 #include <sys/param.h>
51 #include <sys/bus.h>
52 #include <sys/cpu.h>
53 #include <sys/device.h>
54 #include <sys/extent.h>
55 #include <sys/intr.h>
56 #include <sys/kernel.h> /* for 'hz' */
57 #include <sys/malloc.h>
58 #include <sys/systm.h>
59
60 #include <uvm/uvm_extern.h>
61
62 #include <mips/rmi/rmixlreg.h>
63 #include <mips/rmi/rmixlvar.h>
64 #include <mips/rmi/rmixl_intr.h>
65 #include <mips/rmi/rmixl_pcievar.h>
66
67 #include <mips/rmi/rmixl_obiovar.h>
68
69 #include <dev/pci/pcivar.h>
70 #include <dev/pci/pcidevs.h>
71 #include <dev/pci/pciconf.h>
72
73 #ifdef PCI_NETBSD_CONFIGURE
74 #include <mips/cache.h>
75 #endif
76
77 #ifdef PCI_DEBUG
78 int rmixl_pcie_debug = PCI_DEBUG;
79 # define DPRINTF(x) do { if (rmixl_pcie_debug) printf x ; } while (0)
80 #else
81 # define DPRINTF(x)
82 #endif
83
84 #ifndef DDB
85 # define STATIC static
86 #else
87 # define STATIC
88 #endif
89
90
91 /*
92 * XLS PCIe Extended Configuration Registers
93 */
94 #define RMIXL_PCIE_ECFG_UESR 0x104 /* Uncorrectable Error Status Reg */
95 #define RMIXL_PCIE_ECFG_UEMR 0x108 /* Uncorrectable Error Mask Reg */
96 #define RMIXL_PCIE_ECFG_UEVR 0x10c /* Uncorrectable Error seVerity Reg */
97 #define PCIE_ECFG_UEVR_DFLT \
98 (__BITS(18,17) | __BIT(31) | __BITS(5,4) | __BIT(0))
99 #define PCIE_ECFG_UExR_RESV (__BITS(31,21) | __BITS(11,6) | __BITS(3,1))
100 #define RMIXL_PCIE_ECFG_CESR 0x110 /* Correctable Error Status Reg */
101 #define RMIXL_PCIE_ECFG_CEMR 0x114 /* Correctable Error Mask Reg */
102 #define PCIE_ECFG_CExR_RESV (__BITS(31,14) | __BITS(11,9) | __BITS(5,1))
103 #define RMIXL_PCIE_ECFG_ACCR 0x118 /* Adv. Capabilities Control Reg */
104 #define RMIXL_PCIE_ECFG_HLRn(n) (0x11c + ((n) * 4)) /* Header Log Regs */
105 #define RMIXL_PCIE_ECFG_RECR 0x12c /* Root Error Command Reg */
106 #define PCIE_ECFG_RECR_RESV __BITS(31,3)
107 #define RMIXL_PCIE_ECFG_RESR 0x130 /* Root Error Status Reg */
108 #define PCIE_ECFG_RESR_RESV __BITS(26,7)
109 #define RMIXL_PCIE_ECFG_ESI 0x134 /* Error Source Identification Reg */
110 #define RMIXL_PCIE_ECFG_DSNCR 0x140 /* Dev Serial Number Capability Regs */
111
112 static const struct {
113 u_int offset;
114 u_int32_t rw1c;
115 } pcie_ecfg_errs_tab[] = {
116 { RMIXL_PCIE_ECFG_UESR, (__BITS(20,12) | __BIT(4)) },
117 { RMIXL_PCIE_ECFG_CESR, (__BITS(20,12) | __BIT(4)) },
118 { RMIXL_PCIE_ECFG_HLRn(0), 0 },
119 { RMIXL_PCIE_ECFG_HLRn(1), 0 },
120 { RMIXL_PCIE_ECFG_HLRn(2), 0 },
121 { RMIXL_PCIE_ECFG_HLRn(3), 0 },
122 { RMIXL_PCIE_ECFG_RESR, __BITS(6,0) },
123 { RMIXL_PCIE_ECFG_ESI, 0 },
124 };
125 #define PCIE_ECFG_ERRS_OFFTAB_NENTRIES \
126 (sizeof(pcie_ecfg_errs_tab)/sizeof(pcie_ecfg_errs_tab[0]))
127
128 typedef struct rmixl_pcie_int_csr {
129 uint r0;
130 uint r1;
131 } rmixl_pcie_int_csr_t;
132
133 static const rmixl_pcie_int_csr_t int_enb_offset[4] = {
134 { RMIXL_PCIE_LINK0_INT_ENABLE0, RMIXL_PCIE_LINK0_INT_ENABLE1 },
135 { RMIXL_PCIE_LINK1_INT_ENABLE0, RMIXL_PCIE_LINK1_INT_ENABLE1 },
136 { RMIXL_PCIE_LINK2_INT_ENABLE0, RMIXL_PCIE_LINK2_INT_ENABLE1 },
137 { RMIXL_PCIE_LINK3_INT_ENABLE0, RMIXL_PCIE_LINK3_INT_ENABLE1 },
138 };
139
140 static const rmixl_pcie_int_csr_t int_sts_offset[4] = {
141 { RMIXL_PCIE_LINK0_INT_STATUS0, RMIXL_PCIE_LINK0_INT_STATUS1 },
142 { RMIXL_PCIE_LINK1_INT_STATUS0, RMIXL_PCIE_LINK1_INT_STATUS1 },
143 { RMIXL_PCIE_LINK2_INT_STATUS0, RMIXL_PCIE_LINK2_INT_STATUS1 },
144 { RMIXL_PCIE_LINK3_INT_STATUS0, RMIXL_PCIE_LINK3_INT_STATUS1 },
145 };
146
147 static const u_int msi_enb_offset[4] = {
148 RMIXL_PCIE_LINK0_MSI_ENABLE,
149 RMIXL_PCIE_LINK1_MSI_ENABLE,
150 RMIXL_PCIE_LINK2_MSI_ENABLE,
151 RMIXL_PCIE_LINK3_MSI_ENABLE
152 };
153
154 #define RMIXL_PCIE_LINK_STATUS0_ERRORS __BITS(6,4)
155 #define RMIXL_PCIE_LINK_STATUS1_ERRORS __BITS(10,0)
156 #define RMIXL_PCIE_LINK_STATUS_ERRORS \
157 ((((uint64_t)RMIXL_PCIE_LINK_STATUS1_ERRORS) << 32) | \
158 (uint64_t)RMIXL_PCIE_LINK_STATUS0_ERRORS)
159
160 #define RMIXL_PCIE_EVCNT(sc, link, bitno, cpu) \
161 &(sc)->sc_evcnts[link][(bitno) * (ncpu) + (cpu)]
162
163 static int rmixl_pcie_match(device_t, cfdata_t, void *);
164 static void rmixl_pcie_attach(device_t, device_t, void *);
165 static void rmixl_pcie_init(struct rmixl_pcie_softc *);
166 static void rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *);
167 static void rmixl_pcie_attach_hook(device_t, device_t,
168 struct pcibus_attach_args *);
169 static void rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *, uint32_t);
170 static void rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *, uint32_t);
171 static void rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *, uint32_t);
172 static void rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *, uint32_t);
173 static void rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *);
174 static void rmixl_pcie_intcfg(struct rmixl_pcie_softc *);
175 static void rmixl_pcie_errata(struct rmixl_pcie_softc *);
176 static void rmixl_conf_interrupt(void *, int, int, int, int, int *);
177 static int rmixl_pcie_bus_maxdevs(void *, int);
178 static pcitag_t rmixl_tag_to_ecfg(pcitag_t);
179 static pcitag_t rmixl_pcie_make_tag(void *, int, int, int);
180 static void rmixl_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *);
181 void rmixl_pcie_tag_print(const char *restrict, void *, pcitag_t, int, vaddr_t, u_long);
182 static int rmixl_pcie_conf_setup(struct rmixl_pcie_softc *,
183 pcitag_t, int *, bus_space_tag_t *,
184 bus_space_handle_t *);
185 static pcireg_t rmixl_pcie_conf_read(void *, pcitag_t, int);
186 static void rmixl_pcie_conf_write(void *, pcitag_t, int, pcireg_t);
187
188 static int rmixl_pcie_intr_map(const struct pci_attach_args *,
189 pci_intr_handle_t *);
190 static const char *
191 rmixl_pcie_intr_string(void *, pci_intr_handle_t, char *,
192 size_t);
193 static const struct evcnt *
194 rmixl_pcie_intr_evcnt(void *, pci_intr_handle_t);
195 static pci_intr_handle_t
196 rmixl_pcie_make_pih(u_int, u_int, u_int);
197 static void rmixl_pcie_decompose_pih(pci_intr_handle_t, u_int *, u_int *, u_int *);
198 static void rmixl_pcie_intr_disestablish(void *, void *);
199 static void *rmixl_pcie_intr_establish(void *, pci_intr_handle_t,
200 int, int (*)(void *), void *);
201 static rmixl_pcie_link_intr_t *
202 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *, u_int, int, int);
203 static void rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *);
204 static void rmixl_pcie_lip_free(void *);
205 static int rmixl_pcie_intr(void *);
206 static void rmixl_pcie_link_error_intr(u_int, uint32_t, uint32_t);
207 #if defined(DEBUG) || defined(DDB)
208 int rmixl_pcie_error_check(void);
209 #endif
210 static int _rmixl_pcie_error_check(void *);
211 static int rmixl_pcie_error_intr(void *);
212
213
214 #define RMIXL_PCIE_CONCAT3(a,b,c) a ## b ## c
215 #define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \
216 struct extent *ext = rmixl_configuration.rc_phys_ex; \
217 u_long region_start; \
218 uint64_t ba; \
219 int err; \
220 \
221 err = extent_alloc(ext, (size), (align), 0UL, EX_NOWAIT, \
222 ®ion_start); \
223 if (err != 0) \
224 panic("%s: extent_alloc(%p, %#lx, %#lx, %#lx, %#x, %p)",\
225 __func__, ext, size, align, 0UL, EX_NOWAIT, \
226 ®ion_start); \
227 ba = (uint64_t)region_start; \
228 ba *= (1024 * 1024); \
229 bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \
230 DPRINTF(("PCIE %s BAR was not enabled by firmware\n" \
231 "enabling %s at phys %#" PRIxBUSADDR ", size %lu MB\n", \
232 __STRING(reg), __STRING(reg), ba, size)); \
233 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_BRIDGE + \
234 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR), bar); \
235 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + \
236 RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR)); \
237 DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \
238 }
239
240
241 #if defined(DEBUG) || defined(DDB)
242 static void *rmixl_pcie_v;
243 #endif
244
245 CFATTACH_DECL_NEW(rmixl_pcie, sizeof(struct rmixl_pcie_softc),
246 rmixl_pcie_match, rmixl_pcie_attach, NULL, NULL);
247
248 static int rmixl_pcie_found;
249
250 static int
rmixl_pcie_match(device_t parent,cfdata_t cf,void * aux)251 rmixl_pcie_match(device_t parent, cfdata_t cf, void *aux)
252 {
253 uint32_t r;
254
255 /*
256 * PCIe interface exists on XLS chips only
257 */
258 if (! cpu_rmixls(mips_options.mips_cpu))
259 return 0;
260
261 /* XXX
262 * for now there is only one PCIe Interface on chip
263 * this could change with furture RMI XL family designs
264 */
265 if (rmixl_pcie_found)
266 return 0;
267
268 /* read GPIO Reset Configuration register */
269 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG);
270 r >>= 26;
271 r &= 3;
272 if (r != 0)
273 return 0; /* strapped for SRIO */
274
275 return 1;
276 }
277
278 static void
rmixl_pcie_attach(device_t parent,device_t self,void * aux)279 rmixl_pcie_attach(device_t parent, device_t self, void *aux)
280 {
281 struct rmixl_pcie_softc *sc = device_private(self);
282 struct obio_attach_args *obio = aux;
283 struct rmixl_config *rcp = &rmixl_configuration;
284 struct pcibus_attach_args pba;
285 uint32_t bar;
286
287 rmixl_pcie_found = 1;
288 sc->sc_dev = self;
289
290 aprint_normal(" RMI XLS PCIe Interface\n");
291
292 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_HIGH);
293
294 rmixl_pcie_lnkcfg(sc);
295
296 rmixl_pcie_intcfg(sc);
297
298 rmixl_pcie_errata(sc);
299
300 sc->sc_29bit_dmat = obio->obio_29bit_dmat;
301 sc->sc_32bit_dmat = obio->obio_32bit_dmat;
302 sc->sc_64bit_dmat = obio->obio_64bit_dmat;
303
304 sc->sc_tmsk = obio->obio_tmsk;
305
306 /*
307 * get PCI config space base addr from SBC PCIe CFG BAR
308 * initialize it if necessary
309 */
310 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_CFG_BAR);
311 DPRINTF(("%s: PCIE_CFG_BAR %#x\n", __func__, bar));
312 if ((bar & RMIXL_PCIE_CFG_BAR_ENB) == 0) {
313 u_long n = RMIXL_PCIE_CFG_SIZE / (1024 * 1024);
314 RMIXL_PCIE_BAR_INIT(CFG, bar, n, n);
315 }
316 rcp->rc_pci_cfg_pbase = (bus_addr_t)RMIXL_PCIE_CFG_BAR_TO_BA(bar);
317 rcp->rc_pci_cfg_size = (bus_size_t)RMIXL_PCIE_CFG_SIZE;
318
319 /*
320 * get PCIE Extended config space base addr from SBC PCIe ECFG BAR
321 * initialize it if necessary
322 */
323 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_ECFG_BAR);
324 DPRINTF(("%s: PCIE_ECFG_BAR %#x\n", __func__, bar));
325 if ((bar & RMIXL_PCIE_ECFG_BAR_ENB) == 0) {
326 u_long n = RMIXL_PCIE_ECFG_SIZE / (1024 * 1024);
327 RMIXL_PCIE_BAR_INIT(ECFG, bar, n, n);
328 }
329 rcp->rc_pci_ecfg_pbase = (bus_addr_t)RMIXL_PCIE_ECFG_BAR_TO_BA(bar);
330 rcp->rc_pci_ecfg_size = (bus_size_t)RMIXL_PCIE_ECFG_SIZE;
331
332 /*
333 * get PCI MEM space base [addr, size] from SBC PCIe MEM BAR
334 * initialize it if necessary
335 */
336 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_MEM_BAR);
337 DPRINTF(("%s: PCIE_MEM_BAR %#x\n", __func__, bar));
338 if ((bar & RMIXL_PCIE_MEM_BAR_ENB) == 0) {
339 u_long n = 256; /* 256 MB */
340 RMIXL_PCIE_BAR_INIT(MEM, bar, n, n);
341 }
342 rcp->rc_pci_mem_pbase = (bus_addr_t)RMIXL_PCIE_MEM_BAR_TO_BA(bar);
343 rcp->rc_pci_mem_size = (bus_size_t)RMIXL_PCIE_MEM_BAR_TO_SIZE(bar);
344
345 /*
346 * get PCI IO space base [addr, size] from SBC PCIe IO BAR
347 * initialize it if necessary
348 */
349 bar = RMIXL_IOREG_READ(RMIXL_IO_DEV_BRIDGE + RMIXLS_SBC_PCIE_IO_BAR);
350 DPRINTF(("%s: PCIE_IO_BAR %#x\n", __func__, bar));
351 if ((bar & RMIXL_PCIE_IO_BAR_ENB) == 0) {
352 u_long n = 32; /* 32 MB */
353 RMIXL_PCIE_BAR_INIT(IO, bar, n, n);
354 }
355 rcp->rc_pci_io_pbase = (bus_addr_t)RMIXL_PCIE_IO_BAR_TO_BA(bar);
356 rcp->rc_pci_io_size = (bus_size_t)RMIXL_PCIE_IO_BAR_TO_SIZE(bar);
357
358 /*
359 * initialize the PCI CFG, ECFG bus space tags
360 */
361 rmixl_pci_cfg_bus_mem_init(&rcp->rc_pci_cfg_memt, rcp);
362 sc->sc_pci_cfg_memt = &rcp->rc_pci_cfg_memt;
363
364 rmixl_pci_ecfg_bus_mem_init(&rcp->rc_pci_ecfg_memt, rcp);
365 sc->sc_pci_ecfg_memt = &rcp->rc_pci_ecfg_memt;
366
367 /*
368 * initialize the PCI MEM and IO bus space tags
369 */
370 rmixl_pci_bus_mem_init(&rcp->rc_pci_memt, rcp);
371 rmixl_pci_bus_io_init(&rcp->rc_pci_iot, rcp);
372
373 /*
374 * initialize the extended configuration regs
375 */
376 rmixl_pcie_init_ecfg(sc);
377
378 /*
379 * initialize the PCI chipset tag
380 */
381 rmixl_pcie_init(sc);
382
383 /*
384 * attach the PCI bus
385 */
386 memset(&pba, 0, sizeof(pba));
387 pba.pba_memt = &rcp->rc_pci_memt;
388 pba.pba_iot = &rcp->rc_pci_iot;
389 pba.pba_dmat = sc->sc_32bit_dmat;
390 pba.pba_dmat64 = sc->sc_64bit_dmat;
391 pba.pba_pc = &sc->sc_pci_chipset;
392 pba.pba_bus = 0;
393 pba.pba_bridgetag = NULL;
394 pba.pba_intrswiz = 0;
395 pba.pba_intrtag = 0;
396 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
397 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
398
399 config_found(self, &pba, pcibusprint, CFARGS_NONE);
400 }
401
402 /*
403 * rmixl_pcie_lnkcfg_4xx - link configs for XLS4xx and XLS6xx
404 * use IO_AD[11] and IO_AD[10], observable in
405 * Bits[21:20] of the GPIO Reset Configuration register
406 */
407 static void
rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t * ltp,uint32_t grcr)408 rmixl_pcie_lnkcfg_4xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr)
409 {
410 u_int index;
411 static const rmixl_pcie_lnkcfg_t lnktab_4xx[4][4] = {
412 {{ LCFG_EP, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}},
413 {{ LCFG_RC, 4}, {LCFG_NO, 0}, {LCFG_NO, 0}, {LCFG_NO, 0}},
414 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}},
415 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}},
416 };
417 static const char *lnkstr_4xx[4] = {
418 "1EPx4",
419 "1RCx4",
420 "1EPx1, 3RCx1",
421 "4RCx1"
422 };
423 index = (grcr >> 20) & 3;
424 ltp->ncfgs = 4;
425 ltp->cfg = lnktab_4xx[index];
426 ltp->str = lnkstr_4xx[index];
427 }
428
429 /*
430 * rmixl_pcie_lnkcfg_408Lite - link configs for XLS408Lite and XLS04A
431 * use IO_AD[11] and IO_AD[10], observable in
432 * Bits[21:20] of the GPIO Reset Configuration register
433 */
434 static void
rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t * ltp,uint32_t grcr)435 rmixl_pcie_lnkcfg_408Lite(rmixl_pcie_lnktab_t *ltp, uint32_t grcr)
436 {
437 u_int index;
438 static const rmixl_pcie_lnkcfg_t lnktab_408Lite[4][2] = {
439 {{ LCFG_EP, 4}, {LCFG_NO, 0}},
440 {{ LCFG_RC, 4}, {LCFG_NO, 0}},
441 {{ LCFG_EP, 1}, {LCFG_RC, 1}},
442 {{ LCFG_RC, 1}, {LCFG_RC, 1}},
443 };
444 static const char *lnkstr_408Lite[4] = {
445 "4EPx4",
446 "1RCx4",
447 "1EPx1, 1RCx1",
448 "2RCx1"
449 };
450
451 index = (grcr >> 20) & 3;
452 ltp->ncfgs = 2;
453 ltp->cfg = lnktab_408Lite[index];
454 ltp->str = lnkstr_408Lite[index];
455 }
456
457 /*
458 * rmixl_pcie_lnkcfg_2xx - link configs for XLS2xx
459 * use IO_AD[10], observable in Bit[20] of the
460 * GPIO Reset Configuration register
461 */
462 static void
rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t * ltp,uint32_t grcr)463 rmixl_pcie_lnkcfg_2xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr)
464 {
465 u_int index;
466 static const rmixl_pcie_lnkcfg_t lnktab_2xx[2][4] = {
467 {{ LCFG_EP, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}},
468 {{ LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}, {LCFG_RC, 1}}
469 };
470 static const char *lnkstr_2xx[2] = {
471 "1EPx1, 3RCx1",
472 "4RCx1",
473 };
474
475 index = (grcr >> 20) & 1;
476 ltp->ncfgs = 4;
477 ltp->cfg = lnktab_2xx[index];
478 ltp->str = lnkstr_2xx[index];
479 }
480
481 /*
482 * rmixl_pcie_lnkcfg_1xx - link configs for XLS1xx
483 * use IO_AD[10], observable in Bit[20] of the
484 * GPIO Reset Configuration register
485 */
486 static void
rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t * ltp,uint32_t grcr)487 rmixl_pcie_lnkcfg_1xx(rmixl_pcie_lnktab_t *ltp, uint32_t grcr)
488 {
489 u_int index;
490 static const rmixl_pcie_lnkcfg_t lnktab_1xx[2][2] = {
491 {{ LCFG_EP, 1}, {LCFG_RC, 1}},
492 {{ LCFG_RC, 1}, {LCFG_RC, 1}}
493 };
494 static const char *lnkstr_1xx[2] = {
495 "1EPx1, 1RCx1",
496 "2RCx1",
497 };
498
499 index = (grcr >> 20) & 1;
500 ltp->ncfgs = 2;
501 ltp->cfg = lnktab_1xx[index];
502 ltp->str = lnkstr_1xx[index];
503 }
504
505 /*
506 * rmixl_pcie_lnkcfg - determine PCI Express Link Configuration
507 */
508 static void
rmixl_pcie_lnkcfg(struct rmixl_pcie_softc * sc)509 rmixl_pcie_lnkcfg(struct rmixl_pcie_softc *sc)
510 {
511 uint32_t r;
512
513 /* read GPIO Reset Configuration register */
514 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG);
515 DPRINTF(("%s: GPIO RCR %#x\n", __func__, r));
516
517 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
518 case MIPS_XLS104:
519 case MIPS_XLS108:
520 rmixl_pcie_lnkcfg_1xx(&sc->sc_pcie_lnktab, r);
521 break;
522 case MIPS_XLS204:
523 case MIPS_XLS208:
524 rmixl_pcie_lnkcfg_2xx(&sc->sc_pcie_lnktab, r);
525 break;
526 case MIPS_XLS404LITE:
527 case MIPS_XLS408LITE:
528 rmixl_pcie_lnkcfg_408Lite(&sc->sc_pcie_lnktab, r);
529 break;
530 case MIPS_XLS404:
531 case MIPS_XLS408:
532 case MIPS_XLS416:
533 case MIPS_XLS608:
534 case MIPS_XLS616:
535 /* 6xx uses same table as 4xx */
536 rmixl_pcie_lnkcfg_4xx(&sc->sc_pcie_lnktab, r);
537 break;
538 default:
539 panic("%s: unknown RMI PRID IMPL", __func__);
540 }
541
542 aprint_normal("%s: link config %s\n",
543 device_xname(sc->sc_dev), sc->sc_pcie_lnktab.str);
544 }
545
546 /*
547 * rmixl_pcie_intcfg - init PCIe Link interrupt enables
548 */
549 static void
rmixl_pcie_intcfg(struct rmixl_pcie_softc * sc)550 rmixl_pcie_intcfg(struct rmixl_pcie_softc *sc)
551 {
552 int link;
553 size_t size;
554 rmixl_pcie_evcnt_t *ev;
555
556 DPRINTF(("%s: disable all link interrupts\n", __func__));
557 for (link=0; link < sc->sc_pcie_lnktab.ncfgs; link++) {
558 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r0,
559 RMIXL_PCIE_LINK_STATUS0_ERRORS);
560 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + int_enb_offset[link].r1,
561 RMIXL_PCIE_LINK_STATUS1_ERRORS);
562 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + msi_enb_offset[link], 0);
563 sc->sc_link_intr[link] = NULL;
564
565 /*
566 * allocate per-cpu, per-pin interrupt event counters
567 */
568 size = ncpu * PCI_INTERRUPT_PIN_MAX * sizeof(rmixl_pcie_evcnt_t);
569 ev = malloc(size, M_DEVBUF, M_WAITOK);
570 sc->sc_evcnts[link] = ev;
571 for (int pin=PCI_INTERRUPT_PIN_A; pin <= PCI_INTERRUPT_PIN_MAX; pin++) {
572 for (int cpu=0; cpu < ncpu; cpu++) {
573 ev = RMIXL_PCIE_EVCNT(sc, link, pin - 1, cpu);
574 snprintf(ev->name, sizeof(ev->name),
575 "cpu%d, link %d, pin %d", cpu, link, pin);
576 evcnt_attach_dynamic(&ev->evcnt, EVCNT_TYPE_INTR,
577 NULL, "rmixl_pcie", ev->name);
578 }
579 }
580 }
581 }
582
583 static void
rmixl_pcie_errata(struct rmixl_pcie_softc * sc)584 rmixl_pcie_errata(struct rmixl_pcie_softc *sc)
585 {
586 const mips_prid_t cpu_id = mips_options.mips_cpu_id;
587 u_int rev;
588 u_int lanes;
589 bool e391 = false;
590
591 /*
592 * 3.9.1 PCIe Link-0 Registers Reset to Incorrect Values
593 * check if it allies to this CPU implementation and revision
594 */
595 rev = MIPS_PRID_REV(cpu_id);
596 switch (MIPS_PRID_IMPL(cpu_id)) {
597 case MIPS_XLS104:
598 case MIPS_XLS108:
599 break;
600 case MIPS_XLS204:
601 case MIPS_XLS208:
602 /* stepping A0 is affected */
603 if (rev == 0)
604 e391 = true;
605 break;
606 case MIPS_XLS404LITE:
607 case MIPS_XLS408LITE:
608 break;
609 case MIPS_XLS404:
610 case MIPS_XLS408:
611 case MIPS_XLS416:
612 /* steppings A0 and A1 are affected */
613 if ((rev == 0) || (rev == 1))
614 e391 = true;
615 break;
616 case MIPS_XLS608:
617 case MIPS_XLS616:
618 break;
619 default:
620 panic("unknown RMI PRID IMPL");
621 }
622
623 /*
624 * for XLS we only need to check entry #0
625 * this may need to change for later XL family chips
626 */
627 lanes = sc->sc_pcie_lnktab.cfg[0].lanes;
628
629 if ((e391 != false) && ((lanes == 2) || (lanes == 4))) {
630 /*
631 * attempt work around for errata 3.9.1
632 * "PCIe Link-0 Registers Reset to Incorrect Values"
633 * the registers are write-once: if the firmware already wrote,
634 * then our writes are ignored; hope they did it right.
635 */
636 uint32_t queuectrl;
637 uint32_t bufdepth;
638 #ifdef DIAGNOSTIC
639 uint32_t r;
640 #endif
641
642 aprint_normal("%s: attempt work around for errata 3.9.1",
643 device_xname(sc->sc_dev));
644 if (lanes == 4) {
645 queuectrl = 0x00018074;
646 bufdepth = 0x001901D1;
647 } else {
648 queuectrl = 0x00018036;
649 bufdepth = 0x001900D9;
650 }
651
652 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE +
653 RMIXL_VC0_POSTED_RX_QUEUE_CTRL, queuectrl);
654 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_BE +
655 RMIXL_VC0_POSTED_BUFFER_DEPTH, bufdepth);
656
657 #ifdef DIAGNOSTIC
658 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE +
659 RMIXL_VC0_POSTED_RX_QUEUE_CTRL);
660 printf("\nVC0_POSTED_RX_QUEUE_CTRL %#x\n", r);
661
662 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_BE +
663 RMIXL_VC0_POSTED_BUFFER_DEPTH);
664 printf("VC0_POSTED_BUFFER_DEPTH %#x\n", r);
665 #endif
666 }
667 }
668
669 static void
rmixl_pcie_init(struct rmixl_pcie_softc * sc)670 rmixl_pcie_init(struct rmixl_pcie_softc *sc)
671 {
672 pci_chipset_tag_t pc = &sc->sc_pci_chipset;
673 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
674 struct pciconf_resources *pcires;
675 #endif
676
677 pc->pc_conf_v = (void *)sc;
678 pc->pc_attach_hook = rmixl_pcie_attach_hook;
679 pc->pc_bus_maxdevs = rmixl_pcie_bus_maxdevs;
680 pc->pc_make_tag = rmixl_pcie_make_tag;
681 pc->pc_decompose_tag = rmixl_pcie_decompose_tag;
682 pc->pc_conf_read = rmixl_pcie_conf_read;
683 pc->pc_conf_write = rmixl_pcie_conf_write;
684
685 pc->pc_intr_v = (void *)sc;
686 pc->pc_intr_map = rmixl_pcie_intr_map;
687 pc->pc_intr_string = rmixl_pcie_intr_string;
688 pc->pc_intr_evcnt = rmixl_pcie_intr_evcnt;
689 pc->pc_intr_establish = rmixl_pcie_intr_establish;
690 pc->pc_intr_disestablish = rmixl_pcie_intr_disestablish;
691 pc->pc_conf_interrupt = rmixl_conf_interrupt;
692
693 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
694 /*
695 * Configure the PCI bus.
696 */
697 struct rmixl_config *rcp = &rmixl_configuration;
698
699 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
700
701 pcires = pciconf_resource_init();
702
703 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
704 rcp->rc_pci_io_pbase, rcp->rc_pci_io_size);
705 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
706 rcp->rc_pci_mem_pbase, rcp->rc_pci_mem_size);
707
708 pci_configure_bus(pc, pcires, 0,
709 mips_cache_info.mci_dcache_align);
710
711 pciconf_resource_fini(pcires);
712 #endif
713 }
714
715 static void
rmixl_pcie_init_ecfg(struct rmixl_pcie_softc * sc)716 rmixl_pcie_init_ecfg(struct rmixl_pcie_softc *sc)
717 {
718 void *v;
719 pcitag_t tag;
720 pcireg_t r;
721
722 v = sc;
723 tag = rmixl_pcie_make_tag(v, 0, 0, 0);
724
725 #ifdef PCI_DEBUG
726 int i, offset;
727 static const int offtab[] =
728 { 0, 4, 8, 0xc, 0x10, 0x14, 0x18, 0x1c,
729 0x2c, 0x30, 0x34 };
730 for (i=0; i < sizeof(offtab)/sizeof(offtab[0]); i++) {
731 offset = 0x100 + offtab[i];
732 r = rmixl_pcie_conf_read(v, tag, offset);
733 printf("%s: %#x: %#x\n", __func__, offset, r);
734 }
735 #endif
736 r = rmixl_pcie_conf_read(v, tag, 0x100);
737 if (r == -1)
738 return; /* cannot access */
739
740 /* check pre-existing uncorrectable errs */
741 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UESR);
742 r &= ~PCIE_ECFG_UExR_RESV;
743 if (r != 0)
744 panic("%s: Uncorrectable Error Status: %#x\n",
745 __func__, r);
746
747 /* unmask all uncorrectable errs */
748 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEMR);
749 r &= ~PCIE_ECFG_UExR_RESV;
750 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r);
751
752 /* ensure default uncorrectable err severity confniguration */
753 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_UEVR);
754 r &= ~PCIE_ECFG_UExR_RESV;
755 r |= PCIE_ECFG_UEVR_DFLT;
756 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEVR, r);
757
758 /* check pre-existing correctable errs */
759 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CESR);
760 r &= ~PCIE_ECFG_CExR_RESV;
761 #ifdef DIAGNOSTIC
762 if (r != 0)
763 aprint_normal("%s: Correctable Error Status: %#x\n",
764 device_xname(sc->sc_dev), r);
765 #endif
766
767 /* unmask all correctable errs */
768 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_CEMR);
769 r &= ~PCIE_ECFG_CExR_RESV;
770 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_UEMR, r);
771
772 /* check pre-existing Root Error Status */
773 r = rmixl_pcie_conf_read(v, tag, RMIXL_PCIE_ECFG_RESR);
774 r &= ~PCIE_ECFG_RESR_RESV;
775 if (r != 0)
776 panic("%s: Root Error Status: %#x\n", __func__, r);
777 /* XXX TMP FIXME */
778
779 /* enable all Root errs */
780 r = (pcireg_t)(~PCIE_ECFG_RECR_RESV);
781 rmixl_pcie_conf_write(v, tag, RMIXL_PCIE_ECFG_RECR, r);
782
783 /*
784 * establish ISR for PCIE Fatal Error interrupt
785 * - for XLS4xxLite, XLS2xx, XLS1xx only
786 */
787 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
788 case MIPS_XLS104:
789 case MIPS_XLS108:
790 case MIPS_XLS204:
791 case MIPS_XLS208:
792 case MIPS_XLS404LITE:
793 case MIPS_XLS408LITE:
794 sc->sc_fatal_ih = rmixl_intr_establish(29, sc->sc_tmsk,
795 IPL_HIGH, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH,
796 rmixl_pcie_error_intr, v, false);
797 break;
798 default:
799 break;
800 }
801
802 #if defined(DEBUG) || defined(DDB)
803 rmixl_pcie_v = v;
804 #endif
805 }
806
807 void
rmixl_conf_interrupt(void * v,int bus,int dev,int ipin,int swiz,int * iline)808 rmixl_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline)
809 {
810 DPRINTF(("%s: %p, %d, %d, %d, %d, %p\n",
811 __func__, v, bus, dev, ipin, swiz, iline));
812 }
813
814 void
rmixl_pcie_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)815 rmixl_pcie_attach_hook(device_t parent, device_t self,
816 struct pcibus_attach_args *pba)
817 {
818 DPRINTF(("%s: pba_bus %d, pba_bridgetag %p, pc_conf_v %p\n",
819 __func__, pba->pba_bus, pba->pba_bridgetag,
820 pba->pba_pc->pc_conf_v));
821 }
822
823 int
rmixl_pcie_bus_maxdevs(void * v,int busno)824 rmixl_pcie_bus_maxdevs(void *v, int busno)
825 {
826 return (32); /* XXX depends on the family of XLS SoC */
827 }
828
829 /*
830 * rmixl_tag_to_ecfg - convert cfg address (generic tag) to ecfg address
831 *
832 * 39:29 (reserved)
833 * 28 Swap (0=little, 1=big endian)
834 * 27:20 Bus number
835 * 19:15 Device number
836 * 14:12 Function number
837 * 11:8 Extended Register number
838 * 7:0 Register number
839 */
840 static pcitag_t
rmixl_tag_to_ecfg(pcitag_t tag)841 rmixl_tag_to_ecfg(pcitag_t tag)
842 {
843 KASSERT((tag & __BITS(7,0)) == 0);
844 return (tag << 4);
845 }
846
847 /*
848 * XLS pci tag is a 40 bit address composed thusly:
849 * 39:25 (reserved)
850 * 24 Swap (0=little, 1=big endian)
851 * 23:16 Bus number
852 * 15:11 Device number
853 * 10:8 Function number
854 * 7:0 Register number
855 *
856 * Note: this is the "native" composition for addressing CFG space, but not for ECFG space.
857 */
858 pcitag_t
rmixl_pcie_make_tag(void * v,int bus,int dev,int fun)859 rmixl_pcie_make_tag(void *v, int bus, int dev, int fun)
860 {
861 return ((bus << 16) | (dev << 11) | (fun << 8));
862 }
863
864 void
rmixl_pcie_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)865 rmixl_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
866 {
867 if (bp != NULL)
868 *bp = (tag >> 16) & 0xff;
869 if (dp != NULL)
870 *dp = (tag >> 11) & 0x1f;
871 if (fp != NULL)
872 *fp = (tag >> 8) & 0x7;
873 }
874
875 void
rmixl_pcie_tag_print(const char * restrict s,void * v,pcitag_t tag,int offset,vaddr_t va,u_long r)876 rmixl_pcie_tag_print(const char *restrict s, void *v, pcitag_t tag, int offset,
877 vaddr_t va, u_long r)
878 {
879 int bus, dev, fun;
880
881 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun);
882 printf("%s: %d/%d/%d/%d - %#" PRIxVADDR ":%#lx\n",
883 s, bus, dev, fun, offset, va, r);
884 }
885
886 static int
rmixl_pcie_conf_setup(struct rmixl_pcie_softc * sc,pcitag_t tag,int * offp,bus_space_tag_t * bstp,bus_space_handle_t * bshp)887 rmixl_pcie_conf_setup(struct rmixl_pcie_softc *sc,
888 pcitag_t tag, int *offp, bus_space_tag_t *bstp,
889 bus_space_handle_t *bshp)
890 {
891 struct rmixl_config *rcp = &rmixl_configuration;
892 bus_space_tag_t bst;
893 bus_space_handle_t bsh;
894 bus_size_t size;
895 pcitag_t mask;
896 bus_addr_t ba;
897 int err;
898 static bus_space_handle_t cfg_bsh;
899 static bus_addr_t cfg_oba = -1;
900 static bus_space_handle_t ecfg_bsh;
901 static bus_addr_t ecfg_oba = -1;
902
903 /*
904 * bus space depends on offset
905 */
906 if ((*offp >= 0) && (*offp < 0x100)) {
907 mask = __BITS(15,0);
908 bst = sc->sc_pci_cfg_memt;
909 ba = rcp->rc_pci_cfg_pbase;
910 ba += (tag & ~mask);
911 *offp += (tag & mask);
912 if (ba != cfg_oba) {
913 size = (bus_size_t)(mask + 1);
914 if (cfg_oba != -1)
915 bus_space_unmap(bst, cfg_bsh, size);
916 err = bus_space_map(bst, ba, size, 0, &cfg_bsh);
917 if (err != 0) {
918 #ifdef DEBUG
919 panic("%s: bus_space_map err %d, CFG space",
920 __func__, err); /* XXX */
921 #endif
922 return -1;
923 }
924 cfg_oba = ba;
925 }
926 bsh = cfg_bsh;
927 } else if ((*offp >= 0x100) && (*offp <= 0x700)) {
928 mask = __BITS(14,0);
929 tag = rmixl_tag_to_ecfg(tag); /* convert to ECFG format */
930 bst = sc->sc_pci_ecfg_memt;
931 ba = rcp->rc_pci_ecfg_pbase;
932 ba += (tag & ~mask);
933 *offp += (tag & mask);
934 if (ba != ecfg_oba) {
935 size = (bus_size_t)(mask + 1);
936 if (ecfg_oba != -1)
937 bus_space_unmap(bst, ecfg_bsh, size);
938 err = bus_space_map(bst, ba, size, 0, &ecfg_bsh);
939 if (err != 0) {
940 #ifdef DEBUG
941 panic("%s: bus_space_map err %d, ECFG space",
942 __func__, err); /* XXX */
943 #endif
944 return -1;
945 }
946 ecfg_oba = ba;
947 }
948 bsh = ecfg_bsh;
949 } else if ((*offp > 0x700) && (*offp <= PCI_EXTCONF_SIZE)) {
950 return -1;
951 } else {
952 #ifdef DEBUG
953 panic("%s: offset %#x: unknown", __func__, *offp);
954 #endif
955 return -1;
956 }
957
958 *bstp = bst;
959 *bshp = bsh;
960
961 return 0;
962 }
963
964 pcireg_t
rmixl_pcie_conf_read(void * v,pcitag_t tag,int offset)965 rmixl_pcie_conf_read(void *v, pcitag_t tag, int offset)
966 {
967 struct rmixl_pcie_softc *sc = v;
968 static bus_space_handle_t bsh;
969 bus_space_tag_t bst;
970 pcireg_t rv;
971 uint64_t cfg0;
972
973 mutex_enter(&sc->sc_mutex);
974
975 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) {
976 cfg0 = rmixl_cache_err_dis();
977 rv = bus_space_read_4(bst, bsh, (bus_size_t)offset);
978 if (rmixl_cache_err_check() != 0) {
979 #ifdef DIAGNOSTIC
980 int bus, dev, fun;
981
982 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun);
983 printf("%s: %d/%d/%d, offset %#x: bad address\n",
984 __func__, bus, dev, fun, offset);
985 #endif
986 rv = (pcireg_t) -1;
987 }
988 rmixl_cache_err_restore(cfg0);
989 } else {
990 rv = -1;
991 }
992
993 mutex_exit(&sc->sc_mutex);
994
995 return rv;
996 }
997
998 void
rmixl_pcie_conf_write(void * v,pcitag_t tag,int offset,pcireg_t val)999 rmixl_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
1000 {
1001 struct rmixl_pcie_softc *sc = v;
1002 static bus_space_handle_t bsh;
1003 bus_space_tag_t bst;
1004 uint64_t cfg0;
1005
1006 mutex_enter(&sc->sc_mutex);
1007
1008 if (rmixl_pcie_conf_setup(sc, tag, &offset, &bst, &bsh) == 0) {
1009 cfg0 = rmixl_cache_err_dis();
1010 bus_space_write_4(bst, bsh, (bus_size_t)offset, val);
1011 if (rmixl_cache_err_check() != 0) {
1012 #ifdef DIAGNOSTIC
1013 int bus, dev, fun;
1014
1015 rmixl_pcie_decompose_tag(v, tag, &bus, &dev, &fun);
1016 printf("%s: %d/%d/%d, offset %#x: bad address\n",
1017 __func__, bus, dev, fun, offset);
1018 #endif
1019 }
1020 rmixl_cache_err_restore(cfg0);
1021 }
1022
1023 mutex_exit(&sc->sc_mutex);
1024 }
1025
1026 int
rmixl_pcie_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * pih)1027 rmixl_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *pih)
1028 {
1029 int device;
1030 u_int link;
1031 u_int irq;
1032
1033 /*
1034 * The bus is unimportant since it can change depending on the
1035 * configuration. We are tied to device # of PCIe bridge we are
1036 * ultimately attached to.
1037 */
1038 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag,
1039 NULL, &device, NULL);
1040
1041 #ifdef DEBUG
1042 DPRINTF(("%s: ps_bus %d, pa_intrswiz %#x, pa_intrtag %#lx,"
1043 " pa_intrpin %d, pa_intrline %d, pa_rawintrpin %d\n",
1044 __func__, pa->pa_bus, pa->pa_intrswiz, pa->pa_intrtag,
1045 pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin));
1046 #endif
1047
1048 /*
1049 * PCIe Link INT irq assignment is cpu implementation specific
1050 */
1051 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
1052 case MIPS_XLS104:
1053 case MIPS_XLS108:
1054 case MIPS_XLS404LITE:
1055 case MIPS_XLS408LITE:
1056 if (device > 1)
1057 panic("%s: bad bus %d", __func__, device);
1058 link = device;
1059 irq = device + 26;
1060 break;
1061 case MIPS_XLS204:
1062 case MIPS_XLS208: {
1063 if (device > 3)
1064 panic("%s: bad bus %d", __func__, device);
1065 link = device;
1066 irq = device + (device & 2 ? 21 : 26);
1067 break;
1068 }
1069 case MIPS_XLS404:
1070 case MIPS_XLS408:
1071 case MIPS_XLS416:
1072 case MIPS_XLS608:
1073 case MIPS_XLS616:
1074 if (device > 3)
1075 panic("%s: bad bus %d", __func__, device);
1076 link = device;
1077 irq = device + 26;
1078 break;
1079 default:
1080 panic("%s: cpu IMPL %#x not supported\n",
1081 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id));
1082 }
1083
1084 if (pa->pa_intrpin != PCI_INTERRUPT_PIN_NONE)
1085 *pih = rmixl_pcie_make_pih(link, pa->pa_intrpin - 1, irq);
1086 else
1087 *pih = ~0;
1088
1089 return 0;
1090 }
1091
1092 const char *
rmixl_pcie_intr_string(void * v,pci_intr_handle_t pih,char * buf,size_t len)1093 rmixl_pcie_intr_string(void *v, pci_intr_handle_t pih, char *buf, size_t len)
1094 {
1095 const char *name = "(illegal)";
1096 u_int link, bitno, irq;
1097
1098 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq);
1099
1100 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
1101 case MIPS_XLS104:
1102 case MIPS_XLS108:
1103 case MIPS_XLS404LITE:
1104 case MIPS_XLS408LITE:
1105 switch (irq) {
1106 case 26:
1107 case 27:
1108 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq));
1109 break;
1110 }
1111 break;
1112 case MIPS_XLS204:
1113 case MIPS_XLS208:
1114 switch (irq) {
1115 case 23:
1116 case 24:
1117 case 26:
1118 case 27:
1119 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq));
1120 break;
1121 }
1122 break;
1123 case MIPS_XLS404:
1124 case MIPS_XLS408:
1125 case MIPS_XLS416:
1126 case MIPS_XLS608:
1127 case MIPS_XLS616:
1128 switch (irq) {
1129 case 26:
1130 case 27:
1131 case 28:
1132 case 29:
1133 name = rmixl_intr_string(RMIXL_IRT_VECTOR(irq));
1134 break;
1135 }
1136 break;
1137 default:
1138 panic("%s: cpu IMPL %#x not supported\n",
1139 __func__, MIPS_PRID_IMPL(mips_options.mips_cpu_id));
1140 }
1141
1142 strlcpy(buf, name, len);
1143 return buf;
1144 }
1145
1146 const struct evcnt *
rmixl_pcie_intr_evcnt(void * v,pci_intr_handle_t pih)1147 rmixl_pcie_intr_evcnt(void *v, pci_intr_handle_t pih)
1148 {
1149 return NULL;
1150 }
1151
1152 static pci_intr_handle_t
rmixl_pcie_make_pih(u_int link,u_int bitno,u_int irq)1153 rmixl_pcie_make_pih(u_int link, u_int bitno, u_int irq)
1154 {
1155 pci_intr_handle_t pih;
1156
1157 KASSERT(link < RMIXL_PCIE_NLINKS_MAX);
1158 KASSERT(bitno < 64);
1159 KASSERT(irq < 32);
1160
1161 pih = (irq << 10);
1162 pih |= (bitno << 4);
1163 pih |= link;
1164
1165 return pih;
1166 }
1167
1168 static void
rmixl_pcie_decompose_pih(pci_intr_handle_t pih,u_int * link,u_int * bitno,u_int * irq)1169 rmixl_pcie_decompose_pih(pci_intr_handle_t pih, u_int *link, u_int *bitno, u_int *irq)
1170 {
1171 *link = (u_int)(pih & 0xf);
1172 *bitno = (u_int)((pih >> 4) & 0x3f);
1173 *irq = (u_int)(pih >> 10);
1174
1175 KASSERT(*link < RMIXL_PCIE_NLINKS_MAX);
1176 KASSERT(*bitno < 64);
1177 KASSERT(*irq < 32);
1178 }
1179
1180 static void
rmixl_pcie_intr_disestablish(void * v,void * ih)1181 rmixl_pcie_intr_disestablish(void *v, void *ih)
1182 {
1183 rmixl_pcie_softc_t *sc = v;
1184 rmixl_pcie_link_dispatch_t *dip = ih;
1185 rmixl_pcie_link_intr_t *lip = sc->sc_link_intr[dip->link];
1186 uint32_t r;
1187 uint32_t bit;
1188 u_int offset;
1189 u_int other;
1190 bool busy;
1191
1192 DPRINTF(("%s: link=%d pin=%d irq=%d\n",
1193 __func__, dip->link, dip->bitno + 1, dip->irq));
1194
1195 mutex_enter(&sc->sc_mutex);
1196
1197 dip->func = NULL; /* mark unused, prevent further dispatch */
1198
1199 /*
1200 * if no other dispatch handle is using this interrupt,
1201 * we can disable it
1202 */
1203 busy = false;
1204 for (int i=0; i < lip->dispatch_count; i++) {
1205 rmixl_pcie_link_dispatch_t *d = &lip->dispatch_data[i];
1206 if (d == dip)
1207 continue;
1208 if (d->bitno == dip->bitno) {
1209 busy = true;
1210 break;
1211 }
1212 }
1213 if (! busy) {
1214 if (dip->bitno < 32) {
1215 bit = 1 << dip->bitno;
1216 offset = int_enb_offset[dip->link].r0;
1217 other = int_enb_offset[dip->link].r1;
1218 } else {
1219 bit = 1 << (dip->bitno - 32);
1220 offset = int_enb_offset[dip->link].r1;
1221 other = int_enb_offset[dip->link].r0;
1222 }
1223
1224 /* disable this interrupt in the PCIe bridge */
1225 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset);
1226 r &= ~bit;
1227 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r);
1228
1229 /*
1230 * if both ENABLE0 and ENABLE1 are 0
1231 * disable the link interrupt
1232 */
1233 if (r == 0) {
1234 /* check the other reg */
1235 if (RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + other) == 0) {
1236 DPRINTF(("%s: disable link %d\n", __func__, lip->link));
1237
1238 /* tear down interrupt on this link */
1239 rmixl_intr_disestablish(lip->ih);
1240
1241 /* commit NULL interrupt set */
1242 sc->sc_link_intr[dip->link] = NULL;
1243
1244 /* schedule delayed free of the old link interrupt set */
1245 rmixl_pcie_lip_free_callout(lip);
1246 }
1247 }
1248 }
1249
1250 mutex_exit(&sc->sc_mutex);
1251 }
1252
1253 static void *
rmixl_pcie_intr_establish(void * v,pci_intr_handle_t pih,int ipl,int (* func)(void *),void * arg)1254 rmixl_pcie_intr_establish(void *v, pci_intr_handle_t pih, int ipl,
1255 int (*func)(void *), void *arg)
1256 {
1257 rmixl_pcie_softc_t *sc = v;
1258 u_int link, bitno, irq;
1259 uint32_t r;
1260 rmixl_pcie_link_intr_t *lip;
1261 rmixl_pcie_link_dispatch_t *dip = NULL;
1262 uint32_t bit;
1263 u_int offset;
1264
1265 if (pih == ~0) {
1266 DPRINTF(("%s: bad pih=%#lx, implies PCI_INTERRUPT_PIN_NONE\n",
1267 __func__, pih));
1268 return NULL;
1269 }
1270
1271 rmixl_pcie_decompose_pih(pih, &link, &bitno, &irq);
1272 DPRINTF(("%s: link=%d pin=%d irq=%d\n",
1273 __func__, link, bitno + 1, irq));
1274
1275 mutex_enter(&sc->sc_mutex);
1276
1277 lip = rmixl_pcie_lip_add_1(sc, link, irq, ipl);
1278 if (lip == NULL)
1279 return NULL;
1280
1281 /*
1282 * initializae our new interrupt, the last element in dispatch_data[]
1283 */
1284 dip = &lip->dispatch_data[lip->dispatch_count - 1];
1285 dip->link = link;
1286 dip->bitno = bitno;
1287 dip->irq = irq;
1288 dip->func = func;
1289 dip->arg = arg;
1290 dip->counts = RMIXL_PCIE_EVCNT(sc, link, bitno, 0);
1291
1292 if (bitno < 32) {
1293 offset = int_enb_offset[link].r0;
1294 bit = 1 << bitno;
1295 } else {
1296 offset = int_enb_offset[link].r1;
1297 bit = 1 << (bitno - 32);
1298 }
1299
1300 /* commit the new link interrupt set */
1301 sc->sc_link_intr[link] = lip;
1302
1303 /* enable this interrupt in the PCIe bridge */
1304 r = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + offset);
1305 r |= bit;
1306 RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PCIE_LE + offset, r);
1307
1308 mutex_exit(&sc->sc_mutex);
1309 return dip;
1310 }
1311
1312 rmixl_pcie_link_intr_t *
rmixl_pcie_lip_add_1(rmixl_pcie_softc_t * sc,u_int link,int irq,int ipl)1313 rmixl_pcie_lip_add_1(rmixl_pcie_softc_t *sc, u_int link, int irq, int ipl)
1314 {
1315 rmixl_pcie_link_intr_t *lip_old = sc->sc_link_intr[link];
1316 rmixl_pcie_link_intr_t *lip_new;
1317 u_int dispatch_count;
1318 size_t size;
1319
1320 dispatch_count = 1;
1321 size = sizeof(rmixl_pcie_link_intr_t);
1322 if (lip_old != NULL) {
1323 /*
1324 * count only those dispatch elements still in use
1325 * unused ones will be pruned during copy
1326 * i.e. we are "lazy" there is no rmixl_pcie_lip_sub_1
1327 */
1328 for (int i=0; i < lip_old->dispatch_count; i++) {
1329 if (lip_old->dispatch_data[i].func != NULL) {
1330 dispatch_count++;
1331 size += sizeof(rmixl_pcie_link_intr_t);
1332 }
1333 }
1334 }
1335
1336 /*
1337 * allocate and initialize link intr struct
1338 * with one or more dispatch handles
1339 */
1340 lip_new = malloc(size, M_DEVBUF, M_WAITOK);
1341 if (lip_old == NULL) {
1342 /* initialize the link interrupt struct */
1343 lip_new->sc = sc;
1344 lip_new->link = link;
1345 lip_new->ipl = ipl;
1346 lip_new->ih = rmixl_intr_establish(irq, sc->sc_tmsk,
1347 ipl, RMIXL_TRIG_LEVEL, RMIXL_POLR_HIGH,
1348 rmixl_pcie_intr, lip_new, false);
1349 if (lip_new->ih == NULL)
1350 panic("%s: cannot establish irq %d", __func__, irq);
1351 } else {
1352 /*
1353 * all intrs on a link get same ipl and sc
1354 * first intr established sets the standard
1355 */
1356 KASSERT(sc == lip_old->sc);
1357 if (sc != lip_old->sc) {
1358 printf("%s: sc %p mismatch\n", __func__, sc);
1359 free(lip_new, M_DEVBUF);
1360 return NULL;
1361 }
1362 KASSERT (ipl == lip_old->ipl);
1363 if (ipl != lip_old->ipl) {
1364 printf("%s: ipl %d mismatch\n", __func__, ipl);
1365 free(lip_new, M_DEVBUF);
1366 return NULL;
1367 }
1368 /*
1369 * copy lip_old to lip_new, skipping unused dispatch elemets
1370 */
1371 memcpy(lip_new, lip_old, sizeof(rmixl_pcie_link_intr_t));
1372 for (int j=0, i=0; i < lip_old->dispatch_count; i++) {
1373 if (lip_old->dispatch_data[i].func != NULL) {
1374 memcpy(&lip_new->dispatch_data[j],
1375 &lip_old->dispatch_data[i],
1376 sizeof(rmixl_pcie_link_dispatch_t));
1377 j++;
1378 }
1379 }
1380
1381 /*
1382 * schedule delayed free of old link interrupt set
1383 */
1384 rmixl_pcie_lip_free_callout(lip_old);
1385 }
1386 lip_new->dispatch_count = dispatch_count;
1387
1388 return lip_new;
1389 }
1390
1391 /*
1392 * delay free of the old link interrupt set
1393 * to allow anyone still using it to do so safely
1394 * XXX 2 seconds should be plenty?
1395 */
1396 static void
rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t * lip)1397 rmixl_pcie_lip_free_callout(rmixl_pcie_link_intr_t *lip)
1398 {
1399 callout_init(&lip->callout, 0);
1400 callout_reset(&lip->callout, 2 * hz, rmixl_pcie_lip_free, lip);
1401 }
1402
1403 static void
rmixl_pcie_lip_free(void * arg)1404 rmixl_pcie_lip_free(void *arg)
1405 {
1406 rmixl_pcie_link_intr_t *lip = arg;
1407
1408 callout_destroy(&lip->callout);
1409 free(lip, M_DEVBUF);
1410 }
1411
1412 static int
rmixl_pcie_intr(void * arg)1413 rmixl_pcie_intr(void *arg)
1414 {
1415 rmixl_pcie_link_intr_t *lip = arg;
1416 u_int link = lip->link;
1417 int rv = 0;
1418
1419 uint32_t status0 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r0);
1420 uint32_t status1 = RMIXL_IOREG_READ(RMIXL_IO_DEV_PCIE_LE + int_sts_offset[link].r1);
1421 uint64_t status = ((uint64_t)status1 << 32) | status0;
1422 DPRINTF(("%s: %d:%#"PRIx64"\n", __func__, link, status));
1423
1424 if (status != 0) {
1425 rmixl_pcie_link_dispatch_t *dip;
1426
1427 if (status & RMIXL_PCIE_LINK_STATUS_ERRORS)
1428 rmixl_pcie_link_error_intr(link, status0, status1);
1429
1430 for (u_int i=0; i < lip->dispatch_count; i++) {
1431 dip = &lip->dispatch_data[i];
1432 int (*func)(void *) = dip->func;
1433 if (func != NULL) {
1434 uint64_t bit = 1 << dip->bitno;
1435 if ((status & bit) != 0) {
1436 (void)(*func)(dip->arg);
1437 dip->counts[cpu_index(curcpu())].evcnt.ev_count++;
1438 rv = 1;
1439 }
1440 }
1441 }
1442 }
1443
1444 return rv;
1445 }
1446
1447 static void
rmixl_pcie_link_error_intr(u_int link,uint32_t status0,uint32_t status1)1448 rmixl_pcie_link_error_intr(u_int link, uint32_t status0, uint32_t status1)
1449 {
1450 printf("%s: mask %#"PRIx64"\n",
1451 __func__, RMIXL_PCIE_LINK_STATUS_ERRORS);
1452 printf("%s: PCIe Link Error: link=%d status0=%#x status1=%#x\n",
1453 __func__, link, status0, status1);
1454 #if defined(DDB) && defined(DEBUG)
1455 Debugger();
1456 #endif
1457 }
1458
1459 #if defined(DEBUG) || defined(DDB)
1460 /* this function exists to facilitate call from ddb */
1461 int
rmixl_pcie_error_check(void)1462 rmixl_pcie_error_check(void)
1463 {
1464 if (rmixl_pcie_v != 0)
1465 return _rmixl_pcie_error_check(rmixl_pcie_v);
1466 return -1;
1467 }
1468 #endif
1469
1470 STATIC int
_rmixl_pcie_error_check(void * v)1471 _rmixl_pcie_error_check(void *v)
1472 {
1473 int i, offset;
1474 pcireg_t r;
1475 pcitag_t tag;
1476 int err=0;
1477 #ifdef DIAGNOSTIC
1478 pcireg_t regs[PCIE_ECFG_ERRS_OFFTAB_NENTRIES];
1479 #endif
1480
1481 tag = rmixl_pcie_make_tag(v, 0, 0, 0); /* XXX */
1482
1483 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) {
1484 offset = pcie_ecfg_errs_tab[i].offset;
1485 r = rmixl_pcie_conf_read(v, tag, offset);
1486 #ifdef DIAGNOSTIC
1487 regs[i] = r;
1488 #endif
1489 if (r != 0) {
1490 pcireg_t rw1c = r & pcie_ecfg_errs_tab[i].rw1c;
1491 if (rw1c != 0) {
1492 /* attempt to clear the error */
1493 rmixl_pcie_conf_write(v, tag, offset, rw1c);
1494 };
1495 if (offset == RMIXL_PCIE_ECFG_CESR)
1496 err |= 1; /* correctable */
1497 else
1498 err |= 2; /* uncorrectable */
1499 }
1500 }
1501 #ifdef DIAGNOSTIC
1502 if (err != 0) {
1503 for (i=0; i < PCIE_ECFG_ERRS_OFFTAB_NENTRIES; i++) {
1504 offset = pcie_ecfg_errs_tab[i].offset;
1505 printf("%s: %#x: %#x\n", __func__, offset, regs[i]);
1506 }
1507 }
1508 #endif
1509
1510 return err;
1511 }
1512
1513 static int
rmixl_pcie_error_intr(void * v)1514 rmixl_pcie_error_intr(void *v)
1515 {
1516 if (_rmixl_pcie_error_check(v) < 2)
1517 return 0; /* correctable */
1518
1519 /* uncorrectable */
1520 #if DDB
1521 Debugger();
1522 #endif
1523
1524 /* XXX reset and recover? */
1525
1526 panic("%s\n", __func__);
1527 }
1528
1529 /*
1530 * rmixl_physaddr_init_pcie:
1531 * called from rmixl_physaddr_init to get region addrs & sizes
1532 * from PCIE CFG, ECFG, IO, MEM BARs
1533 */
1534 void
rmixl_physaddr_init_pcie(struct extent * ext)1535 rmixl_physaddr_init_pcie(struct extent *ext)
1536 {
1537 u_long base;
1538 u_long size;
1539 uint32_t r;
1540
1541 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_CFG_BAR);
1542 if ((r & RMIXL_PCIE_CFG_BAR_ENB) != 0) {
1543 base = (u_long)(RMIXL_PCIE_CFG_BAR_TO_BA((uint64_t)r)
1544 / (1024 * 1024));
1545 size = (u_long)RMIXL_PCIE_CFG_SIZE / (1024 * 1024);
1546 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__,
1547 __LINE__, "CFG", r, base * 1024 * 1024, size));
1548 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0)
1549 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) "
1550 "failed", __func__, ext, base, size, EX_NOWAIT);
1551 }
1552
1553 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_ECFG_BAR);
1554 if ((r & RMIXL_PCIE_ECFG_BAR_ENB) != 0) {
1555 base = (u_long)(RMIXL_PCIE_ECFG_BAR_TO_BA((uint64_t)r)
1556 / (1024 * 1024));
1557 size = (u_long)RMIXL_PCIE_ECFG_SIZE / (1024 * 1024);
1558 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__,
1559 __LINE__, "ECFG", r, base * 1024 * 1024, size));
1560 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0)
1561 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) "
1562 "failed", __func__, ext, base, size, EX_NOWAIT);
1563 }
1564
1565 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_MEM_BAR);
1566 if ((r & RMIXL_PCIE_MEM_BAR_ENB) != 0) {
1567 base = (u_long)(RMIXL_PCIE_MEM_BAR_TO_BA((uint64_t)r)
1568 / (1024 * 1024));
1569 size = (u_long)(RMIXL_PCIE_MEM_BAR_TO_SIZE((uint64_t)r)
1570 / (1024 * 1024));
1571 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__,
1572 __LINE__, "MEM", r, base * 1024 * 1024, size));
1573 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0)
1574 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) "
1575 "failed", __func__, ext, base, size, EX_NOWAIT);
1576 }
1577
1578 r = RMIXL_IOREG_READ(RMIXLS_SBC_PCIE_IO_BAR);
1579 if ((r & RMIXL_PCIE_IO_BAR_ENB) != 0) {
1580 base = (u_long)(RMIXL_PCIE_IO_BAR_TO_BA((uint64_t)r)
1581 / (1024 * 1024));
1582 size = (u_long)(RMIXL_PCIE_IO_BAR_TO_SIZE((uint64_t)r)
1583 / (1024 * 1024));
1584 DPRINTF(("%s: %d: %s: 0x%08x -- 0x%010lx:%ld MB\n", __func__,
1585 __LINE__, "IO", r, base * 1024 * 1024, size));
1586 if (extent_alloc_region(ext, base, size, EX_NOWAIT) != 0)
1587 panic("%s: extent_alloc_region(%p, %#lx, %#lx, %#x) "
1588 "failed", __func__, ext, base, size, EX_NOWAIT);
1589 }
1590 }
1591