1 /* $NetBSD: ingenic_com.c,v 1.9 2018/12/11 06:34:00 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2014 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: ingenic_com.c,v 1.9 2018/12/11 06:34:00 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/kernel.h>
36 #include <sys/termios.h>
37 #include <sys/ttydefaults.h>
38 #include <sys/types.h>
39
40 #include <sys/bus.h>
41
42 #include <dev/cons.h>
43 #include <dev/ic/comreg.h>
44 #include <dev/ic/comvar.h>
45
46 #include <mips/cpuregs.h>
47
48 #include <mips/ingenic/ingenic_var.h>
49 #include <mips/ingenic/ingenic_regs.h>
50
51 volatile int32_t *com0addr = (int32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
52
53 void ingenic_putchar_init(void);
54 void ingenic_puts(const char *);
55 void ingenic_putchar(char);
56
57 #ifndef CONMODE
58 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8)
59 #endif
60
61 void ingenic_com_cnattach(void);
62
63 static int ingenic_com_match(device_t, cfdata_t , void *);
64 static void ingenic_com_attach(device_t, device_t, void *);
65
66 struct ingenic_com_softc {
67 struct com_softc sc_com;
68 bus_space_tag_t sc_tag;
69 bus_space_handle_t sc_regh;
70 };
71
72 CFATTACH_DECL_NEW(ingenic_com, sizeof(struct ingenic_com_softc),
73 ingenic_com_match, ingenic_com_attach, NULL, NULL);
74
75 static bus_space_handle_t regh = 0;
76 static bus_addr_t cons_com = 0;
77 static struct com_regs cons_regs;
78 extern bus_space_tag_t apbus_memt;
79
80 static void
ingenic_com_init_regs(struct com_regs * regs,bus_space_tag_t st,bus_space_handle_t sh,bus_addr_t addr)81 ingenic_com_init_regs(struct com_regs *regs, bus_space_tag_t st,
82 bus_space_handle_t sh, bus_addr_t addr)
83 {
84
85 com_init_regs_stride(regs, st, sh, addr, 2);
86 }
87
88 void
ingenic_putchar_init(void)89 ingenic_putchar_init(void)
90 {
91 /*
92 * XXX don't screw with the UART's speed until we know what clock
93 * we're on
94 */
95 #if 0
96 int rate;
97 #endif
98 extern int comspeed(long, long, int);
99
100 com0addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(JZ_UART0);
101 #if 0
102 if (comcnfreq != -1) {
103 rate = comspeed(comcnspeed, comcnfreq, COM_TYPE_INGENIC);
104 if (rate < 0)
105 return; /* XXX */
106 #endif
107 com0addr[com_ier] = 0;
108 com0addr[com_lctl] = htole32(LCR_DLAB);
109 #if 0
110 com0addr[com_dlbl] = htole32(rate & 0xff);
111 com0addr[com_dlbh] = htole32(rate >> 8);
112 #endif
113 com0addr[com_lctl] = htole32(LCR_8BITS); /* XXX */
114 com0addr[com_mcr] = htole32(MCR_DTR|MCR_RTS);
115 com0addr[com_fifo] = htole32(
116 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
117 FIFO_TRIGGER_1 | FIFO_UART_ON);
118 #if 0
119 }
120 #endif
121 }
122
123
124 void
ingenic_putchar(char c)125 ingenic_putchar(char c)
126 {
127 int timo = 150000;
128
129 while ((le32toh(com0addr[com_lsr]) & LSR_TXRDY) == 0)
130 if (--timo == 0)
131 break;
132
133 com0addr[com_data] = htole32((uint32_t)c);
134
135 while ((le32toh(com0addr[com_lsr]) & LSR_TSRE) == 0)
136 if (--timo == 0)
137 break;
138 }
139
140 void
ingenic_puts(const char * restrict s)141 ingenic_puts(const char *restrict s)
142 {
143 char c;
144
145 while ((c = *s++) != 0)
146 ingenic_putchar(c);
147 }
148
149 void
ingenic_com_cnattach(void)150 ingenic_com_cnattach(void)
151 {
152
153 bus_space_map(apbus_memt, JZ_UART0, 0x100, 0, ®h);
154 cons_com = JZ_UART0;
155 ingenic_com_init_regs(&cons_regs, apbus_memt, regh, JZ_UART0);
156
157 comcnattach1(&cons_regs, 115200, 48000000, COM_TYPE_INGENIC, CONMODE);
158 }
159
160 static int
ingenic_com_match(device_t parent,cfdata_t cfdata,void * args)161 ingenic_com_match(device_t parent, cfdata_t cfdata, void *args)
162 {
163 struct mainbusdev {
164 const char *md_name;
165 } *aa = args;
166 if (strcmp(aa->md_name, "com") == 0) return 1;
167 return 0;
168 }
169
170
171 static void
ingenic_com_attach(device_t parent,device_t self,void * args)172 ingenic_com_attach(device_t parent, device_t self, void *args)
173 {
174 struct ingenic_com_softc *isc = device_private(self);
175 struct com_softc *sc = &isc->sc_com;
176 struct apbus_attach_args *aa = args;
177
178 sc->sc_dev = self;
179 sc->sc_frequency = 48000000;
180 sc->sc_type = COM_TYPE_INGENIC;
181 isc->sc_tag = aa->aa_bst;
182
183 if (cons_com == aa->aa_addr) {
184 isc->sc_regh = regh;
185 } else {
186 bus_space_map(apbus_memt, aa->aa_addr, 0x1000, 0, &isc->sc_regh);
187 }
188 ingenic_com_init_regs(&sc->sc_regs, aa->aa_bst, isc->sc_regh,
189 aa->aa_addr);
190
191 com_attach_subr(sc);
192 evbmips_intr_establish(aa->aa_irq, comintr, sc);
193 }
194