1 /* $NetBSD: apbus.c,v 1.21 2021/08/07 16:18:59 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2014 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /* catch-all for on-chip peripherals */
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.21 2021/08/07 16:18:59 thorpej Exp $");
33
34 #include "locators.h"
35 #define _MIPS_BUS_DMA_PRIVATE
36
37 #include <sys/param.h>
38 #include <sys/bus.h>
39 #include <sys/device.h>
40 #include <sys/extent.h>
41 #include <sys/systm.h>
42
43 #include <mips/ingenic/ingenic_var.h>
44 #include <mips/ingenic/ingenic_regs.h>
45
46 #include "opt_ingenic.h"
47
48 static int apbus_match(device_t, cfdata_t, void *);
49 static void apbus_attach(device_t, device_t, void *);
50 static int apbus_print(void *, const char *);
51 static void apbus_bus_mem_init(bus_space_tag_t, void *);
52
53 CFATTACH_DECL_NEW(apbus, 0, apbus_match, apbus_attach, NULL, NULL);
54
55 static struct mips_bus_space apbus_mbst;
56 bus_space_tag_t apbus_memt = NULL;
57
58 struct mips_bus_dma_tag apbus_dmat = {
59 ._bounce_alloc_hi = 0x10000000,
60 ._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
61 ._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
62 ._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
63 };
64
65 typedef struct apbus_dev {
66 const char *name; /* driver name */
67 bus_addr_t addr; /* base address */
68 uint32_t irq; /* interrupt */
69 uint32_t clk0; /* bit(s) in CLKGR0 */
70 uint32_t clk1; /* bit(s) in CLKGR1 */
71 uint32_t clkreg; /* CGU register */
72 } apbus_dev_t;
73
74 static const apbus_dev_t apbus_devs[] = {
75 { "efuse", JZ_EFUSE, -1, 0, 0, 0},
76 { "com", JZ_UART0, 51, CLK_UART0, 0, 0},
77 { "com", JZ_UART1, 50, CLK_UART1, 0, 0},
78 { "com", JZ_UART2, 49, CLK_UART2, 0, 0},
79 { "com", JZ_UART3, 48, CLK_UART3, 0, 0},
80 { "com", JZ_UART4, 34, 0, CLK_UART4, 0},
81 { "dwctwo", JZ_DWC2_BASE, 21, CLK_OTG0 | CLK_UHC, CLK_OTG1, 0},
82 { "ohci", JZ_OHCI_BASE, 5, CLK_UHC, 0, 0},
83 { "ehci", JZ_EHCI_BASE, 20, CLK_UHC, 0, 0},
84 { "dme", JZ_DME_BASE, -1, 0, 0, 0},
85 { "jzgpio", JZ_GPIO_A_BASE, 17, 0, 0, 0},
86 { "jzgpio", JZ_GPIO_B_BASE, 16, 0, 0, 0},
87 { "jzgpio", JZ_GPIO_C_BASE, 15, 0, 0, 0},
88 { "jzgpio", JZ_GPIO_D_BASE, 14, 0, 0, 0},
89 { "jzgpio", JZ_GPIO_E_BASE, 13, 0, 0, 0},
90 { "jzgpio", JZ_GPIO_F_BASE, 12, 0, 0, 0},
91 { "jziic", JZ_SMB0_BASE, 60, CLK_SMB0, 0, 0},
92 { "jziic", JZ_SMB1_BASE, 59, CLK_SMB1, 0, 0},
93 { "jziic", JZ_SMB2_BASE, 58, CLK_SMB2, 0, 0},
94 { "jziic", JZ_SMB3_BASE, 57, 0, CLK_SMB3, 0},
95 { "jziic", JZ_SMB4_BASE, 56, 0, CLK_SMB4, 0},
96 { "jzmmc", JZ_MSC0_BASE, 37, CLK_MSC0, 0, JZ_MSC0CDR},
97 { "jzmmc", JZ_MSC1_BASE, 36, CLK_MSC1, 0, JZ_MSC1CDR},
98 { "jzmmc", JZ_MSC2_BASE, 35, CLK_MSC2, 0, JZ_MSC2CDR},
99 { "jzfb", JZ_LCDC0_BASE, 31, CLK_LCD, CLK_HDMI, 0},
100 { "jzrng", JZ_RNG, -1, 0, 0, 0},
101 { NULL, -1, -1, 0, 0, 0}
102 };
103
104 void
apbus_init(void)105 apbus_init(void)
106 {
107 static bool done = false;
108 if (done)
109 return;
110 done = true;
111
112 apbus_bus_mem_init(&apbus_mbst, NULL);
113 apbus_memt = &apbus_mbst;
114 }
115
116 int
apbus_match(device_t parent,cfdata_t match,void * aux)117 apbus_match(device_t parent, cfdata_t match, void *aux)
118 {
119 struct mainbusdev {
120 const char *md_name;
121 } *aa = aux;
122 if (strcmp(aa->md_name, "apbus") == 0) return 1;
123 return 0;
124 }
125
126 void
apbus_attach(device_t parent,device_t self,void * aux)127 apbus_attach(device_t parent, device_t self, void *aux)
128 {
129 uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv;
130 aprint_normal("\n");
131
132 /* should have been called early on */
133 apbus_init();
134
135 #ifdef INGENIC_DEBUG
136 printf("core ctrl: %08x\n", MFC0(12, 2));
137 printf("core status: %08x\n", MFC0(12, 3));
138 printf("REIM: %08x\n", MFC0(12, 4));
139 printf("ID: %08x\n", MFC0(15, 1));
140 #endif
141 /* assuming we're using MPLL */
142 mpll = readreg(JZ_CPMPCR);
143 m = (mpll & JZ_PLLM_M) >> JZ_PLLM_S;
144 n = (mpll & JZ_PLLN_M) >> JZ_PLLN_S;
145 p = (mpll & JZ_PLLP_M) >> JZ_PLLP_S;
146
147 /* assuming 48MHz EXTCLK */
148 mclk = (48000 * (m + 1) / (n + 1)) / (p + 1);
149
150 reg = readreg(JZ_CPCCR);
151 pdiv = ((reg & JZ_PDIV_M) >> JZ_PDIV_S) + 1;
152 pclk = mclk / pdiv;
153 cdiv = (reg & JZ_CDIV_M) + 1;
154 cclk = mclk / cdiv;
155
156 aprint_debug_dev(self, "mclk %d kHz\n", mclk);
157 aprint_debug_dev(self, "pclk %d kHz\n", pclk);
158 aprint_debug_dev(self, "CPU clock %d kHz\n", cclk);
159
160 /* enable clocks */
161 reg = readreg(JZ_CLKGR1);
162 reg &= ~CLK_AHB_MON; /* AHB_MON clock */
163 writereg(JZ_CLKGR1, reg);
164
165 /* enable RNG */
166 writereg(JZ_ERNG, 1);
167
168 /* wake up the USB part */
169 reg = readreg(JZ_OPCR);
170 reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
171 writereg(JZ_OPCR, reg);
172
173 /* wire up GPIOs */
174 /* iic0 */
175 gpio_as_dev0(3, 30);
176 gpio_as_dev0(3, 31);
177 /* iic1 */
178 gpio_as_dev0(4, 30);
179 gpio_as_dev0(4, 31);
180 /* iic2 */
181 gpio_as_dev2(5, 16);
182 gpio_as_dev2(5, 17);
183 /* iic3 */
184 gpio_as_dev1(3, 10);
185 gpio_as_dev1(3, 11);
186 /* iic4 */
187 /* make sure these aren't SMB4 */
188 gpio_as_dev3(4, 3);
189 gpio_as_dev3(4, 4);
190 /* these are supposed to be connected to the RTC */
191 gpio_as_dev1(4, 12);
192 gpio_as_dev1(4, 13);
193 /* these can be DDC2 or SMB4 */
194 #if 0
195 /* DDC2 devices show up at SMB4 */
196 gpio_as_dev1(5, 24);
197 gpio_as_dev1(5, 25);
198 #else
199 gpio_as_dev0(5, 24);
200 gpio_as_dev0(5, 25);
201 #endif
202 /* MSC0 */
203 gpio_as_dev1(0, 4);
204 gpio_as_dev1(0, 5);
205 gpio_as_dev1(0, 6);
206 gpio_as_dev1(0, 7);
207 gpio_as_dev1(0, 18);
208 gpio_as_dev1(0, 19);
209 gpio_as_dev1(0, 20);
210 gpio_as_dev1(0, 21);
211 gpio_as_dev1(0, 22);
212 gpio_as_dev1(0, 23);
213 gpio_as_dev1(0, 24);
214 gpio_as_intr_level_low(5, 20); /* card detect */
215
216 /* MSC1, for wifi/bt */
217 gpio_as_dev0(3, 20);
218 gpio_as_dev0(3, 21);
219 gpio_as_dev0(3, 22);
220 gpio_as_dev0(3, 23);
221 gpio_as_dev0(3, 24);
222 gpio_as_dev0(3, 25);
223
224 /* MSC2, on expansion header */
225 gpio_as_dev0(1, 20);
226 gpio_as_dev0(1, 21);
227 gpio_as_dev0(1, 28);
228 gpio_as_dev0(1, 29);
229 gpio_as_dev0(1, 30);
230 gpio_as_dev0(1, 31);
231
232 #ifndef INGENIC_DEBUG
233 printf("JZ_CLKGR0 %08x\n", readreg(JZ_CLKGR0));
234 printf("JZ_CLKGR1 %08x\n", readreg(JZ_CLKGR1));
235 printf("JZ_SPCR0 %08x\n", readreg(JZ_SPCR0));
236 printf("JZ_SPCR1 %08x\n", readreg(JZ_SPCR1));
237 printf("JZ_SRBC %08x\n", readreg(JZ_SRBC));
238 printf("JZ_OPCR %08x\n", readreg(JZ_OPCR));
239 printf("JZ_UHCCDR %08x\n", readreg(JZ_UHCCDR));
240 printf("JZ_ERNG %08x\n", readreg(JZ_ERNG));
241 printf("JZ_RNG %08x\n", readreg(JZ_RNG));
242 #endif
243
244 for (const apbus_dev_t *adv = apbus_devs; adv->name != NULL; adv++) {
245 struct apbus_attach_args aa;
246 aa.aa_name = adv->name;
247 aa.aa_addr = adv->addr;
248 aa.aa_irq = adv->irq;
249 aa.aa_dmat = &apbus_dmat;
250 aa.aa_bst = apbus_memt;
251 aa.aa_pclk = pclk;
252 aa.aa_mclk = mclk;
253 aa.aa_clockreg = adv->clkreg;
254
255 /* enable clocks as needed */
256 if (adv->clk0 != 0) {
257 reg = readreg(JZ_CLKGR0);
258 reg &= ~adv->clk0;
259 writereg(JZ_CLKGR0, reg);
260 }
261
262 if (adv->clk1 != 0) {
263 reg = readreg(JZ_CLKGR1);
264 reg &= ~adv->clk1;
265 writereg(JZ_CLKGR1, reg);
266 }
267
268 config_found(self, &aa, apbus_print, CFARGS_NONE);
269 }
270 }
271
272 int
apbus_print(void * aux,const char * pnp)273 apbus_print(void *aux, const char *pnp)
274 {
275 struct apbus_attach_args *aa = aux;
276
277 if (pnp) {
278 aprint_normal("%s at %s", aa->aa_name, pnp);
279 }
280 if (aa->aa_addr != -1)
281 aprint_normal(" addr 0x%" PRIxBUSADDR, aa->aa_addr);
282 if ((pnp == NULL) && (aa->aa_irq != -1))
283 aprint_normal(" irq %d", aa->aa_irq);
284 return (UNCONF);
285 }
286
287 #define CHIP apbus
288 #define CHIP_MEM /* defined */
289 #define CHIP_W1_BUS_START(v) 0x10000000UL
290 #define CHIP_W1_BUS_END(v) 0x20000000UL
291 #define CHIP_W1_SYS_START(v) 0x10000000UL
292 #define CHIP_W1_SYS_END(v) 0x20000000UL
293
294 #include <mips/mips/bus_space_alignstride_chipdep.c>
295