1 /* $NetBSD: esp.c,v 1.35 2024/06/02 19:27:12 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9 * Simulation Facility, NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1994 Peter Galbavy
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 * 3. All advertising materials mentioning features or use of this software
46 * must display the following acknowledgement:
47 * This product includes software developed by Peter Galbavy
48 * 4. The name of the author may not be used to endorse or promote products
49 * derived from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
60 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
61 * POSSIBILITY OF SUCH DAMAGE.
62 */
63
64 /*
65 * Based on aic6360 by Jarle Greipsland
66 *
67 * Acknowledgements: Many of the algorithms used in this driver are
68 * inspired by the work of Julian Elischer (julian@tfs.com) and
69 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
70 */
71
72 #include <sys/cdefs.h>
73 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.35 2024/06/02 19:27:12 andvar Exp $");
74
75 #include <sys/types.h>
76 #include <sys/param.h>
77 #include <sys/systm.h>
78 #include <sys/kernel.h>
79 #include <sys/errno.h>
80 #include <sys/ioctl.h>
81 #include <sys/device.h>
82 #include <sys/buf.h>
83 #include <sys/proc.h>
84 #include <sys/queue.h>
85
86 #include <dev/scsipi/scsi_all.h>
87 #include <dev/scsipi/scsipi_all.h>
88 #include <dev/scsipi/scsiconf.h>
89 #include <dev/scsipi/scsi_message.h>
90
91 #include <dev/ofw/openfirm.h>
92
93 #include <machine/cpu.h>
94 #include <machine/autoconf.h>
95 #include <machine/pio.h>
96
97 #include <dev/ic/ncr53c9xreg.h>
98 #include <dev/ic/ncr53c9xvar.h>
99
100 #include <macppc/dev/dbdma.h>
101 #include <macppc/dev/espvar.h>
102
103 int espmatch(device_t, cfdata_t, void *);
104 void espattach(device_t, device_t, void *);
105
106 /* Linkup to the rest of the kernel */
107 CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc),
108 espmatch, espattach, NULL, NULL);
109
110 /*
111 * Functions and the switch for the MI code.
112 */
113 static uint8_t esp_read_reg(struct ncr53c9x_softc *, int);
114 static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t);
115 static int esp_dma_isintr(struct ncr53c9x_softc *);
116 static void esp_dma_reset(struct ncr53c9x_softc *);
117 static int esp_dma_intr(struct ncr53c9x_softc *);
118 static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **,
119 size_t *, int, size_t *);
120 static void esp_dma_go(struct ncr53c9x_softc *);
121 static void esp_dma_stop(struct ncr53c9x_softc *);
122 static int esp_dma_isactive(struct ncr53c9x_softc *);
123
124 static struct ncr53c9x_glue esp_glue = {
125 esp_read_reg,
126 esp_write_reg,
127 esp_dma_isintr,
128 esp_dma_reset,
129 esp_dma_intr,
130 esp_dma_setup,
131 esp_dma_go,
132 esp_dma_stop,
133 esp_dma_isactive,
134 NULL, /* gl_clear_latched_intr */
135 };
136
137 static int espdmaintr(struct esp_softc *);
138 static bool esp_shutdown(device_t, int);
139
140 int
espmatch(device_t parent,cfdata_t cf,void * aux)141 espmatch(device_t parent, cfdata_t cf, void *aux)
142 {
143 struct confargs *ca = aux;
144
145 if (strcmp(ca->ca_name, "53c94") != 0)
146 return 0;
147
148 if (ca->ca_nreg != 16)
149 return 0;
150 if (ca->ca_nintr != 8)
151 return 0;
152
153 return 1;
154 }
155
156 /*
157 * Attach this instance, and then all the sub-devices
158 */
159 void
espattach(device_t parent,device_t self,void * aux)160 espattach(device_t parent, device_t self, void *aux)
161 {
162 struct esp_softc *esc = device_private(self);
163 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
164 struct confargs *ca = aux;
165 u_int *reg;
166 int sz;
167
168 /*
169 * Set up glue for MI code early; we use some of it here.
170 */
171 sc->sc_dev = self;
172 sc->sc_glue = &esp_glue;
173
174 esc->sc_node = ca->ca_node;
175 esc->sc_pri = ca->ca_intr[0];
176 aprint_normal(" irq %d", esc->sc_pri);
177
178 /*
179 * Map my registers in.
180 */
181 reg = ca->ca_reg;
182 esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1], false);
183 esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3], false);
184
185 /* Allocate 16-byte aligned DMA command space */
186 esc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20, NULL);
187
188 /* Other settings */
189 sc->sc_id = 7;
190 sz = OF_getprop(ca->ca_node, "clock-frequency",
191 &sc->sc_freq, sizeof(int));
192 if (sz != sizeof(int))
193 sc->sc_freq = 25000000;
194
195 /* gimme MHz */
196 sc->sc_freq /= 1000000;
197
198 /* esc->sc_dma->sc_esp = esc;*/
199
200 /*
201 * XXX More of this should be in ncr53c9x_attach(), but
202 * XXX should we really poke around the chip that much in
203 * XXX the MI code? Think about this more...
204 */
205
206 /*
207 * Set up static configuration info.
208 */
209 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
210 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */
211 sc->sc_cfg3 = NCRCFG3_CDB;
212 sc->sc_rev = NCR_VARIANT_NCR53C94;
213
214 /*
215 * XXX minsync and maxxfer _should_ be set up in MI code,
216 * XXX but it appears to have some dependency on what sort
217 * XXX of DMA we're hooked up to, etc.
218 */
219
220 /*
221 * This is the value used to start sync negotiations
222 * Note that the NCR register "SYNCTP" is programmed
223 * in "clocks per byte", and has a minimum value of 4.
224 * The SCSI period used in negotiation is one-fourth
225 * of the time (in nanoseconds) needed to transfer one byte.
226 * Since the chip's clock is given in MHz, we have the following
227 * formula: 4 * period = (1000 / freq) * 4
228 */
229 sc->sc_minsync = 1000 / sc->sc_freq;
230
231 sc->sc_maxxfer = 64 * 1024;
232
233 /* and the interrupts */
234 intr_establish_xname(esc->sc_pri, IST_EDGE, IPL_BIO, ncr53c9x_intr, sc,
235 device_xname(self));
236
237 /* Do the common parts of attachment. */
238 sc->sc_adapter.adapt_minphys = minphys;
239 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
240 ncr53c9x_attach(sc);
241
242 /* Turn on target selection using the `DMA' method */
243 sc->sc_features |= NCR_F_DMASELECT;
244
245 /* Reset SCSI bus when halt. */
246 if (!pmf_device_register1(self, NULL, NULL, esp_shutdown))
247 aprint_error_dev(self, "couldn't establish power handler\n");
248 }
249
250 /*
251 * Glue functions.
252 */
253
254 uint8_t
esp_read_reg(struct ncr53c9x_softc * sc,int reg)255 esp_read_reg(struct ncr53c9x_softc *sc, int reg)
256 {
257 struct esp_softc *esc = (struct esp_softc *)sc;
258
259 return in8(&esc->sc_reg[reg * 16]);
260 /*return (esc->sc_reg[reg * 16]);*/
261 }
262
263 void
esp_write_reg(struct ncr53c9x_softc * sc,int reg,uint8_t val)264 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
265 {
266 struct esp_softc *esc = (struct esp_softc *)sc;
267 uint8_t v = val;
268
269 out8(&esc->sc_reg[reg * 16], v);
270 /*esc->sc_reg[reg * 16] = v;*/
271 }
272
273 int
esp_dma_isintr(struct ncr53c9x_softc * sc)274 esp_dma_isintr(struct ncr53c9x_softc *sc)
275 {
276
277 return esp_read_reg(sc, NCR_STAT) & NCRSTAT_INT;
278 }
279
280 void
esp_dma_reset(struct ncr53c9x_softc * sc)281 esp_dma_reset(struct ncr53c9x_softc *sc)
282 {
283 struct esp_softc *esc = (struct esp_softc *)sc;
284
285 dbdma_stop(esc->sc_dmareg);
286 esc->sc_dmaactive = 0;
287 }
288
289 int
esp_dma_intr(struct ncr53c9x_softc * sc)290 esp_dma_intr(struct ncr53c9x_softc *sc)
291 {
292 struct esp_softc *esc = (struct esp_softc *)sc;
293
294 return espdmaintr(esc);
295 }
296
297 int
esp_dma_setup(struct ncr53c9x_softc * sc,uint8_t ** addr,size_t * len,int datain,size_t * dmasize)298 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
299 int datain, size_t *dmasize)
300 {
301 struct esp_softc *esc = (struct esp_softc *)sc;
302 dbdma_command_t *cmdp;
303 u_int cmd;
304 u_int va;
305 int count, offset;
306
307 cmdp = esc->sc_dmacmd;
308 cmd = datain ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE;
309
310 count = *dmasize;
311
312 if (count / PAGE_SIZE > 32)
313 panic("%s: transfer size >= 128k", device_xname(sc->sc_dev));
314
315 esc->sc_dmaaddr = addr;
316 esc->sc_dmalen = len;
317 esc->sc_dmasize = count;
318
319 va = (u_int)*esc->sc_dmaaddr;
320 offset = va & PGOFSET;
321
322 /* if va is not page-aligned, setup the first page */
323 if (offset != 0) {
324 int rest = PAGE_SIZE - offset; /* the rest of the page */
325
326 if (count > rest) { /* if continues to next page */
327 DBDMA_BUILD(cmdp, cmd, 0, rest, kvtop((void *)va),
328 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER,
329 DBDMA_BRANCH_NEVER);
330 count -= rest;
331 va += rest;
332 cmdp++;
333 }
334 }
335
336 /* now va is page-aligned */
337 while (count > PAGE_SIZE) {
338 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, kvtop((void *)va),
339 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
340 count -= PAGE_SIZE;
341 va += PAGE_SIZE;
342 cmdp++;
343 }
344
345 /* the last page (count <= PAGE_SIZE here) */
346 cmd = datain ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST;
347 DBDMA_BUILD(cmdp, cmd , 0, count, kvtop((void *)va),
348 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
349 cmdp++;
350
351 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0,
352 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
353
354 esc->sc_dma_direction = datain ? D_WRITE : 0;
355
356 return 0;
357 }
358
359 void
esp_dma_go(struct ncr53c9x_softc * sc)360 esp_dma_go(struct ncr53c9x_softc *sc)
361 {
362 struct esp_softc *esc = (struct esp_softc *)sc;
363
364 dbdma_start(esc->sc_dmareg, esc->sc_dmacmd);
365 esc->sc_dmaactive = 1;
366 }
367
368 void
esp_dma_stop(struct ncr53c9x_softc * sc)369 esp_dma_stop(struct ncr53c9x_softc *sc)
370 {
371 struct esp_softc *esc = (struct esp_softc *)sc;
372
373 dbdma_stop(esc->sc_dmareg);
374 esc->sc_dmaactive = 0;
375 }
376
377 int
esp_dma_isactive(struct ncr53c9x_softc * sc)378 esp_dma_isactive(struct ncr53c9x_softc *sc)
379 {
380 struct esp_softc *esc = (struct esp_softc *)sc;
381
382 return esc->sc_dmaactive;
383 }
384
385
386 /*
387 * Pseudo (chained) interrupt from the esp driver to kick the
388 * current running DMA transfer. I am replying on espintr() to
389 * pickup and clean errors for now
390 *
391 * return 1 if it was a DMA continue.
392 */
393 int
espdmaintr(struct esp_softc * sc)394 espdmaintr(struct esp_softc *sc)
395 {
396 struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc;
397 int trans, resid;
398 u_long csr = sc->sc_dma_direction;
399
400 #if 0
401 if (csr & D_ERR_PEND) {
402 DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
403 DMACSR(sc) |= D_INVALIDATE;
404 snprintb(bits, sizeof(bits), DMACSRBITS, csr);
405 printf("%s: error: csr=%s\n", device_xname(nsc->sc_dev), bits);
406 return -1;
407 }
408 #endif
409
410 /* This is an "assertion" :) */
411 if (sc->sc_dmaactive == 0)
412 panic("%s: DMA wasn't active", __func__);
413
414 /* dbdma_flush(sc->sc_dmareg); */
415
416 /* DMA has stopped */
417 dbdma_stop(sc->sc_dmareg);
418 sc->sc_dmaactive = 0;
419
420 if (sc->sc_dmasize == 0) {
421 /* A "Transfer Pad" operation completed */
422 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
423 NCR_READ_REG(nsc, NCR_TCL) |
424 (NCR_READ_REG(nsc, NCR_TCM) << 8),
425 NCR_READ_REG(nsc, NCR_TCL),
426 NCR_READ_REG(nsc, NCR_TCM)));
427 return 0;
428 }
429
430 resid = 0;
431 /*
432 * If a transfer onto the SCSI bus gets interrupted by the device
433 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts
434 * as residual since the ESP counter registers get decremented as
435 * bytes are clocked into the FIFO.
436 */
437 if (!(csr & D_WRITE) &&
438 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
439 NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
440 }
441
442 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
443 /*
444 * `Terminal count' is off, so read the residue
445 * out of the ESP counter registers.
446 */
447 resid += (NCR_READ_REG(nsc, NCR_TCL) |
448 (NCR_READ_REG(nsc, NCR_TCM) << 8) |
449 ((nsc->sc_cfg2 & NCRCFG2_FE)
450 ? (NCR_READ_REG(nsc, NCR_TCH) << 16)
451 : 0));
452
453 if (resid == 0 && sc->sc_dmasize == 65536 &&
454 (nsc->sc_cfg2 & NCRCFG2_FE) == 0)
455 /* A transfer of 64K is encoded as `TCL=TCM=0' */
456 resid = 65536;
457 }
458
459 trans = sc->sc_dmasize - resid;
460 if (trans < 0) { /* transferred < 0 ? */
461 #if 0
462 /*
463 * This situation can happen in perfectly normal operation
464 * if the ESP is reselected while using DMA to select
465 * another target. As such, don't print the warning.
466 */
467 printf("%s: xfer (%d) > req (%d)\n",
468 device_xname(nsc->sc_dev), trans, sc->sc_dmasize);
469 #endif
470 trans = sc->sc_dmasize;
471 }
472
473 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
474 NCR_READ_REG(nsc, NCR_TCL),
475 NCR_READ_REG(nsc, NCR_TCM),
476 (nsc->sc_cfg2 & NCRCFG2_FE)
477 ? NCR_READ_REG(nsc, NCR_TCH) : 0,
478 trans, resid));
479
480 #if 0
481 if (csr & D_WRITE)
482 flushcache(*sc->sc_dmaaddr, trans);
483 #endif
484
485 *sc->sc_dmalen -= trans;
486 *sc->sc_dmaaddr += trans;
487
488 #if 0 /* this is not normal operation just yet */
489 if (*sc->sc_dmalen == 0 ||
490 nsc->sc_phase != nsc->sc_prevphase)
491 return 0;
492
493 /* and again */
494 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
495 return 1;
496 #endif
497 return 0;
498 }
499
500 bool
esp_shutdown(device_t self,int howto)501 esp_shutdown(device_t self, int howto)
502 {
503 struct esp_softc *esc;
504 struct ncr53c9x_softc *sc;
505
506 esc = device_private(self);
507 sc = &esc->sc_ncr53c9x;
508 NCRCMD(sc, NCRCMD_RSTSCSI);
509
510 return true;
511 }
512