1 /* $NetBSD: cuda.c,v 1.30 2023/09/06 08:14:42 macallan Exp $ */
2
3 /*-
4 * Copyright (c) 2006 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.30 2023/09/06 08:14:42 macallan Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/device.h>
36 #include <sys/proc.h>
37 #include <sys/mutex.h>
38
39 #include <sys/bus.h>
40 #include <machine/autoconf.h>
41 #include <machine/pio.h>
42 #include <dev/clock_subr.h>
43 #include <dev/i2c/i2cvar.h>
44
45 #include <macppc/dev/viareg.h>
46 #include <macppc/dev/cudavar.h>
47
48 #include <dev/ofw/openfirm.h>
49 #include <dev/adb/adbvar.h>
50 #include "opt_cuda.h"
51
52 #ifdef CUDA_DEBUG
53 #define DPRINTF printf
54 #else
55 #define DPRINTF while (0) printf
56 #endif
57
58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */
59 #define CUDA_IDLE 0x2 /* the bus is currently idle */
60 #define CUDA_OUT 0x3 /* sending out a command */
61 #define CUDA_IN 0x4 /* receiving data */
62 #define CUDA_POLLING 0x5 /* polling - II only */
63
64 static void cuda_attach(device_t, device_t, void *);
65 static int cuda_match(device_t, struct cfdata *, void *);
66 static void cuda_autopoll(void *, int);
67
68 static int cuda_intr(void *);
69
70 typedef struct _cuda_handler {
71 int (*handler)(void *, int, uint8_t *);
72 void *cookie;
73 } CudaHandler;
74
75 struct cuda_softc {
76 device_t sc_dev;
77 void *sc_ih;
78 CudaHandler sc_handlers[16];
79 struct todr_chip_handle sc_todr;
80 struct adb_bus_accessops sc_adbops;
81 struct i2c_controller sc_i2c;
82 bus_space_tag_t sc_memt;
83 bus_space_handle_t sc_memh;
84 int sc_node;
85 int sc_state;
86 int sc_waiting;
87 int sc_polling;
88 int sc_sent;
89 int sc_out_length;
90 int sc_received;
91 int sc_iic_done;
92 int sc_error;
93 /* time */
94 uint32_t sc_tod;
95 uint32_t sc_autopoll;
96 kcondvar_t sc_todev;
97 kmutex_t sc_todevmtx;
98 /* ADB */
99 void (*sc_adb_handler)(void *, int, uint8_t *);
100 void *sc_adb_cookie;
101 uint32_t sc_i2c_read_len;
102 /* internal buffers */
103 uint8_t sc_in[256];
104 uint8_t sc_out[256];
105 };
106
107 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc),
108 cuda_match, cuda_attach, NULL, NULL);
109
110 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t);
111 static inline uint8_t cuda_read_reg(struct cuda_softc *, int);
112 static void cuda_idle(struct cuda_softc *);
113 static void cuda_tip(struct cuda_softc *);
114 static void cuda_clear_tip(struct cuda_softc *);
115 static void cuda_in(struct cuda_softc *);
116 static void cuda_out(struct cuda_softc *);
117 static void cuda_toggle_ack(struct cuda_softc *);
118 static void cuda_ack_off(struct cuda_softc *);
119 static int cuda_intr_state(struct cuda_softc *);
120
121 static void cuda_init(struct cuda_softc *);
122
123 /*
124 * send a message to Cuda.
125 */
126 /* cookie, flags, length, data */
127 static int cuda_send(void *, int, int, uint8_t *);
128 static void cuda_poll(void *);
129 static void cuda_adb_poll(void *);
130 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *);
131
132 static int cuda_error_handler(void *, int, uint8_t *);
133
134 static int cuda_todr_handler(void *, int, uint8_t *);
135 static int cuda_todr_set(todr_chip_handle_t, struct timeval *);
136 static int cuda_todr_get(todr_chip_handle_t, struct timeval *);
137
138 static int cuda_adb_handler(void *, int, uint8_t *);
139 static void cuda_final(device_t);
140
141 static struct cuda_attach_args *cuda0 = NULL;
142
143 /* ADB bus attachment stuff */
144 static int cuda_adb_send(void *, int, int, int, uint8_t *);
145 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *);
146
147 /* i2c stuff */
148 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
149 void *, size_t, int);
150
151 static int
cuda_match(device_t parent,struct cfdata * cf,void * aux)152 cuda_match(device_t parent, struct cfdata *cf, void *aux)
153 {
154 struct confargs *ca = aux;
155
156 if (ca->ca_nreg < 8)
157 return 0;
158
159 if (ca->ca_nintr < 4)
160 return 0;
161
162 if (strcmp(ca->ca_name, "via-cuda") == 0) {
163 return 10; /* beat adb* at obio? */
164 }
165
166 return 0;
167 }
168
169 static void
cuda_attach(device_t parent,device_t self,void * aux)170 cuda_attach(device_t parent, device_t self, void *aux)
171 {
172 struct confargs *ca = aux;
173 struct cuda_softc *sc = device_private(self);
174 struct i2cbus_attach_args iba;
175 static struct cuda_attach_args caa;
176 prop_dictionary_t dict = device_properties(self);
177 prop_dictionary_t dev;
178 prop_array_t cfg;
179 int irq = ca->ca_intr[0];
180 int node, i, child;
181 char name[32];
182
183 sc->sc_dev = self;
184 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1");
185 if (node)
186 OF_getprop(node, "interrupts", &irq, 4);
187
188 aprint_normal(" irq %d", irq);
189
190 sc->sc_node = ca->ca_node;
191 sc->sc_memt = ca->ca_tag;
192
193 sc->sc_sent = 0;
194 sc->sc_received = 0;
195 sc->sc_waiting = 0;
196 sc->sc_polling = 0;
197 sc->sc_state = CUDA_NOTREADY;
198 sc->sc_error = 0;
199 sc->sc_i2c_read_len = 0;
200
201 cv_init(&sc->sc_todev, "cuda_event");
202 mutex_init(&sc->sc_todevmtx, MUTEX_DEFAULT, IPL_NONE);
203
204 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr,
205 ca->ca_reg[1], 0, &sc->sc_memh) != 0) {
206
207 aprint_normal(": unable to map registers\n");
208 return;
209 }
210 sc->sc_ih = intr_establish_xname(irq, IST_EDGE, IPL_TTY, cuda_intr, sc,
211 device_xname(self));
212 printf("\n");
213
214 for (i = 0; i < 16; i++) {
215 sc->sc_handlers[i].handler = NULL;
216 sc->sc_handlers[i].cookie = NULL;
217 }
218
219 cuda_init(sc);
220
221 /* now attach children */
222 config_interrupts(self, cuda_final);
223 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc);
224 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc);
225
226 child = OF_child(ca->ca_node);
227 while (child != 0) {
228
229 if (OF_getprop(child, "name", name, 32) == 0)
230 continue;
231 if (strncmp(name, "adb", 4) == 0) {
232
233 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc);
234 sc->sc_adbops.cookie = sc;
235 sc->sc_adbops.send = cuda_adb_send;
236 sc->sc_adbops.poll = cuda_adb_poll;
237 sc->sc_adbops.autopoll = cuda_autopoll;
238 sc->sc_adbops.set_handler = cuda_adb_set_handler;
239 config_found(self, &sc->sc_adbops, nadb_print,
240 CFARGS(.iattr = "adb_bus"));
241 } else if (strncmp(name, "rtc", 4) == 0) {
242
243 sc->sc_todr.todr_gettime = cuda_todr_get;
244 sc->sc_todr.todr_settime = cuda_todr_set;
245 sc->sc_todr.cookie = sc;
246 todr_attach(&sc->sc_todr);
247 }
248 child = OF_peer(child);
249 }
250
251 caa.cookie = sc;
252 caa.set_handler = cuda_set_handler;
253 caa.send = cuda_send;
254 caa.poll = cuda_poll;
255 #if notyet
256 config_found(self, &caa, cuda_print, CFARGS_NONE);
257 #endif
258 cfg = prop_array_create();
259 prop_dictionary_set(dict, "i2c-child-devices", cfg);
260 prop_object_release(cfg);
261
262 /* we don't have OF nodes for i2c devices so we have to make our own */
263
264 node = OF_finddevice("/valkyrie");
265 if (node != -1) {
266 dev = prop_dictionary_create();
267 prop_dictionary_set_string(dev, "name", "videopll");
268 prop_dictionary_set_uint32(dev, "addr", 0x50);
269 prop_array_add(cfg, dev);
270 prop_object_release(dev);
271 }
272
273 node = OF_finddevice("/perch");
274 if (node != -1) {
275 dev = prop_dictionary_create();
276 prop_dictionary_set_string(dev, "name", "sgsmix");
277 prop_dictionary_set_uint32(dev, "addr", 0x8a);
278 prop_array_add(cfg, dev);
279 prop_object_release(dev);
280 }
281
282 memset(&iba, 0, sizeof(iba));
283 iba.iba_tag = &sc->sc_i2c;
284 iic_tag_init(&sc->sc_i2c);
285 sc->sc_i2c.ic_cookie = sc;
286 sc->sc_i2c.ic_exec = cuda_i2c_exec;
287 config_found(self, &iba, iicbus_print,
288 CFARGS(.iattr = "i2cbus"));
289
290 if (cuda0 == NULL)
291 cuda0 = &caa;
292 }
293
294 static void
cuda_init(struct cuda_softc * sc)295 cuda_init(struct cuda_softc *sc)
296 {
297 uint8_t reg;
298
299 reg = cuda_read_reg(sc, vDirB);
300 reg |= 0x30; /* register B bits 4 and 5: outputs */
301 cuda_write_reg(sc, vDirB, reg);
302
303 reg = cuda_read_reg(sc, vDirB);
304 reg &= 0xf7; /* register B bit 3: input */
305 cuda_write_reg(sc, vDirB, reg);
306
307 reg = cuda_read_reg(sc, vACR);
308 reg &= ~vSR_OUT; /* make sure SR is set to IN */
309 cuda_write_reg(sc, vACR, reg);
310
311 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
312
313 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
314
315 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
316 cuda_idle(sc); /* set ADB bus state to idle */
317
318 /* sort of a device reset */
319 (void)cuda_read_reg(sc, vSR); /* clear interrupt */
320 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
321 cuda_idle(sc); /* reset state to idle */
322 delay(150);
323 cuda_tip(sc); /* signal start of frame */
324 delay(150);
325 cuda_toggle_ack(sc);
326 delay(150);
327 cuda_clear_tip(sc);
328 delay(150);
329 cuda_idle(sc); /* back to idle state */
330 (void)cuda_read_reg(sc, vSR); /* clear interrupt */
331 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
332 }
333
334 static void
cuda_final(device_t dev)335 cuda_final(device_t dev)
336 {
337 struct cuda_softc *sc = device_private(dev);
338
339 sc->sc_polling = 0;
340 }
341
342 static inline void
cuda_write_reg(struct cuda_softc * sc,int offset,uint8_t value)343 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value)
344 {
345
346 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value);
347 }
348
349 static inline uint8_t
cuda_read_reg(struct cuda_softc * sc,int offset)350 cuda_read_reg(struct cuda_softc *sc, int offset)
351 {
352
353 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset);
354 }
355
356 static int
cuda_set_handler(void * cookie,int type,int (* handler)(void *,int,uint8_t *),void * hcookie)357 cuda_set_handler(void *cookie, int type,
358 int (*handler)(void *, int, uint8_t *), void *hcookie)
359 {
360 struct cuda_softc *sc = cookie;
361 CudaHandler *me;
362
363 if ((type >= 0) && (type < 16)) {
364 me = &sc->sc_handlers[type];
365 me->handler = handler;
366 me->cookie = hcookie;
367 return 0;
368 }
369 return -1;
370 }
371
372 static int
cuda_send(void * cookie,int poll,int length,uint8_t * msg)373 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
374 {
375 struct cuda_softc *sc = cookie;
376 int s;
377
378 DPRINTF("cuda_send %08x\n", (uint32_t)cookie);
379 if (sc->sc_state == CUDA_NOTREADY)
380 return -1;
381
382 s = splhigh();
383
384 if (sc->sc_state == CUDA_IDLE /*&&
385 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) {
386 /* fine */
387 DPRINTF("chip is idle\n");
388 } else {
389 DPRINTF("cuda state is %d\n", sc->sc_state);
390 if (sc->sc_waiting == 0) {
391 sc->sc_waiting = 1;
392 } else {
393 splx(s);
394 return -1;
395 }
396 }
397
398 sc->sc_error = 0;
399 memcpy(sc->sc_out, msg, length);
400 sc->sc_out_length = length;
401 sc->sc_sent = 0;
402
403 if (sc->sc_waiting != 1) {
404
405 delay(150);
406 sc->sc_state = CUDA_OUT;
407 cuda_out(sc);
408 cuda_write_reg(sc, vSR, sc->sc_out[0]);
409 cuda_ack_off(sc);
410 cuda_tip(sc);
411 }
412 sc->sc_waiting = 1;
413
414 if (sc->sc_polling || poll || cold) {
415 cuda_poll(sc);
416 }
417
418 splx(s);
419
420 return 0;
421 }
422
423 static void
cuda_poll(void * cookie)424 cuda_poll(void *cookie)
425 {
426 struct cuda_softc *sc = cookie;
427 int s;
428
429 DPRINTF("polling\n");
430 while ((sc->sc_state != CUDA_IDLE) ||
431 (cuda_intr_state(sc)) ||
432 (sc->sc_waiting == 1)) {
433 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) {
434 s = splhigh();
435 cuda_intr(sc);
436 splx(s);
437 }
438 }
439 }
440
441 static void
cuda_adb_poll(void * cookie)442 cuda_adb_poll(void *cookie)
443 {
444 struct cuda_softc *sc = cookie;
445 int s;
446
447 s = splhigh();
448 cuda_intr(sc);
449 splx(s);
450 }
451
452 static void
cuda_idle(struct cuda_softc * sc)453 cuda_idle(struct cuda_softc *sc)
454 {
455 uint8_t reg;
456
457 reg = cuda_read_reg(sc, vBufB);
458 reg |= (vPB4 | vPB5);
459 cuda_write_reg(sc, vBufB, reg);
460 }
461
462 static void
cuda_tip(struct cuda_softc * sc)463 cuda_tip(struct cuda_softc *sc)
464 {
465 uint8_t reg;
466
467 reg = cuda_read_reg(sc, vBufB);
468 reg &= ~vPB5;
469 cuda_write_reg(sc, vBufB, reg);
470 }
471
472 static void
cuda_clear_tip(struct cuda_softc * sc)473 cuda_clear_tip(struct cuda_softc *sc)
474 {
475 uint8_t reg;
476
477 reg = cuda_read_reg(sc, vBufB);
478 reg |= vPB5;
479 cuda_write_reg(sc, vBufB, reg);
480 }
481
482 static void
cuda_in(struct cuda_softc * sc)483 cuda_in(struct cuda_softc *sc)
484 {
485 uint8_t reg;
486
487 reg = cuda_read_reg(sc, vACR);
488 reg &= ~vSR_OUT;
489 cuda_write_reg(sc, vACR, reg);
490 }
491
492 static void
cuda_out(struct cuda_softc * sc)493 cuda_out(struct cuda_softc *sc)
494 {
495 uint8_t reg;
496
497 reg = cuda_read_reg(sc, vACR);
498 reg |= vSR_OUT;
499 cuda_write_reg(sc, vACR, reg);
500 }
501
502 static void
cuda_toggle_ack(struct cuda_softc * sc)503 cuda_toggle_ack(struct cuda_softc *sc)
504 {
505 uint8_t reg;
506
507 reg = cuda_read_reg(sc, vBufB);
508 reg ^= vPB4;
509 cuda_write_reg(sc, vBufB, reg);
510 }
511
512 static void
cuda_ack_off(struct cuda_softc * sc)513 cuda_ack_off(struct cuda_softc *sc)
514 {
515 uint8_t reg;
516
517 reg = cuda_read_reg(sc, vBufB);
518 reg |= vPB4;
519 cuda_write_reg(sc, vBufB, reg);
520 }
521
522 static int
cuda_intr_state(struct cuda_softc * sc)523 cuda_intr_state(struct cuda_softc *sc)
524 {
525 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
526 }
527
528 static int
cuda_intr(void * arg)529 cuda_intr(void *arg)
530 {
531 struct cuda_softc *sc = arg;
532 int ending, type;
533 uint8_t reg;
534
535 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */
536 DPRINTF("[");
537 if ((reg & 0x80) == 0) {
538 DPRINTF("irq %02x]", reg);
539 return 0; /* No interrupts to process */
540 }
541 DPRINTF(":");
542
543 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */
544
545 switch_start:
546 switch (sc->sc_state) {
547 case CUDA_IDLE:
548 /*
549 * This is an unexpected packet, so grab the first (dummy)
550 * byte, set up the proper vars, and tell the chip we are
551 * starting to receive the packet by setting the TIP bit.
552 */
553 sc->sc_in[1] = cuda_read_reg(sc, vSR);
554 DPRINTF("start: %02x", sc->sc_in[1]);
555 if (cuda_intr_state(sc) == 0) {
556 /* must have been a fake start */
557 DPRINTF(" ... fake start\n");
558 if (sc->sc_waiting) {
559 /* start over */
560 delay(150);
561 sc->sc_state = CUDA_OUT;
562 sc->sc_sent = 0;
563 cuda_out(sc);
564 cuda_write_reg(sc, vSR, sc->sc_out[1]);
565 cuda_ack_off(sc);
566 cuda_tip(sc);
567 }
568 break;
569 }
570
571 cuda_in(sc);
572 cuda_tip(sc);
573
574 sc->sc_received = 1;
575 sc->sc_state = CUDA_IN;
576 DPRINTF(" CUDA_IN");
577 break;
578
579 case CUDA_IN:
580 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
581 DPRINTF(" %02x", sc->sc_in[sc->sc_received]);
582 ending = 0;
583 if (sc->sc_received > 255) {
584 /* bitch only once */
585 if (sc->sc_received == 256) {
586 aprint_error_dev(sc->sc_dev,
587 "input overflow\n");
588 ending = 1;
589 }
590 } else
591 sc->sc_received++;
592 if (sc->sc_received > 3) {
593 if ((sc->sc_in[3] == CMD_IIC) &&
594 (sc->sc_received > (sc->sc_i2c_read_len + 4))) {
595 ending = 1;
596 }
597 }
598
599 /* intr off means this is the last byte (end of frame) */
600 if (cuda_intr_state(sc) == 0) {
601 ending = 1;
602 DPRINTF(".\n");
603 } else {
604 cuda_toggle_ack(sc);
605 }
606
607 if (ending == 1) { /* end of message? */
608
609 sc->sc_in[0] = sc->sc_received - 1;
610
611 /* reset vars and signal the end of this frame */
612 cuda_idle(sc);
613
614 /* check if we have a handler for this message */
615 type = sc->sc_in[1];
616 if ((type >= 0) && (type < 16)) {
617 CudaHandler *me = &sc->sc_handlers[type];
618
619 if (me->handler != NULL) {
620 me->handler(me->cookie,
621 sc->sc_received - 1, &sc->sc_in[1]);
622 } else {
623 aprint_error_dev(sc->sc_dev,
624 "no handler for type %02x\n", type);
625 panic("barf");
626 }
627 }
628
629 DPRINTF("CUDA_IDLE");
630 sc->sc_state = CUDA_IDLE;
631
632 sc->sc_received = 0;
633
634 /*
635 * If there is something waiting to be sent out,
636 * set everything up and send the first byte.
637 */
638 if (sc->sc_waiting == 1) {
639
640 DPRINTF("pending write\n");
641 delay(1500); /* required */
642 sc->sc_sent = 0;
643 sc->sc_state = CUDA_OUT;
644
645 /*
646 * If the interrupt is on, we were too slow
647 * and the chip has already started to send
648 * something to us, so back out of the write
649 * and start a read cycle.
650 */
651 if (cuda_intr_state(sc)) {
652 cuda_in(sc);
653 cuda_idle(sc);
654 sc->sc_sent = 0;
655 sc->sc_state = CUDA_IDLE;
656 sc->sc_received = 0;
657 delay(150);
658 DPRINTF("too slow - incoming message\n");
659 goto switch_start;
660 }
661 /*
662 * If we got here, it's ok to start sending
663 * so load the first byte and tell the chip
664 * we want to send.
665 */
666 DPRINTF("sending ");
667
668 cuda_out(sc);
669 cuda_write_reg(sc, vSR,
670 sc->sc_out[sc->sc_sent]);
671 cuda_ack_off(sc);
672 cuda_tip(sc);
673 }
674 }
675 break;
676
677 case CUDA_OUT:
678 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
679
680 sc->sc_sent++;
681 if (cuda_intr_state(sc)) { /* ADB intr low during write */
682
683 DPRINTF("incoming msg during send\n");
684 cuda_in(sc); /* make sure SR is set to IN */
685 cuda_idle(sc);
686 sc->sc_sent = 0; /* must start all over */
687 sc->sc_state = CUDA_IDLE; /* new state */
688 sc->sc_received = 0;
689 sc->sc_waiting = 1; /* must retry when done with
690 * read */
691 delay(150);
692 goto switch_start; /* process next state right
693 * now */
694 break;
695 }
696 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
697
698 sc->sc_waiting = 0; /* done writing */
699 sc->sc_state = CUDA_IDLE; /* signal bus is idle */
700 cuda_in(sc);
701 cuda_idle(sc);
702 DPRINTF("done sending\n");
703 } else {
704 /* send next byte */
705 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
706 DPRINTF("%02x", sc->sc_out[sc->sc_sent]);
707 cuda_toggle_ack(sc); /* signal byte ready to
708 * shift */
709 }
710 break;
711
712 case CUDA_NOTREADY:
713 DPRINTF("adb: not yet initialized\n");
714 break;
715
716 default:
717 DPRINTF("intr: unknown ADB state\n");
718 break;
719 }
720
721 DPRINTF("]");
722 return 1;
723 }
724
725 static int
cuda_error_handler(void * cookie,int len,uint8_t * data)726 cuda_error_handler(void *cookie, int len, uint8_t *data)
727 {
728 struct cuda_softc *sc = cookie;
729
730 /*
731 * something went wrong
732 * byte 3 seems to be the failed command
733 */
734 sc->sc_error = 1;
735 DPRINTF("cuda error %02x %02x %02x %02x\n", data[0], data[1], data[2], data[3]);
736 cv_signal(&sc->sc_todev);
737 return 0;
738 }
739
740
741 /* real time clock */
742
743 static int
cuda_todr_handler(void * cookie,int len,uint8_t * data)744 cuda_todr_handler(void *cookie, int len, uint8_t *data)
745 {
746 struct cuda_softc *sc = cookie;
747
748 #ifdef CUDA_DEBUG
749 int i;
750 printf("msg: %02x", data[0]);
751 for (i = 1; i < len; i++) {
752 printf(" %02x", data[i]);
753 }
754 printf("\n");
755 #endif
756
757 switch(data[2]) {
758 case CMD_READ_RTC:
759 memcpy(&sc->sc_tod, &data[3], 4);
760 break;
761 case CMD_WRITE_RTC:
762 sc->sc_tod = 0xffffffff;
763 break;
764 case CMD_AUTOPOLL:
765 sc->sc_autopoll = 1;
766 break;
767 case CMD_IIC:
768 sc->sc_iic_done = len;
769 break;
770 }
771 cv_signal(&sc->sc_todev);
772 return 0;
773 }
774
775 #define DIFF19041970 2082844800
776
777 static int
cuda_todr_get(todr_chip_handle_t tch,struct timeval * tvp)778 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp)
779 {
780 struct cuda_softc *sc = tch->cookie;
781 int cnt = 0;
782 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC};
783
784 sc->sc_tod = 0;
785 while (sc->sc_tod == 0) {
786 cuda_send(sc, 0, 2, cmd);
787
788 while ((sc->sc_tod == 0) && (cnt < 10)) {
789 mutex_enter(&sc->sc_todevmtx);
790 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz);
791 mutex_exit(&sc->sc_todevmtx);
792
793 cnt++;
794 }
795
796 if (sc->sc_tod == 0) {
797 aprint_error_dev(sc->sc_dev,
798 "unable to read a sane RTC value\n");
799 return EIO;
800 }
801 if ((sc->sc_tod > 0xf0000000UL) ||
802 (sc->sc_tod < DIFF19041970)) {
803 /* huh? try again */
804 sc->sc_tod = 0;
805 aprint_verbose_dev(sc->sc_dev,
806 "got garbage reading RTC, trying again\n");
807 }
808 }
809
810 tvp->tv_sec = sc->sc_tod - DIFF19041970;
811 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec);
812 tvp->tv_usec = 0;
813 return 0;
814 }
815
816 static int
cuda_todr_set(todr_chip_handle_t tch,struct timeval * tvp)817 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp)
818 {
819 struct cuda_softc *sc = tch->cookie;
820 uint32_t sec;
821 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
822
823 sec = tvp->tv_sec + DIFF19041970;
824 memcpy(&cmd[2], &sec, 4);
825 sc->sc_tod = 0;
826 if (cuda_send(sc, 0, 6, cmd) == 0) {
827 while (sc->sc_tod == 0) {
828 mutex_enter(&sc->sc_todevmtx);
829 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz);
830 mutex_exit(&sc->sc_todevmtx);
831 }
832 return 0;
833 }
834 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__);
835 return -1;
836
837 }
838
839 /* poweroff and reboot */
840
841 void
cuda_poweroff(void)842 cuda_poweroff(void)
843 {
844 struct cuda_softc *sc;
845 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF};
846
847 if (cuda0 == NULL)
848 return;
849 sc = cuda0->cookie;
850 sc->sc_polling = 1;
851 cuda0->poll(sc);
852 if (cuda0->send(sc, 1, 2, cmd) == 0)
853 while (1);
854 }
855
856 void
cuda_restart(void)857 cuda_restart(void)
858 {
859 struct cuda_softc *sc;
860 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET};
861
862 if (cuda0 == NULL)
863 return;
864 sc = cuda0->cookie;
865 sc->sc_polling = 1;
866 cuda0->poll(sc);
867 if (cuda0->send(sc, 1, 2, cmd) == 0)
868 while (1);
869 }
870
871 /* ADB message handling */
872
873 static void
cuda_autopoll(void * cookie,int flag)874 cuda_autopoll(void *cookie, int flag)
875 {
876 struct cuda_softc *sc = cookie;
877 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)};
878
879 if (cmd[2] == sc->sc_autopoll)
880 return;
881
882 sc->sc_autopoll = -1;
883 cuda_send(sc, 0, 3, cmd);
884 while(sc->sc_autopoll == -1) {
885 if (sc->sc_polling || cold) {
886 cuda_poll(sc);
887 } else {
888 mutex_enter(&sc->sc_todevmtx);
889 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz);
890 mutex_exit(&sc->sc_todevmtx);
891 }
892 }
893 }
894
895 static int
cuda_adb_handler(void * cookie,int len,uint8_t * data)896 cuda_adb_handler(void *cookie, int len, uint8_t *data)
897 {
898 struct cuda_softc *sc = cookie;
899
900 if (sc->sc_adb_handler != NULL) {
901 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1,
902 &data[1]);
903 return 0;
904 }
905 return -1;
906 }
907
908 static int
cuda_adb_send(void * cookie,int poll,int command,int len,uint8_t * data)909 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data)
910 {
911 struct cuda_softc *sc = cookie;
912 int i, s = 0;
913 uint8_t packet[16];
914
915 /* construct an ADB command packet and send it */
916 packet[0] = CUDA_ADB;
917 packet[1] = command;
918 for (i = 0; i < len; i++)
919 packet[i + 2] = data[i];
920 if (poll || cold) {
921 s = splhigh();
922 cuda_poll(sc);
923 }
924 cuda_send(sc, poll, len + 2, packet);
925 if (poll || cold) {
926 cuda_poll(sc);
927 splx(s);
928 }
929 return 0;
930 }
931
932 static int
cuda_adb_set_handler(void * cookie,void (* handler)(void *,int,uint8_t *),void * hcookie)933 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *),
934 void *hcookie)
935 {
936 struct cuda_softc *sc = cookie;
937
938 /* register a callback for incoming ADB messages */
939 sc->sc_adb_handler = handler;
940 sc->sc_adb_cookie = hcookie;
941 return 0;
942 }
943
944 /* i2c message handling */
945
946 static int
cuda_i2c_exec(void * cookie,i2c_op_t op,i2c_addr_t addr,const void * _send,size_t send_len,void * _recv,size_t recv_len,int flags)947 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send,
948 size_t send_len, void *_recv, size_t recv_len, int flags)
949 {
950 struct cuda_softc *sc = cookie;
951 const uint8_t *send = _send;
952 uint8_t *recv = _recv;
953 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC};
954
955 DPRINTF("cuda_i2c_exec(%02x)\n", addr);
956 command[2] = addr;
957
958 /* Copy command and output data bytes, if any, to buffer */
959 if (send_len > 0)
960 memcpy(&command[3], send, uimin((int)send_len, 12));
961 else if (I2C_OP_READ_P(op) && (recv_len == 0)) {
962 /*
963 * If no data bytes in either direction, it's a "quick"
964 * i2c operation. We don't know how to do a quick_read
965 * since that requires us to set the low bit of the
966 * address byte after it has been left-shifted.
967 */
968 sc->sc_error = 0;
969 return -1;
970 }
971
972 sc->sc_iic_done = 0;
973 cuda_send(sc, sc->sc_polling, send_len + 3, command);
974
975 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) {
976 if (sc->sc_polling || cold) {
977 cuda_poll(sc);
978 } else {
979 mutex_enter(&sc->sc_todevmtx);
980 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz);
981 mutex_exit(&sc->sc_todevmtx);
982 }
983 }
984
985 if (sc->sc_error) {
986 sc->sc_error = 0;
987 aprint_error_dev(sc->sc_dev, "error doing I2C\n");
988 return -1;
989 }
990
991 /* see if we're supposed to do a read */
992 if (recv_len > 0) {
993 sc->sc_iic_done = 0;
994 command[2] |= 1;
995 command[3] = 0;
996
997 /*
998 * XXX we need to do something to limit the size of the answer
999 * - apparently the chip keeps sending until we tell it to stop
1000 */
1001 sc->sc_i2c_read_len = recv_len;
1002 DPRINTF("rcv_len: %d\n", recv_len);
1003 cuda_send(sc, sc->sc_polling, 3, command);
1004 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) {
1005 if (sc->sc_polling || cold) {
1006 cuda_poll(sc);
1007 } else {
1008 mutex_enter(&sc->sc_todevmtx);
1009 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz);
1010 mutex_exit(&sc->sc_todevmtx);
1011 }
1012 }
1013
1014 if (sc->sc_error) {
1015 aprint_error_dev(sc->sc_dev,
1016 "error trying to read from I2C\n");
1017 sc->sc_error = 0;
1018 return -1;
1019 }
1020 }
1021
1022 DPRINTF("received: %d\n", sc->sc_iic_done);
1023 if ((sc->sc_iic_done > 3) && (recv_len > 0)) {
1024 int rlen;
1025
1026 /* we got an answer */
1027 rlen = uimin(sc->sc_iic_done - 3, recv_len);
1028 memcpy(recv, &sc->sc_in[4], rlen);
1029 #ifdef CUDA_DEBUG
1030 {
1031 int i;
1032 printf("ret:");
1033 for (i = 0; i < rlen; i++)
1034 printf(" %02x", recv[i]);
1035 printf("\n");
1036 }
1037 #endif
1038 return rlen;
1039 }
1040 return 0;
1041 }
1042