1 /* $NetBSD: mem.c,v 1.2 2022/09/29 06:39:58 skrll Exp $ */
2
3 /* $OpenBSD: mem.c,v 1.30 2007/09/22 16:21:32 krw Exp $ */
4 /*
5 * Copyright (c) 1998-2004 Michael Shalayeff
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 */
29 /*
30 * Copyright (c) 1991,1992,1994, The University of Utah and
31 * the Computer Systems Laboratory (CSL). All rights reserved.
32 *
33 * Subject to your agreements with CMU,
34 * permission to use, copy, modify and distribute this software and its
35 * documentation is hereby granted, provided that both the copyright
36 * notice and this permission notice appear in all copies of the
37 * software, derivative works or modified versions, and any portions
38 * thereof, and that both notices appear in supporting documentation.
39 *
40 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
41 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
42 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
43 *
44 * CSL requests users of this software to return to csl-dist@cs.utah.edu any
45 * improvements that they make and grant CSL redistribution rights.
46 *
47 * Utah $Hdr: mem.c 1.9 94/12/16$
48 */
49 /*
50 * Mach Operating System
51 * Copyright (c) 1992 Carnegie Mellon University
52 * All Rights Reserved.
53 *
54 * Permission to use, copy, modify and distribute this software and its
55 * documentation is hereby granted, provided that both the copyright
56 * notice and this permission notice appear in all copies of the
57 * software, derivative works or modified versions, and any portions
58 * thereof, and that both notices appear in supporting documentation.
59 *
60 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
61 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
62 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
63 *
64 * Carnegie Mellon requests users of this software to return to
65 *
66 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
67 * School of Computer Science
68 * Carnegie Mellon University
69 * Pittsburgh PA 15213-3890
70 *
71 * any improvements or extensions that they make and grant Carnegie Mellon
72 * the rights to redistribute these changes.
73 */
74
75 #include <sys/cdefs.h>
76 __KERNEL_RCSID(0, "$NetBSD: mem.c,v 1.2 2022/09/29 06:39:58 skrll Exp $");
77
78 #include <sys/param.h>
79 #include <sys/systm.h>
80 #include <sys/buf.h>
81 #include <sys/conf.h>
82 #include <sys/proc.h>
83 #include <sys/uio.h>
84 #include <sys/types.h>
85 #include <sys/device.h>
86 #include <sys/errno.h>
87 #include <sys/ioctl.h>
88 #include <sys/file.h>
89 #include <sys/bus.h>
90 #include <sys/mutex.h>
91
92 #include <uvm/uvm.h>
93
94 #include <machine/iomod.h>
95 #include <machine/autoconf.h>
96 #include <machine/pmap.h>
97
98 #include <hppa/hppa/machdep.h>
99 #include <hppa/dev/cpudevs.h>
100 #include <hppa/dev/viper.h>
101
102 /* registers on the PCXL2 MIOC */
103 struct l2_mioc {
104 uint32_t pad[0x20]; /* 0x000 */
105 uint32_t mioc_control; /* 0x080 MIOC control bits */
106 uint32_t mioc_status; /* 0x084 MIOC status bits */
107 uint32_t pad1[6]; /* 0x088 */
108 uint32_t sltcv; /* 0x0a0 L2 cache control */
109 #define SLTCV_AVWL 0x00002000 /* extra cycle for addr valid write low */
110 #define SLTCV_UP4COUT 0x00001000 /* update cache on CPU castouts */
111 #define SLTCV_EDCEN 0x08000000 /* enable error correction */
112 #define SLTCV_EDTAG 0x10000000 /* enable diagtag */
113 #define SLTCV_CHKTP 0x20000000 /* enable parity checking */
114 #define SLTCV_LOWPWR 0x40000000 /* low power mode */
115 #define SLTCV_ENABLE 0x80000000 /* enable L2 cache */
116 #define SLTCV_BITS "\020\15avwl\16up4cout\24edcen\25edtag\26chktp\27lowpwr\30l2ena"
117 uint32_t tagmask; /* 0x0a4 L2 cache tag mask */
118 uint32_t diagtag; /* 0x0a8 L2 invalidates tag */
119 uint32_t sltestat; /* 0x0ac L2 last logged tag read */
120 uint32_t slteadd; /* 0x0b0 L2 pa of -- " -- */
121 uint32_t pad2[3]; /* 0x0b4 */
122 uint32_t mtcv; /* 0x0c0 MIOC timings */
123 uint32_t ref; /* 0x0cc MIOC refresh timings */
124 uint32_t pad3[4]; /* 0x0d0 */
125 uint32_t mderradd; /* 0x0e0 addr of most evil mem error */
126 uint32_t pad4; /* 0x0e4 */
127 uint32_t dmaerr; /* 0x0e8 addr of most evil dma error */
128 uint32_t dioerr; /* 0x0ec addr of most evil dio error */
129 uint32_t gsc_timeout; /* 0x0f0 1-compl of GSC timeout delay */
130 uint32_t hidmamem; /* 0x0f4 amount of phys mem installed */
131 uint32_t pad5[2]; /* 0x0f8 */
132 uint32_t memcomp[16]; /* 0x100 memory address comparators */
133 uint32_t memmask[16]; /* 0x140 masks for -- " -- */
134 uint32_t memtest; /* 0x180 test address decoding */
135 uint32_t pad6[0xf]; /* 0x184 */
136 uint32_t outchk; /* 0x1c0 address decoding output */
137 uint32_t pad7[0x168]; /* 0x200 */
138 uint32_t gsc15x_config; /* 0x7a0 writev enable */
139 };
140
141 struct mem_softc {
142 device_t sc_dev;
143
144 volatile struct vi_trs *sc_vp;
145 volatile struct l2_mioc *sc_l2;
146 };
147
148 int memmatch(device_t, cfdata_t, void *);
149 void memattach(device_t, device_t, void *);
150
151 CFATTACH_DECL_NEW(mem, sizeof(struct mem_softc), memmatch, memattach,
152 NULL, NULL);
153
154 int
memmatch(device_t parent,cfdata_t cf,void * aux)155 memmatch(device_t parent, cfdata_t cf, void *aux)
156 {
157 struct confargs *ca = aux;
158
159 if (ca->ca_type.iodc_type != HPPA_TYPE_MEMORY ||
160 ca->ca_type.iodc_sv_model != HPPA_MEMORY_PDEP)
161 return 0;
162 return 1;
163 }
164
165 void
memattach(device_t parent,device_t self,void * aux)166 memattach(device_t parent, device_t self, void *aux)
167 {
168 struct pdc_iodc_minit pdc_minit;
169 struct confargs *ca = aux;
170 struct mem_softc *sc = device_private(self);
171 int err, pagezero_cookie;
172 char bits[128];
173
174 sc->sc_dev = self;
175
176 aprint_normal(":");
177
178 pagezero_cookie = hppa_pagezero_map();
179
180 /* XXX check if we are dealing w/ Viper */
181 if (ca->ca_hpa == (hppa_hpa_t)VIPER_HPA) {
182
183 sc->sc_vp = (struct vi_trs *)
184 &((struct iomod *)ca->ca_hpa)->priv_trs;
185
186 /* XXX other values seem to blow it up */
187 if (sc->sc_vp->vi_status.hw_rev == 0) {
188 uint32_t vic;
189 int s, settimeout;
190
191 switch (cpu_modelno) {
192 case HPPA_BOARD_HP715_33:
193 case HPPA_BOARD_HP715S_33:
194 case HPPA_BOARD_HP715T_33:
195 case HPPA_BOARD_HP715_50:
196 case HPPA_BOARD_HP715S_50:
197 case HPPA_BOARD_HP715T_50:
198 case HPPA_BOARD_HP715_75:
199 case HPPA_BOARD_HP725_50:
200 case HPPA_BOARD_HP725_75:
201 settimeout = 1;
202 break;
203 default:
204 settimeout = 0;
205 break;
206 }
207 if (device_cfdata(self)->cf_flags & 1)
208 settimeout = !settimeout;
209
210 snprintb(bits, sizeof(bits), VIPER_BITS, VI_CTRL);
211 aprint_normal(" viper rev %x, ctrl %s",
212 sc->sc_vp->vi_status.hw_rev, bits);
213
214 s = splhigh();
215 vic = VI_CTRL;
216 ((struct vi_ctrl *)&vic)->core_den = 0;
217 ((struct vi_ctrl *)&vic)->sgc0_den = 0;
218 ((struct vi_ctrl *)&vic)->sgc1_den = 0;
219 ((struct vi_ctrl *)&vic)->eisa_den = 1;
220 ((struct vi_ctrl *)&vic)->core_prf = 1;
221
222 if (settimeout &&
223 ((struct vi_ctrl *)&vic)->vsc_tout == 0)
224 /* clks */
225 ((struct vi_ctrl *)&vic)->vsc_tout = 850;
226
227 sc->sc_vp->vi_control = vic;
228
229 __asm __volatile("stwas %1, 0(%0)"
230 :: "r" (&VI_CTRL), "r" (vic) : "memory");
231 splx(s);
232 #ifdef DEBUG
233 snprintb(bits, sizeof(bits), VIPER_BITS, VI_CTRL);
234 printf (" >> %s", bits);
235 #endif
236 } else
237 sc->sc_vp = NULL;
238 } else
239 sc->sc_vp = NULL;
240
241 err = pdcproc_iodc_ninit(&pdc_minit, ca->ca_hpa, PAGE0->imm_spa_size);
242 if (err < 0)
243 pdc_minit.max_spa = PAGE0->imm_max_mem;
244
245 hppa_pagezero_unmap(pagezero_cookie);
246
247 aprint_normal(" size %d", pdc_minit.max_spa / (1024*1024));
248 if (pdc_minit.max_spa % (1024*1024))
249 aprint_normal(".%d", pdc_minit.max_spa % (1024*1024));
250 aprint_normal("MB");
251
252 /* L2 cache controller is a part of the memory controller on PCXL2 */
253 if (hppa_cpu_info->hci_cputype == hpcxl2) {
254 sc->sc_l2 = (struct l2_mioc *)ca->ca_hpa;
255 #ifdef DEBUG
256 snprintb(bits, sizeof(bits), SLTCV_BITS, sc->sc_l2->sltcv);
257 printf(", sltcv %s", bits);
258 #endif
259 /* sc->sc_l2->sltcv |= SLTCV_UP4COUT; */
260 if (sc->sc_l2->sltcv & SLTCV_ENABLE) {
261 uint32_t tagmask = sc->sc_l2->tagmask >> 20;
262 aprint_normal(", %dMB L2 cache", tagmask + 1);
263 }
264 }
265 aprint_normal("\n");
266 }
267
268 void
viper_setintrwnd(uint32_t mask)269 viper_setintrwnd(uint32_t mask)
270 {
271 device_t dv;
272 struct mem_softc *sc;
273
274 dv = device_find_by_driver_unit("mem", 0);
275 sc = device_private(dv);
276
277 if (sc->sc_vp)
278 sc->sc_vp->vi_intrwd;
279 }
280
281 void
viper_eisa_en(void)282 viper_eisa_en(void)
283 {
284 device_t dv;
285 struct mem_softc *sc;
286
287 dv = device_find_by_driver_unit("mem", 0);
288 sc = device_private(dv);
289
290 if (sc->sc_vp) {
291 int pagezero_cookie;
292 uint32_t vic;
293 int s;
294
295 pagezero_cookie = hppa_pagezero_map();
296 s = splhigh();
297 vic = VI_CTRL;
298 ((struct vi_ctrl *)&vic)->eisa_den = 0;
299 sc->sc_vp->vi_control = vic;
300 __asm __volatile("stwas %1, 0(%0)"
301 :: "r" (&VI_CTRL), "r" (vic) : "memory");
302 splx(s);
303 hppa_pagezero_unmap(pagezero_cookie);
304 }
305 }
306