1 /*
2 * Copyright (c) 2001 HAMAJIMA Katsuomi. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: vrdcu.c,v 1.8 2015/06/11 08:22:09 matt Exp $");
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/device.h>
32
33 #include <uvm/uvm_extern.h>
34
35 #include <machine/cpu.h>
36 #include <machine/bus.h>
37 #include <machine/bus_dma_hpcmips.h>
38
39 #include <hpcmips/vr/vripif.h>
40 #include <hpcmips/vr/dcureg.h>
41
42 #ifdef VRDCU_DEBUG
43 int vrdcu_debug = VRDCU_DEBUG;
44 #define DPRINTFN(n,x) if (vrdcu_debug>(n)) printf x;
45 #else
46 #define DPRINTFN(n,x)
47 #endif
48
49 struct vrdcu_softc {
50 bus_space_tag_t sc_iot;
51 bus_space_handle_t sc_ioh;
52 struct vrdcu_chipset_tag sc_chipset;
53 int sc_status; /* DMA status */
54 };
55
56 int vrdcu_match(device_t, cfdata_t, void *);
57 void vrdcu_attach(device_t, device_t, void *);
58
59 CFATTACH_DECL_NEW(vrdcu, sizeof(struct vrdcu_softc),
60 vrdcu_match, vrdcu_attach, NULL, NULL);
61
62 int vrdcu_enable_aiuin(vrdcu_chipset_tag_t);
63 int vrdcu_enable_aiuout(vrdcu_chipset_tag_t);
64 int vrdcu_enable_fir(vrdcu_chipset_tag_t);
65 void vrdcu_disable(vrdcu_chipset_tag_t);
66 void vrdcu_fir_direction(vrdcu_chipset_tag_t, int);
67 int _vrdcu_dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
68 bus_size_t, bus_dma_segment_t *, int, int *, int);
69
70 struct bus_dma_tag vrdcu_bus_dma_tag = {
71 NULL,
72 {
73 _hpcmips_bd_map_create,
74 _hpcmips_bd_map_destroy,
75 _hpcmips_bd_map_load,
76 _hpcmips_bd_map_load_mbuf,
77 _hpcmips_bd_map_load_uio,
78 _hpcmips_bd_map_load_raw,
79 _hpcmips_bd_map_unload,
80 _hpcmips_bd_map_sync,
81 _vrdcu_dmamem_alloc,
82 _hpcmips_bd_mem_free,
83 _hpcmips_bd_mem_map,
84 _hpcmips_bd_mem_unmap,
85 _hpcmips_bd_mem_mmap,
86 },
87 };
88
89 int
vrdcu_match(device_t parent,cfdata_t cf,void * aux)90 vrdcu_match(device_t parent, cfdata_t cf, void *aux)
91 {
92 return 2; /* 1st attach group of vrip */
93 }
94
95 void
vrdcu_attach(device_t parent,device_t self,void * aux)96 vrdcu_attach(device_t parent, device_t self, void *aux)
97 {
98 struct vrip_attach_args *va = aux;
99 struct vrdcu_softc *sc = device_private(self);
100
101 sc->sc_iot = va->va_iot;
102 sc->sc_chipset.dc_sc = sc;
103 sc->sc_chipset.dc_enable_aiuin = vrdcu_enable_aiuin;
104 sc->sc_chipset.dc_enable_aiuout = vrdcu_enable_aiuout;
105 sc->sc_chipset.dc_enable_fir = vrdcu_enable_fir;
106 sc->sc_chipset.dc_disable = vrdcu_disable;
107 sc->sc_chipset.dc_fir_direction = vrdcu_fir_direction;
108
109 if (bus_space_map(sc->sc_iot, va->va_addr, va->va_size,
110 0 /* no flags */, &sc->sc_ioh)) {
111 printf("%s: can't map i/o space\n", device_xname(self));
112 return;
113 }
114 printf("\n");
115 vrip_register_dcu(va->va_vc, &sc->sc_chipset);
116
117 sc->sc_status = DMASDS;
118 /* reset DCU */
119 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMARST_REG_W, DMARST);
120 }
121
122 int
vrdcu_enable_aiuin(vrdcu_chipset_tag_t dc)123 vrdcu_enable_aiuin(vrdcu_chipset_tag_t dc)
124 {
125 struct vrdcu_softc *sc = dc->dc_sc;
126 int mask;
127
128 DPRINTFN(1, ("vrdcu_enable_aiuin\n"));
129
130 if (sc->sc_status){
131 mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W);
132 if (mask & DMAMSKAIN) {
133 DPRINTFN(0, ("vrdcu_enable_aiuin: already enabled\n"));
134 return 0;
135 } else {
136 DPRINTFN(0, ("vrdcu_enable_aiuin: device busy\n"));
137 return EBUSY;
138 }
139 }
140 sc->sc_status = DMASEN;
141 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKAIN);
142 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status);
143 return 0;
144 }
145
146 int
vrdcu_enable_aiuout(vrdcu_chipset_tag_t dc)147 vrdcu_enable_aiuout(vrdcu_chipset_tag_t dc)
148 {
149 struct vrdcu_softc *sc = dc->dc_sc;
150 int mask;
151
152 DPRINTFN(1, ("vrdcu_enable_aiuout\n"));
153
154 if (sc->sc_status){
155 mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W);
156 if (mask & DMAMSKAOUT) {
157 DPRINTFN(0, ("vrdcu_enable_aiuout: already enabled\n"));
158 return 0;
159 } else {
160 DPRINTFN(0, ("vrdcu_enable_aiuout: device busy\n"));
161 return EBUSY;
162 }
163 }
164 sc->sc_status = DMASEN;
165 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKAOUT);
166 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status);
167 return 0;
168 }
169
170 int
vrdcu_enable_fir(vrdcu_chipset_tag_t dc)171 vrdcu_enable_fir(vrdcu_chipset_tag_t dc)
172 {
173 struct vrdcu_softc *sc = dc->dc_sc;
174 int mask;
175
176 DPRINTFN(1, ("vrdcu_enable_fir\n"));
177
178 if (sc->sc_status){
179 mask = bus_space_read_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W);
180 if (mask & DMAMSKFOUT) {
181 DPRINTFN(0, ("vrdcu_enable_fir: already enabled\n"));
182 return 0;
183 } else {
184 DPRINTFN(0, ("vrdcu_enable_fir: device busy\n"));
185 return EBUSY;
186 }
187 }
188 sc->sc_status = DMASEN;
189 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMAMSK_REG_W, DMAMSKFOUT);
190 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status);
191 return 0;
192 }
193
194 void
vrdcu_disable(vrdcu_chipset_tag_t dc)195 vrdcu_disable(vrdcu_chipset_tag_t dc)
196 {
197 struct vrdcu_softc *sc = dc->dc_sc;
198
199 DPRINTFN(1, ("vrdcu_disable\n"));
200
201 sc->sc_status = DMASDS;
202 bus_space_write_2(sc->sc_iot, sc->sc_ioh, DMASEN_REG_W, sc->sc_status);
203 }
204
205 void
vrdcu_fir_direction(vrdcu_chipset_tag_t dc,int dir)206 vrdcu_fir_direction(vrdcu_chipset_tag_t dc, int dir)
207 {
208 struct vrdcu_softc *sc = dc->dc_sc;
209
210 DPRINTFN(1, ("vrdcu_fir_direction: dir %d\n", dir));
211
212 bus_space_write_2(sc->sc_iot, sc->sc_ioh,
213 DMATD_REG_W, dir & DMATDMASK);
214 }
215
216 int
_vrdcu_dmamem_alloc(bus_dma_tag_t t,bus_size_t size,bus_size_t alignment,bus_size_t boundary,bus_dma_segment_t * segs,int nsegs,int * rsegs,int flags)217 _vrdcu_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment,
218 bus_size_t boundary, bus_dma_segment_t *segs,
219 int nsegs, int *rsegs, int flags)
220 {
221 paddr_t high;
222
223 DPRINTFN(1, ("_vrdcu_dmamem_alloc\n"));
224
225 high = (pmap_limits.avail_end < VRDMAAU_BOUNCE_THRESHOLD ?
226 pmap_limits.avail_end : VRDMAAU_BOUNCE_THRESHOLD) - PAGE_SIZE;
227 alignment = alignment > VRDMAAU_ALIGNMENT ?
228 alignment : VRDMAAU_ALIGNMENT;
229
230 return _hpcmips_bd_mem_alloc_range(t, size, alignment, boundary,
231 segs, nsegs, rsegs, flags,
232 pmap_limits.avail_start, high);
233 }
234