xref: /netbsd-src/sys/arch/hpcmips/dev/mq200debug.c (revision 2c375dfeefc2fa4344bdc70d51780afd037cdb6c)
1 /*	$NetBSD: mq200debug.c,v 1.7 2024/07/05 19:28:35 andvar Exp $	*/
2 
3 /*-
4  * Copyright (c) 2001 TAKEMURA Shin
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  *    derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  */
31 
32 #ifdef _KERNEL
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: mq200debug.c,v 1.7 2024/07/05 19:28:35 andvar Exp $");
35 
36 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/systm.h>
39 #include <sys/device.h>
40 #else
41 #include <stdio.h>
42 #endif
43 #include <sys/types.h>
44 
45 #include <machine/platid.h>
46 #include <machine/platid_mask.h>
47 
48 #include "opt_mq200.h"
49 #include "mq200var.h"
50 #include "mq200reg.h"
51 #include "mq200priv.h"
52 
53 #define ENABLE(b)	((b)?"enable":"disable")
54 
55 const char *mq200_clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" };
56 
57 #ifdef MQ200_DEBUG
58 
59 void
mq200_dump_pll(struct mq200_softc * sc)60 mq200_dump_pll(struct mq200_softc *sc)
61 {
62 	int n, m;
63 	u_int32_t reg, pm00r;
64 	int clocks[4];
65 	int memclock, geclock;
66 	static const char *clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" };
67 	static const char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" };
68 	static int fd_vals[] = { 10, 15, 25, 35, 45, 55, 65 };
69 #define FIXEDFLOAT1000(a)	(a)/1000, (a)%1000
70 
71 	/* PM00R */
72 	pm00r = mq200_read(sc, MQ200_PMCR);
73 	geclock = (pm00r&MQ200_PMC_GE_CLK_MASK)>>MQ200_PMC_GE_CLK_SHIFT;
74 
75 	/* MM01R */
76 	reg = mq200_read(sc, MQ200_MMR(1));
77 	memclock = (reg & MQ200_MM01_CLK_PLL2) ? 2 : 1;
78 
79 	/* bus clock */
80 	clocks[0] = 0;
81 
82 	/* PLL1 */
83 	reg = mq200_read(sc, MQ200_DCMISCR);
84 	m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;
85 	n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) |
86 	    ((pm00r & MQ200_PMC_PLL1_N) << MQ200_PMC_PLL1_N_SHIFT));
87 	n <<= ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT);
88 	printf("  PLL1:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
89 	    FIXEDFLOAT1000(sc->sc_baseclock*m/n),
90 	    reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
91 	clocks[1] = sc->sc_baseclock*m/n;
92 
93 	/* PLL2 */
94 	if (pm00r & MQ200_PMC_PLL2_ENABLE) {
95 		reg = mq200_read(sc, MQ200_PLL2R);
96 		m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;
97 		n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) +1) <<
98 		    ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));
99 		clocks[2] = sc->sc_baseclock*m/n;
100 		printf("  PLL2:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
101 		    FIXEDFLOAT1000(sc->sc_baseclock*m/n),
102 		    reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
103 	} else {
104 		printf("  PLL2: disable\n");
105 		clocks[2] = 0;
106 	}
107 
108 	/* PLL3 */
109 	if (pm00r & MQ200_PMC_PLL3_ENABLE) {
110 		reg = mq200_read(sc, MQ200_PLL3R);
111 		m = (((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1);
112 		n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) <<
113 		    ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));
114 		clocks[3] = sc->sc_baseclock*m/n;
115 		printf("  PLL3:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
116 		    FIXEDFLOAT1000(sc->sc_baseclock*m/n),
117 		    reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
118 	} else {
119 		printf("  PLL3: disable\n");
120 		clocks[3] = 0;
121 	}
122 
123 	printf("   MEM:%3d.%03dMHz(%s)\n",
124 	    FIXEDFLOAT1000(clocks[memclock]),
125 	    clknames[memclock]);
126 	printf("    GE:%3d.%03dMHz(%s)\n",
127 	    FIXEDFLOAT1000(clocks[geclock]),
128 	    clknames[geclock]);
129 
130 	/* GC1 */
131 	reg = mq200_read(sc, MQ200_GCCR(MQ200_GC1));
132 	if (reg & MQ200_GCC_ENABLE) {
133 		int fd, sd, rc;
134 		rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;
135 		fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;
136 		sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;
137 		printf("   GC1:%3d.%03dMHz(%s/%s/%d)",
138 		    FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd),
139 		    clknames[rc], fd_names[fd], sd);
140 		/* GC01R */
141 		reg = mq200_read(sc, MQ200_GC1CRTCR);
142 		if (reg&MQ200_GC1CRTC_DACEN)
143 			printf(", CRT");
144 		reg = mq200_read(sc, MQ200_FPCR);
145 		if ((reg & MQ200_FPC_ENABLE) && !(reg & MQ200_FPC_GC2))
146 			printf(", LCD");
147 		printf("\n");
148 	} else {
149 		printf("   GC1: disable\n");
150 	}
151 
152 	/* GC2 */
153 	reg = mq200_read(sc, MQ200_GCCR(MQ200_GC2));
154 	if (reg & MQ200_GCC_ENABLE) {
155 		int fd, sd, rc;
156 		rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;
157 		fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;
158 		sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;
159 		printf("   GC2:%3d.%03dMHz(%s/%s/%d)",
160 		    FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd),
161 		    clknames[rc], fd_names[fd], sd);
162 		reg = mq200_read(sc, MQ200_FPCR);
163 		if ((reg & MQ200_FPC_ENABLE) && (reg & MQ200_FPC_GC2))
164 			printf(", FP");
165 		printf("\n");
166 	} else {
167 		printf("   GC2: disable\n");
168 	}
169 }
170 
171 struct {
172 	const char *name;
173 	u_int32_t base;
174 	int start, end;
175 } regs[] = {
176 	{ "GC",	MQ200_GCR(0),	0x00,	0x13 },
177 	{ "GC",	MQ200_GCR(0),	0x20,	0x33 },
178 	{ "FP",	MQ200_FP,	0x00,	0x0f },
179 	{ "CC",	MQ200_CC,	0x00,	0x01 },
180 	{ "PC",	MQ200_PC,	0x00,	0x05 },
181 	{ "MM",	MQ200_MM,	0x00,	0x04 },
182 	{ "DC",	MQ200_DC,	0x00,	0x03 },
183 	{ "PM",	MQ200_PM,	0x00,	0x03 },
184 	{ "PM",	MQ200_PM,	0x06,	0x07 },
185 	{ "IN",	MQ200_IN,	0x00,	0x03 },
186 };
187 
188 char *
mq200_regname(struct mq200_softc * sc,int offset,char * buf,int bufsize)189 mq200_regname(struct mq200_softc *sc, int offset, char *buf, int bufsize)
190 {
191 	int i;
192 
193 	for (i = 0; i < sizeof(regs)/sizeof(*regs); i++)
194 		if (regs[i].base + regs[i].start * 4 <= offset &&
195 		    offset <= regs[i].base + regs[i].end * 4) {
196 			snprintf(buf, bufsize, "%s%02XR", regs[i].name,
197 			    (offset - regs[i].base) / 4);
198 			return (buf);
199 		}
200 	snprintf(buf, bufsize, "OFFSET %02X", offset);
201 	return (buf);
202 }
203 
204 void
mq200_dump_all(struct mq200_softc * sc)205 mq200_dump_all(struct mq200_softc *sc)
206 {
207 	int i, j;
208 
209 	for (i = 0; i < sizeof(regs)/sizeof(*regs); i++)
210 		for (j = regs[i].start; j <= regs[i].end; j++)
211 			printf("%s%02XR: %08x\n",
212 			    regs[i].name, j,
213 			    mq200_read(sc, regs[i].base + (j * 4)));
214 }
215 
216 void
mq200_write(struct mq200_softc * sc,int offset,u_int32_t data)217 mq200_write(struct mq200_softc *sc, int offset, u_int32_t data)
218 {
219 	int i;
220 	char buf[32];
221 
222 	for (i = 0; i < MQ200_I_MAX; i++) {
223 	    if (sc->sc_regctxs[i].offset == offset)
224 		printf("mq200_write: WARNING: raw access %s\n",
225 		    mq200_regname(sc, offset, buf, sizeof(buf)));
226 	}
227 
228 	mq200_writex(sc, offset, data);
229 }
230 
231 #if 0
232 void
233 mq200_dump_gc(struct mq200_softc *sc, int gc)
234 {
235 	u_int32_t reg;
236 	char *depth_names[] = {
237 		"1bpp with CLUT",
238 		"2bpp with CLUT",
239 		"4bpp with CLUT",
240 		"8bpp with CLUT",
241 		"16bpp with CLUT",
242 		"24bpp with CLUT",
243 		"32bpp(RGB) with CLUT",
244 		"32bpp(BGR) with CLUT",
245 		"1bpp w/o CLUT",
246 		"2bpp w/o CLUT",
247 		"4bpp w/o CLUT",
248 		"8bpp w/o CLUT",
249 		"16bpp w/o CLUT",
250 		"24bpp w/o CLUT",
251 		"32bpp(RGB) w/o CLUT",
252 		"32bpp(BGR) w/o CLUT",
253 	};
254 	char *rc_names[] = { "BUS", "PLL1", "PLL2", "PLL3" };
255 	char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" };
256 
257 	/*
258 	 * GC00R	Graphics Controller Control
259 	 */
260 	reg = mq200_read(sc, MQ200_GCCR(gc));
261 	printf("GC00R=0x%08x: ", reg);
262 	printf("%s %s%s%s%s%s\n",
263 	    ENABLE(reg & MQ200_GCC_ENABLE),
264 	    (reg & MQ200_GCC_HCRESET)?"HC_reset ":"",
265 	    (reg & MQ200_GCC_VCRESET)?"VC_reset ":"",
266 	    (reg & MQ200_GCC_HCEN)?"cursor_enable ":"",
267 	    (reg & MQ200_GCC_TESTMODE0)?"test_mode0 ":"",
268 	    (reg & MQ200_GCC_TESTMODE1)?"test_mode1 ":"");
269 	printf("  window: %s %s\n",
270 	    ENABLE(reg & MQ200_GCC_WINEN),
271 	    depth_names[(reg&MQ200_GCC_DEPTH_MASK)>>MQ200_GCC_DEPTH_SHIFT]);
272 	printf("  altwin: %s %s\n",
273 	    ENABLE(reg & MQ200_GCC_ALTEN),
274 	    depth_names[(reg&MQ200_GCC_ALTDEPTH_MASK)>>MQ200_GCC_ALTDEPTH_SHIFT]);
275 	printf("   clock: root_clock/first_div/second_div = %s/%s/%d\n",
276 	    rc_names[(reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT],
277 	    fd_names[(reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT],
278 	    (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT);
279 
280 	if (gc == 0) {
281 		/*
282 		 * GC01R	Graphics Controller CRT Control
283 		 */
284 		reg = mq200_read(sc, MQ200_GC1CRTCR);
285 		printf("GC01R=0x%08x:\n", reg);
286 		printf("  CRT DAC: %s\n",
287 		    ENABLE(reg&MQ200_GC1CRTC_DACEN));
288 
289 		printf("  power down mode: H-sync=");
290 		switch (reg & MQ200_GC1CRTC_HSYNC_PMMASK) {
291 		case MQ200_GC1CRTC_HSYNC_PMNORMAL:
292 			if (reg & MQ200_GC1CRTC_HSYNC_PMCLK)
293 				printf("PMCLK");
294 			else
295 				printf("LOW");
296 			break;
297 		case MQ200_GC1CRTC_HSYNC_PMLOW:
298 			printf("LOW");
299 			break;
300 		case MQ200_GC1CRTC_HSYNC_PMHIGH:
301 			printf("HIGH");
302 			break;
303 		default:
304 			printf("???");
305 			break;
306 		}
307 
308 		printf("  V-sync=");
309 		switch (reg & MQ200_GC1CRTC_VSYNC_PMMASK) {
310 		case MQ200_GC1CRTC_VSYNC_PMNORMAL:
311 			if (reg & MQ200_GC1CRTC_VSYNC_PMCLK)
312 				printf("PMCLK");
313 			else
314 				printf("LOW");
315 			break;
316 		case MQ200_GC1CRTC_VSYNC_PMLOW:
317 			printf("LOW");
318 			break;
319 		case MQ200_GC1CRTC_VSYNC_PMHIGH:
320 			printf("HIGH");
321 			break;
322 		default:
323 			printf("???");
324 			break;
325 		}
326 		printf("\n");
327 
328 		printf("  sync active: H=%s  V=%s\n",
329 		    (reg & MQ200_GC1CRTC_HSYNC_ACTVLOW)?"low":"high",
330 		    (reg & MQ200_GC1CRTC_VSYNC_ACTVLOW)?"low":"high");
331 		printf("  other: ");
332 		if (reg & MQ200_GC1CRTC_SYNC_PEDESTAL_EN)
333 			printf("Sync_pedestal ");
334 		if (reg & MQ200_GC1CRTC_BLANK_PEDESTAL_EN)
335 			printf("Blank_pedestal ");
336 		if (reg & MQ200_GC1CRTC_COMPOSITE_SYNC_EN)
337 			printf("Conposite_sync ");
338 		if (reg & MQ200_GC1CRTC_VREF_EXTR)
339 			printf("External_VREF ");
340 		if (reg & MQ200_GC1CRTC_MONITOR_SENCE_EN) {
341 			if (reg & MQ200_GC1CRTC_CONSTANT_OUTPUT_EN)
342 				printf("Monitor_sence=%s%s%s/- ",
343 				    (reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B",
344 				    (reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R",
345 				    (reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G");
346 			else
347 				printf("Monitor_sence=%s%s%s/0x%02x ",
348 				    (reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B",
349 				    (reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R",
350 				    (reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G",
351 				    (reg & MQ200_GC1CRTC_OUTPUT_LEVEL_MASK)>>MQ200_GC1CRTC_OUTPUT_LEVEL_SHIFT);
352 		}
353 		if (reg & MQ200_GC1CRTC_MONO)
354 			printf("Mono_monitor ");
355 		printf("\n");
356 	}
357 
358 	/*
359 	 * GC02R	Horizontal Display Control
360 	 */
361 	reg = mq200_read(sc, MQ200_GCHDCR(gc));
362 	if (gc == 0) {
363 		printf("GC02R=0x%08x: Horizontal display total=%03d end=%03d\n", reg,
364 		    (reg&MQ200_GC1HDC_TOTAL_MASK)>>MQ200_GC1HDC_TOTAL_SHIFT,
365 		    (reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT);
366 	} else {
367 		printf("GC02R=0x%08x: Horizontal display end=%03d\n", reg,
368 		    (reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT);
369 	}
370 
371 	/*
372 	 * GC03R	Vertical Display Control
373 	 */
374 	reg = mq200_read(sc, MQ200_GCVDCR(gc));
375 	if (gc == 0) {
376 		printf("GC03R=0x%08x:   Vertical display total=%03d end=%03d\n", reg,
377 		    (reg&MQ200_GC1VDC_TOTAL_MASK)>>MQ200_GC1VDC_TOTAL_SHIFT,
378 		    (reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT);
379 	} else {
380 		printf("GC03R=0x%08x:   Vertical display end=%03d\n", reg,
381 		    (reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT);
382 	}
383 
384 	/*
385 	 * GC04R	Horizontal Sync Control
386 	 */
387 	reg = mq200_read(sc, MQ200_GCHSCR(gc));
388 	printf("GC04R=0x%08x: Horizontal    sync start=%03d end=%03d\n", reg,
389 	    (reg&MQ200_GCHSC_START_MASK)>>MQ200_GCHSC_START_SHIFT,
390 	    (reg&MQ200_GCHSC_END_MASK)>>MQ200_GCHSC_END_SHIFT);
391 
392 	/*
393 	 * GC05R	Vertical Sync Control
394 	 */
395 	reg = mq200_read(sc, MQ200_GCVSCR(gc));
396 	printf("GC05R=0x%08x:   Vertical    sync start=%03d end=%03d\n", reg,
397 	    (reg&MQ200_GCVSC_START_MASK)>>MQ200_GCVSC_START_SHIFT,
398 	    (reg&MQ200_GCVSC_END_MASK)>>MQ200_GCVSC_END_SHIFT);
399 
400 	if (gc == 0) {
401 		/*
402 		 * GC07R	Vertical Display Count
403 		 */
404 		reg = mq200_read(sc, MQ200_GC1VDCNTR);
405 		printf("GC07R=0x%08x: Vertical Display Count=%d\n", reg,
406 		    (reg&MQ200_GC1VDCNT_MASK));
407 	}
408 
409 	/*
410 	 * GC08R	Window Horizontal Control
411 	 */
412 	reg = mq200_read(sc, MQ200_GCWHCR(gc));
413 	printf("GC08R=0x%08x: Window Horizontal start=%03d width=%03d",
414 	    reg,
415 	    (reg&MQ200_GCWHC_START_MASK)>> MQ200_GCWHC_START_SHIFT,
416 	    (reg&MQ200_GCWHC_WIDTH_MASK)>> MQ200_GCWHC_WIDTH_SHIFT);
417 	if (gc == 0) {
418 		printf(" add=%03x",
419 		    (reg&MQ200_GC1WHC_ALD_MASK)>> MQ200_GC1WHC_ALD_SHIFT);
420 	}
421 	printf("\n");
422 
423 	/*
424 	 * GC09R	Window Vertical Control
425 	 */
426 	reg = mq200_read(sc, MQ200_GCWVCR(gc));
427 	printf("GC09R=0x%08x:   Window Vertical start=%03d height=%03d\n",
428 	    reg,
429 	    (reg&MQ200_GCWVC_START_MASK)>> MQ200_GCWVC_START_SHIFT,
430 	    (reg&MQ200_GCWVC_HEIGHT_MASK)>> MQ200_GCWVC_HEIGHT_SHIFT);
431 
432 	/*
433 	 * GC0AR	Alternate Window Horizontal Control
434 	 */
435 	reg = mq200_read(sc, MQ200_GCAWHCR(gc));
436 	printf("GC0AR=0x%08x: Altwin Horizontal start=%03d width=%03d",
437 	    reg,
438 	    (reg&MQ200_GCAWHC_START_MASK)>> MQ200_GCAWHC_START_SHIFT,
439 	    (reg&MQ200_GCAWHC_WIDTH_MASK)>> MQ200_GCAWHC_WIDTH_SHIFT);
440 	if (gc == 0) {
441 		printf(" add=%03d",
442 		    (reg&MQ200_GC1AWHC_ALD_MASK)>> MQ200_GC1AWHC_ALD_SHIFT);
443 	}
444 	printf("\n");
445 
446 	/*
447 	 * GC0BR	Alternate Window Vertical Control
448 	 */
449 	reg = mq200_read(sc, MQ200_GCAWVCR(gc));
450 	printf("GC0BR=0x%08x:   Altwin Vertical start=%03d height=%03d\n",
451 	    reg,
452 	    (reg&MQ200_GCAWVC_START_MASK)>> MQ200_GCAWVC_START_SHIFT,
453 	    (reg&MQ200_GCAWVC_HEIGHT_MASK)>> MQ200_GCAWVC_HEIGHT_SHIFT);
454 
455 	/*
456 	 * GC0CR	Window Start Address
457 	 */
458 	reg = mq200_read(sc, MQ200_GCWSAR(gc));
459 	printf("GC0CR=0x%08x: Window start address=0x%08x\n",
460 	    reg, (reg&MQ200_GCWSA_MASK));
461 
462 	/*
463 	 * GC0DR	Alternate Window Start Address
464 	 */
465 	reg = mq200_read(sc, MQ200_GCAWSAR(gc));
466 	printf("GC0DR=0x%08x: Altwin start address=0x%08x palette_index=%02d\n",
467 	    reg, (reg&MQ200_GCAWSA_MASK),
468 	    (reg&MQ200_GCAWPI_MASK)>>MQ200_GCAWPI_SHIFT);
469 
470 	/*
471 	 * GC0ER	Windows Stride
472 	 */
473 	reg = mq200_read(sc, MQ200_GCWSTR(gc));
474 	printf("GC0ER=0x%08x: Stride window=%04d  altwin=%04d\n",
475 	    reg,
476 	    (reg&MQ200_GCWST_MASK)>>MQ200_GCWST_SHIFT,
477 	    (reg&MQ200_GCAWST_MASK)>>MQ200_GCAWST_SHIFT);
478 
479 	/*
480 	 * GC10R	Hardware Cursor Position
481 	 */
482 	reg = mq200_read(sc, MQ200_GCHCPR(gc));
483 	printf("GC10R=0x%08x: Hardware Cursor Position %d,%d\n",
484 	    reg,
485 	    (reg&MQ200_GCHCP_HSTART_MASK)>>MQ200_GCHCP_HSTART_SHIFT,
486 	    (reg&MQ200_GCHCP_VSTART_MASK)>>MQ200_GCHCP_VSTART_SHIFT);
487 
488 	/*
489 	 * GC11R	Hardware Cursor Start Address and Offset
490 	 */
491 	reg = mq200_read(sc, MQ200_GCHCAOR(gc));
492 	printf("GC11R=0x%08x: Hardware Cursor Start Address and Offset\n",
493 	    reg);
494 
495 	/*
496 	 * GC12R	Hardware Cursor Foreground Color
497 	 */
498 	reg = mq200_read(sc, MQ200_GCHCFCR(gc));
499 	printf("GC12R=0x%08x: Hardware Cursor Foreground Color\n", reg);
500 
501 	/*
502 	 * GC13R	Hardware Cursor Background Color
503 	 */
504 	reg = mq200_read(sc, MQ200_GCHCBCR(gc));
505 	printf("GC13R=0x%08x: Hardware Cursor Background Color\n", reg);
506 
507 }
508 
509 void
510 mq200_dump_fp(struct mq200_softc *sc)
511 {
512 	u_int32_t reg;
513 #define I(type)	((type)>>MQ200_FPC_TYPE_SHIFT)
514 	static char *panel_type_names[64] = {
515 		[I(MQ200_FPC_TFT4MONO)] = 	"TFT 4bit mono",
516 		[I(MQ200_FPC_TFT12)] = 		"TFT 12bit color",
517 		[I(MQ200_FPC_SSTN4)] = 		"S-STN 4bit color",
518 		[I(MQ200_FPC_DSTN8)] = 		"D-STN 8bit color",
519 		[I(MQ200_FPC_TFT6MONO)] = 	"TFT 6bit mono",
520 		[I(MQ200_FPC_TFT18)] = 		"TFT 18bit color",
521 		[I(MQ200_FPC_SSTN8)] = 		"S-STN 8bit color",
522 		[I(MQ200_FPC_DSTN16)] = 	"D-STN 16bit color",
523 		[I(MQ200_FPC_TFT8MONO)] = 	"TFT 8bit mono",
524 		[I(MQ200_FPC_TFT24)] =	 	"TFT 24bit color",
525 		[I(MQ200_FPC_SSTN12)] = 	"S-STN 12bit color",
526 		[I(MQ200_FPC_DSTN24)] = 	"D-STN 24bit color",
527 		[I(MQ200_FPC_SSTN16)] = 	"S-STN 16bit color",
528 		[I(MQ200_FPC_SSTN24)] = 	"S-STN 24bit color",
529 	};
530 
531 	reg = mq200_read(sc, MQ200_FPCR);
532 	printf("FP00R=0x%08x: Flat Panel Control\n", reg);
533 	printf("  %s, driven by %s, %s\n",
534 	    ENABLE(reg & MQ200_FPC_ENABLE),
535 	    (reg & MQ200_FPC_GC2) ? "GC2" : "GC1",
536 	    panel_type_names[(reg & MQ200_FPC_TYPE_MASK) >> MQ200_FPC_TYPE_SHIFT]);
537 	reg = mq200_read(sc, MQ200_FPPCR);
538 	printf("FP01R=0x%08x: Flat Panel Output Pin Control\n", reg);
539 }
540 
541 void
542 mq200_dump_dc(struct mq200_softc *sc)
543 {
544 	u_int32_t reg;
545 
546 	reg = 0;
547 }
548 #endif /* 0 */
549 
550 #endif /* MQ200_DEBUG */
551