1 /* -*-C++-*- $NetBSD: arm_mmu.cpp,v 1.6 2008/04/28 20:23:20 martin Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <arm/arm_mmu.h>
33 #include <console.h>
34
MemoryManager_ArmMMU(Console * & cons,size_t pagesize)35 MemoryManager_ArmMMU::MemoryManager_ArmMMU(Console *&cons,
36 size_t pagesize)
37 : MemoryManager(cons, pagesize)
38 {
39 DPRINTF((TEXT("Use ARM software MMU.\n")));
40 }
41
~MemoryManager_ArmMMU(void)42 MemoryManager_ArmMMU::~MemoryManager_ArmMMU(void)
43 {
44 SetKMode(_kmode);
45 }
46
47 BOOL
init(void)48 MemoryManager_ArmMMU::init(void)
49 {
50 uint32_t reg;
51
52 _kmode = SetKMode(1);
53 // Check system mode
54 if ((GetCPSR() & 0x1f) != 0x1f) {
55 DPRINTF((TEXT("not System mode\n")));
56 return FALSE;
57 }
58 // Domain access control.(full access)
59 SetCop15Reg3(~0);
60
61 // Get Translation table base.
62 reg = GetCop15Reg2();
63 _table_base = reg & ARM_MMU_TABLEBASE_MASK;
64 DPRINTF((TEXT("page directory address=0x%08x->0x%08x(0x%08x)\n"),
65 _table_base, readPhysical4(_table_base), reg));
66
67 return TRUE;
68 }
69
70 paddr_t
searchPage(vaddr_t vaddr)71 MemoryManager_ArmMMU::searchPage(vaddr_t vaddr)
72 {
73 paddr_t daddr, paddr = ~0;
74 uint32_t desc1, desc2;
75
76 // set marker.
77 memset(LPVOID(vaddr), 0xa5, _page_size);
78
79 // PID virtual address mapping.
80 DPRINTF((TEXT("Virtual Address 0x%08x"), vaddr));
81 vaddr |= GetCop15Reg13();
82 DPRINTF((TEXT("(+PID)-> 0x%08x\n"), vaddr));
83
84 daddr = _table_base | ARM_MMU_TABLEINDEX(vaddr);
85 desc1 = readPhysical4(daddr);
86 DPRINTF((TEXT("1st level descriptor 0x%08x(addr 0x%08x)\n"),
87 desc1, daddr));
88
89 switch(ARM_MMU_LEVEL1DESC_TRANSLATE_TYPE(desc1)) {
90 default:
91 DPRINTF((TEXT("1st level descriptor fault.\n")));
92 break;
93 case ARM_MMU_LEVEL1DESC_TRANSLATE_SECTION:
94 paddr = ARM_MMU_SECTION_BASE(desc1) |
95 ARM_MMU_VADDR_SECTION_INDEX(vaddr);
96 DPRINTF((TEXT("section Physical Address 0x%08x\n"), paddr));
97 break;
98 case ARM_MMU_LEVEL1DESC_TRANSLATE_PAGE:
99 DPRINTF((TEXT("-> Level2 page descriptor.\n")));
100 daddr = ARM_MMU_PTE_BASE(desc1) |
101 ARM_MMU_VADDR_PTE_INDEX(vaddr);
102 desc2 = readPhysical4(daddr);
103 DPRINTF((TEXT("2nd level descriptor 0x%08x(addr 0x%08x)\n"),
104 desc2, daddr));
105 switch(desc2 & 0x3) {
106 default:
107 DPRINTF((TEXT("2nd level descriptor fault.\n")));
108 break;
109 case 2: // 4Kpage
110 paddr =(desc2 & 0xfffff000) |(vaddr & 0x00000fff);
111 break;
112 case 1: // 64Kpage
113 paddr =(desc2 & 0xffff0000) |(vaddr & 0x0000ffff);
114 break;
115 }
116 break;
117 }
118
119 return paddr;
120 }
121