1 /* $NetBSD: autoconf.c,v 1.6 2016/10/05 15:54:58 ryo Exp $ */
2 /*-
3 * Copyright (c) 2011 CradlePoint Technology, Inc.
4 * All rights reserved.
5 *
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.6 2016/10/05 15:54:58 ryo Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/conf.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37
38 #include <mips/ralink/ralink_reg.h>
39 #include <mips/ralink/ralink_var.h>
40
41 /*
42 * Configure all devices on system
43 */
44 void
cpu_configure(void)45 cpu_configure(void)
46 {
47 intr_init();
48
49 /* Kick off autoconfiguration. */
50 if (config_rootfound("mainbus", NULL) == NULL)
51 panic("no mainbus found");
52
53 /*
54 * Hardware interrupts will be enabled in
55 * sys/arch/mips/mips/mips3_clockintr.c:mips3_initclocks()
56 * to avoid hardclock(9) by CPU INT5 before softclockintr is
57 * initialized in initclocks().
58 */
59 }
60
61 void
cpu_rootconf(void)62 cpu_rootconf(void)
63 {
64 rootconf();
65 }
66
67 static const struct cfg_info {
68 const char *map_name;
69 uint32_t map_rst;
70 uint32_t map_clkcfg1;
71 } map_info[] = {
72 #if defined(MT7628)
73 { "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 },
74 { "ohci", RST_UHST0_7620|RST_UHST,
75 SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 },
76 { "ehci", RST_UHST0_7620|RST_UHST,
77 SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 },
78 { "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN },
79 { "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN },
80 #endif
81 #if defined(MT7620)
82 { "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 },
83 { "ohci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 },
84 { "ehci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 },
85 { "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN },
86 { "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN },
87 #endif
88 #if defined(RT3883)
89 { "rpci", RST_PCI_3883 | RST_PCIPCIE_3883,
90 SYSCTL_CLKCFG1_PCI_CLK_EN|SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 },
91 { "ohci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 },
92 { "ehci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 },
93 #endif
94 };
95
96 static void
ra_device_fixup(bus_space_tag_t bst,const struct cfg_info * map)97 ra_device_fixup(bus_space_tag_t bst, const struct cfg_info *map)
98 {
99 const uint32_t clkcfg1 = bus_space_read_4(bst, ra_sysctl_bsh,
100 RA_SYSCTL_CLKCFG1);
101 if ((clkcfg1 & map->map_clkcfg1) != map->map_clkcfg1) {
102 bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_CLKCFG1,
103 clkcfg1 | map->map_clkcfg1);
104 delay(10000);
105 }
106
107 const uint32_t rst = bus_space_read_4(bst, ra_sysctl_bsh,
108 RA_SYSCTL_RST);
109 if ((rst & map->map_rst) != 0) {
110 bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_RST,
111 rst & ~map->map_rst);
112 delay(10000);
113 }
114 }
115
116 void
device_register(device_t self,void * aux)117 device_register(device_t self, void *aux)
118 {
119 device_t parent = device_parent(self);
120
121 if (parent != NULL && device_is_a(parent, "mainbus")) {
122 // If we are attaching a mainbus device, see if we know how
123 // to bring it out of reset.
124 struct mainbus_attach_args * const ma = aux;
125 for (const struct cfg_info *map = map_info;
126 map < map_info + __arraycount(map_info);
127 map++) {
128 if (device_is_a(self, map->map_name)) {
129 ra_device_fixup(ma->ma_memt, map);
130 delay(1000);
131 break;
132 }
133 }
134
135 #if defined(RT3883) || defined(MT7620)
136 if (device_is_a(self, "ohci") || device_is_a(self, "ehci")) {
137 const uint32_t cfg1 = bus_space_read_4(ma->ma_memt,
138 ra_sysctl_bsh, RA_SYSCTL_CFG1);
139 if ((cfg1 & SYSCTL_CFG1_USB0_HOST_MODE) == 0) {
140 bus_space_write_4(ma->ma_memt, ra_sysctl_bsh,
141 RA_SYSCTL_CFG1,
142 cfg1 | SYSCTL_CFG1_USB0_HOST_MODE);
143 delay(10);
144 }
145 }
146 #endif
147 }
148 }
149