1 /* $NetBSD: sacc_obio.c,v 1.17 2023/07/13 21:29:49 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by IWAMOTO Toshihiro.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * for SA-1111 companion chip on Intel DBPXA250 evaluation board.
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: sacc_obio.c,v 1.17 2023/07/13 21:29:49 riastradh Exp $");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/mbuf.h>
42 #include <sys/socket.h>
43 #include <sys/ioctl.h>
44 #include <sys/errno.h>
45 #include <sys/syslog.h>
46 #include <sys/select.h>
47 #include <sys/device.h>
48 #include <sys/bitops.h>
49
50 #include <net/if.h>
51 #include <net/if_dl.h>
52 #include <net/if_ether.h>
53 #include <net/if_media.h>
54
55 #include <machine/intr.h>
56 #include <sys/bus.h>
57
58 #include <arm/sa11x0/sa1111_reg.h>
59 #include <arm/sa11x0/sa1111_var.h>
60 #include <arm/xscale/pxa2x0cpu.h>
61 #include <arm/xscale/pxa2x0reg.h>
62 #include <arm/xscale/pxa2x0var.h>
63 #include <arm/xscale/pxa2x0_gpio.h>
64
65 #include <evbarm/lubbock/lubbock_reg.h>
66 #include <evbarm/lubbock/lubbock_var.h>
67
68
69 static int sacc_obio_probe(device_t parent, cfdata_t match, void *aux);
70 static void sacc_obio_attach(device_t, device_t, void *);
71 static int sacc_obio_intr(void *arg);
72
73 CFATTACH_DECL_NEW(sacc_obio, sizeof(struct sacc_softc), sacc_obio_probe,
74 sacc_obio_attach, NULL, NULL);
75
76 #if 0
77 #define DPRINTF(arg) aprint_normal arg
78 #else
79 #define DPRINTF(arg)
80 #endif
81
82 uint16_t cs2_memctl_init = 0x7ff0;
83
84 static int
sacc_obio_probe(device_t parent,cfdata_t match,void * aux)85 sacc_obio_probe(device_t parent, cfdata_t match, void *aux)
86 {
87 struct obio_attach_args *oa = aux;
88 struct sa11x0_attach_args sa;
89
90 printf("%s: addr=%lx\n", __func__, oa->oba_addr);
91
92 sa.sa_sc = oa->oba_sc;
93 sa.sa_iot = oa->oba_iot;
94 sa.sa_addr = oa->oba_addr;
95 sa.sa_size = 0x2000;
96
97 return sacc_probe(parent, match, &sa);
98 }
99
100 static void
sacc_obio_attach(device_t parent,device_t self,void * aux)101 sacc_obio_attach(device_t parent, device_t self, void *aux)
102 {
103 int i;
104 uint32_t skid, tmp;
105 struct sacc_softc *sc = device_private(self);
106 struct obio_softc *psc = device_private(parent);
107 struct obio_attach_args *sa = aux;
108 bus_space_tag_t iot = sa->oba_iot;
109 bus_space_handle_t memctl_ioh;
110
111 aprint_normal("\n");
112
113 /* Set alternative function for GPIO pings 48..57 on PXA2X0 */
114 for (i=48; i <= 55; ++i)
115 pxa2x0_gpio_set_function(i, GPIO_ALT_FN_2_OUT);
116 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN);
117 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN);
118
119 /* XXX */
120 if (bus_space_map(iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0,
121 &memctl_ioh))
122 goto fail;
123
124 tmp = bus_space_read_4(iot, memctl_ioh, MEMCTL_MSC2 );
125 bus_space_write_4(iot, memctl_ioh, MEMCTL_MSC2,
126 (tmp & 0xffff0000) | cs2_memctl_init );
127
128 bus_space_unmap(iot, memctl_ioh, PXA2X0_MEMCTL_SIZE);
129
130 sc->sc_dev = self;
131 sc->sc_piot = sc->sc_iot = iot;
132 sc->sc_gpioh = 0; /* not used */
133
134 if (bus_space_map(iot, sa->oba_addr, 0x2000/*size*/, 0, &sc->sc_ioh))
135 goto fail;
136
137 skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID);
138
139 aprint_normal_dev(self, "SA1111 rev %d.%d\n",
140 (skid & 0xf0) >> 4, skid & 0xf);
141
142 tmp = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR);
143 tmp = (tmp & ~SKCR_VCOOFF) | SKCR_PLLBYPASS;
144 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp );
145
146 delay(100); /* XXX */
147
148 tmp |= SKCR_RCLKEN;
149 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp );
150
151 #if 1
152 if( tmp != bus_space_read_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR ) )
153 printf( "!!! FAIL SKCR\n" );
154 #endif
155
156 /* PCMCIA socket0 power control */
157 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DVR, 0 );
158 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DDR, 0 );
159
160 for(i = 0; i < SACCIC_LEN; i++)
161 sc->sc_intrhand[i] = NULL;
162
163 /* initialize SA1111 interrupt controller */
164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0);
165 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0);
166 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0);
167 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
168 SACCIC_INTSTATCLR0, 0xffffffff);
169 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
170 SACCIC_INTSTATCLR1, 0xffffffff);
171
172 /* connect to On-board peripheral interrupt */
173 obio_intr_establish(psc, sa->oba_intr,
174 IPL_HIGH, sacc_obio_intr, sc );
175 /*
176 * Attach each devices
177 */
178 config_search(self, NULL,
179 CFARGS(.search = sa1111_search));
180
181 return;
182
183 fail:
184 aprint_normal_dev(self, "unable to map registers\n");
185 }
186
187 static int
sacc_obio_intr(void * arg)188 sacc_obio_intr(void *arg)
189 {
190 int i;
191 struct sacc_intrvec intstat;
192 struct sacc_softc *sc = arg;
193 struct sacc_intrhand *ih;
194
195 intstat.lo =
196 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0);
197 intstat.hi =
198 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1);
199 DPRINTF(("sacc_obio_intr_dispatch: %x %x\n", intstat.lo, intstat.hi));
200
201 while ((i = fls32(intstat.lo) - 1) >= 0) {
202
203 /*
204 * Clear intr status before calling intr handlers.
205 * This cause stray interrupts, but clearing
206 * after calling intr handlers cause intr lossage.
207 */
208 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
209 SACCIC_INTSTATCLR0, 1U<<i );
210
211 for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next)
212 softint_schedule(ih->ih_soft);
213
214 intstat.lo &= ~(1U<<i);
215 }
216
217 while ((i = fls32(intstat.hi) - 1) >= 0) {
218 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
219 SACCIC_INTSTATCLR1, 1U<<i);
220
221 for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next)
222 softint_schedule(ih->ih_soft);
223
224 intstat.hi &= ~(1U<<i);
225 }
226
227 return 1;
228 }
229