1 /* $NetBSD: zs.c,v 1.7 2021/09/11 20:28:03 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 1996 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Zilog Z8530 Dual UART driver (machine-dependent part)
34 *
35 * Runs two serial lines per chip using slave drivers.
36 * Plain tty/async lines use the zs_async slave.
37 */
38
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.7 2021/09/11 20:28:03 andvar Exp $");
41
42 #include "opt_ddb.h"
43
44 #include <sys/param.h>
45 #include <sys/conf.h>
46 #include <sys/cpu.h>
47 #include <sys/device.h>
48 #include <sys/intr.h>
49 #include <sys/tty.h>
50 #include <sys/systm.h>
51
52 #include <dev/cons.h>
53 #include <dev/ic/z8530reg.h>
54
55 #include <mips/cpuregs.h>
56
57 #include <machine/autoconf.h>
58 #include <machine/z8530var.h>
59
60 #include <cobalt/cobalt/console.h>
61
62 #include "ioconf.h"
63
64 /*
65 * Some warts needed by z8530tty.c -
66 * The default parity REALLY needs to be the same as the PROM uses,
67 * or you can not see messages done with printf during boot-up...
68 */
69 int zs_def_cflag = (CREAD | CS8 | HUPCL);
70
71 #define ZS_DEFSPEED 115200
72 #define PCLK (115200 * 96) /* 11.0592MHz */
73
74 #define ZS_DELAY() delay(2)
75
76 /* The layout of this is hardware-dependent (padding, order). */
77 /* A/~B (Channel A/Channel B) pin is connected to DAdr0 */
78 #define ZS_CHAN_A 0x01
79 #define ZS_CHAN_B 0x00
80
81 /* D/~C (Data/Control) pin is connected to DAdr1 */
82 #define ZS_CSR 0x00 /* ctrl, status, and indirect access */
83 #define ZS_DATA 0x02 /* data */
84
85
86 /* Definition of the driver for autoconfig. */
87 static int zs_match(device_t, cfdata_t, void *);
88 static void zs_attach(device_t, device_t, void *);
89 static int zs_print(void *, const char *name);
90
91 CFATTACH_DECL_NEW(zsc, sizeof(struct zsc_softc),
92 zs_match, zs_attach, NULL, NULL);
93
94 static int zshard(void *);
95 #if 0
96 static int zs_get_speed(struct zs_chanstate *);
97 #endif
98 static int zs_getc(void *);
99 static void zs_putc(void *, int);
100
101 /* console status from cninit */
102 static struct zs_chanstate zs_conschan_store;
103 static struct zs_chanstate *zs_conschan;
104 static uint8_t *zs_cons;
105
106 /* default speed for all channels */
107 static int zs_defspeed = ZS_DEFSPEED;
108
109 static uint8_t zs_init_reg[16] = {
110 0, /* 0: CMD (reset, etc.) */
111 0, /* 1: No interrupts yet. */
112 0, /* 2: no IVECT */
113 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, /* 3: RX params and ctrl */
114 ZSWR4_CLK_X16 | ZSWR4_ONESB, /* 4: TX/RX misc params */
115 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, /* 5: TX params and ctrl */
116 0, /* 6: TXSYNC/SYNCLO */
117 0, /* 7: RXSYNC/SYNCHI */
118 0, /* 8: alias for data port */
119 ZSWR9_MASTER_IE, /* 9: Master interrupt ctrl */
120 0, /*10: Misc TX/RX ctrl */
121 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, /*11: Clock Mode ctrl */
122 BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /*12: BAUDLO */
123 0, /*13: BAUDHI */
124 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, /*14: Misc ctrl */
125 ZSWR15_BREAK_IE, /*15: Ext/Status intr ctrl */
126 };
127
128 /* register address offset for each channel */
129 static const int chanoff[] = { ZS_CHAN_A, ZS_CHAN_B };
130
131
132 static int
zs_match(device_t parent,cfdata_t cf,void * aux)133 zs_match(device_t parent, cfdata_t cf, void *aux)
134 {
135 static int matched;
136
137 /* only one zs */
138 if (matched)
139 return 0;
140
141 /* only Qube 2700 could have Z85C30 serial */
142 if (cobalt_id != COBALT_ID_QUBE2700)
143 return 0;
144
145 if (!console_present)
146 return 0;
147
148 matched = 1;
149 return 1;
150 }
151
152 /*
153 * Attach a found zs.
154 */
155 static void
zs_attach(device_t parent,device_t self,void * aux)156 zs_attach(device_t parent, device_t self, void *aux)
157 {
158 struct zsc_softc *zsc = device_private(self);
159 struct mainbus_attach_args *maa = aux;
160 struct zsc_attach_args zsc_args;
161 uint8_t *zs_base;
162 struct zs_chanstate *cs;
163 int s, channel;
164
165 zsc->zsc_dev = self;
166
167 /* XXX: MI z8530 doesn't use bus_space(9) yet */
168 zs_base = (void *)MIPS_PHYS_TO_KSEG1(maa->ma_addr);
169
170 aprint_normal(": optional Z85C30 serial port\n");
171
172 /*
173 * Initialize software state for each channel.
174 */
175 for (channel = 0; channel < 2; channel++) {
176 zsc_args.channel = channel;
177 cs = &zsc->zsc_cs_store[channel];
178
179 zsc->zsc_cs[channel] = cs;
180
181 zs_init_reg[2] = 0;
182
183 if ((zs_base + chanoff[channel]) == zs_cons) {
184 memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
185 zs_conschan = cs;
186 zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
187 } else {
188 cs->cs_reg_csr = zs_base + chanoff[channel] + ZS_CSR;
189 cs->cs_reg_data = zs_base + chanoff[channel] + ZS_DATA;
190 memcpy(cs->cs_creg, zs_init_reg, 16);
191 memcpy(cs->cs_preg, zs_init_reg, 16);
192 cs->cs_defspeed = zs_defspeed;
193 zsc_args.hwflags = 0;
194 }
195
196 zs_lock_init(cs);
197 cs->cs_defcflag = zs_def_cflag;
198
199 cs->cs_channel = channel;
200 cs->cs_private = NULL;
201 cs->cs_ops = &zsops_null;
202 cs->cs_brg_clk = PCLK / 16;
203
204 /* Make these correspond to cs_defcflag (-crtscts) */
205 cs->cs_rr0_dcd = ZSRR0_DCD;
206 cs->cs_rr0_cts = 0;
207 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
208 cs->cs_wr5_rts = 0;
209
210 /*
211 * Clear the master interrupt enable.
212 * The INTENA is common to both channels,
213 * so just do it on the A channel.
214 */
215 if (channel == 0) {
216 s = splhigh();
217 zs_write_reg(cs, 9, 0);
218 splx(s);
219 }
220
221 /*
222 * Look for a child driver for this channel.
223 * The child attach will setup the hardware.
224 */
225 if (!config_found(self, (void *)&zsc_args, zs_print,
226 CFARGS_NONE)) {
227 /* No sub-driver. Just reset it. */
228 uint8_t reset = (channel == 0) ?
229 ZSWR9_A_RESET : ZSWR9_B_RESET;
230 s = splhigh();
231 zs_write_reg(cs, 9, reset);
232 splx(s);
233 }
234 }
235
236 /*
237 * Now safe to install interrupt handlers.
238 */
239 icu_intr_establish(maa->ma_irq, IST_EDGE, IPL_SERIAL, zshard, zsc);
240 zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
241 (void (*)(void *))zsc_intr_soft, zsc);
242
243 /*
244 * Set the master interrupt enable and interrupt vector.
245 * (common to both channels, do it on A)
246 */
247 cs = zsc->zsc_cs[0];
248 s = splhigh();
249 /* interrupt vector */
250 zs_write_reg(cs, 2, 0);
251 /* master interrupt control (enable) */
252 zs_write_reg(cs, 9, zs_init_reg[9]);
253 splx(s);
254 }
255
256 static int
zs_print(void * aux,const char * name)257 zs_print(void *aux, const char *name)
258 {
259 struct zsc_attach_args *args = aux;
260
261 if (name != NULL)
262 aprint_normal("%s: ", name);
263
264 if (args->channel != -1)
265 aprint_normal(" channel %d", args->channel);
266
267 return UNCONF;
268 }
269
270 static int
zshard(void * arg)271 zshard(void *arg)
272 {
273 struct zsc_softc *zsc = arg;
274 int rval;
275
276 rval = zsc_intr_hard(zsc);
277
278 #if 1
279 /* XXX: there is some race condition? */
280 if (rval)
281 while (zsc_intr_hard(zsc))
282 ;
283 #endif
284
285 /* We are at splzs here, so no need to lock. */
286 if (zsc->zsc_cs[0]->cs_softreq || zsc->zsc_cs[1]->cs_softreq)
287 softint_schedule(zsc->zsc_softintr_cookie);
288
289 return rval;
290 }
291
292 /*
293 * Compute the current baud rate given a ZS channel.
294 */
295 #if 0
296 static int
297 zs_get_speed(struct zs_chanstate *cs)
298 {
299 int tconst;
300
301 tconst = zs_read_reg(cs, 12);
302 tconst |= zs_read_reg(cs, 13) << 8;
303 return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
304 }
305 #endif
306
307 /*
308 * MD functions for setting the baud rate and control modes.
309 */
310 int
zs_set_speed(struct zs_chanstate * cs,int bps)311 zs_set_speed(struct zs_chanstate *cs, int bps)
312 {
313 int tconst, real_bps;
314
315 if (bps == 0)
316 return 0;
317
318 #ifdef DIAGNOSTIC
319 if (cs->cs_brg_clk == 0)
320 panic("zs_set_speed");
321 #endif
322
323 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
324 if (tconst < 0)
325 return EINVAL;
326
327 /* Convert back to make sure we can do it. */
328 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
329
330 /* Allow ~4% tolerance here */
331 if (abs(real_bps - bps) >= bps * 4 / 100)
332 return EINVAL;
333
334 cs->cs_preg[12] = tconst;
335 cs->cs_preg[13] = tconst >> 8;
336
337 /* Caller will stuff the pending registers. */
338 return 0;
339 }
340
341 int
zs_set_modes(struct zs_chanstate * cs,int cflag)342 zs_set_modes(struct zs_chanstate *cs, int cflag)
343 {
344 int s;
345
346 /*
347 * Output hardware flow control on the chip is horrendous:
348 * if carrier detect drops, the receiver is disabled, and if
349 * CTS drops, the transmitter is stopped IN MID CHARACTER!
350 * Therefore, NEVER set the HFC bit, and instead use the
351 * status interrupt to detect CTS changes.
352 */
353 s = splzs();
354 cs->cs_rr0_pps = 0;
355 if ((cflag & (CLOCAL | MDMBUF)) != 0) {
356 cs->cs_rr0_dcd = 0;
357 if ((cflag & MDMBUF) == 0)
358 cs->cs_rr0_pps = ZSRR0_DCD;
359 } else
360 cs->cs_rr0_dcd = ZSRR0_DCD;
361 if ((cflag & CRTSCTS) != 0) {
362 cs->cs_wr5_dtr = ZSWR5_DTR;
363 cs->cs_wr5_rts = ZSWR5_RTS;
364 cs->cs_rr0_cts = ZSRR0_CTS;
365 } else if ((cflag & MDMBUF) != 0) {
366 cs->cs_wr5_dtr = 0;
367 cs->cs_wr5_rts = ZSWR5_DTR;
368 cs->cs_rr0_cts = ZSRR0_DCD;
369 } else {
370 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
371 cs->cs_wr5_rts = 0;
372 cs->cs_rr0_cts = 0;
373 }
374 splx(s);
375
376 /* Caller will stuff the pending registers. */
377 return 0;
378 }
379
380
381 /*
382 * Read or write the chip with suitable delays.
383 */
384
385 uint8_t
zs_read_reg(struct zs_chanstate * cs,uint8_t reg)386 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
387 {
388 uint8_t val;
389
390 *cs->cs_reg_csr = reg;
391 ZS_DELAY();
392 val = *cs->cs_reg_csr;
393 ZS_DELAY();
394 return val;
395 }
396
397 void
zs_write_reg(struct zs_chanstate * cs,uint8_t reg,uint8_t val)398 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
399 {
400
401 *cs->cs_reg_csr = reg;
402 ZS_DELAY();
403 *cs->cs_reg_csr = val;
404 ZS_DELAY();
405 }
406
407 uint8_t
zs_read_csr(struct zs_chanstate * cs)408 zs_read_csr(struct zs_chanstate *cs)
409 {
410 uint8_t val;
411
412 val = *cs->cs_reg_csr;
413 ZS_DELAY();
414 return val;
415 }
416
417 void
zs_write_csr(struct zs_chanstate * cs,uint8_t val)418 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
419 {
420
421 *cs->cs_reg_csr = val;
422 ZS_DELAY();
423 }
424
425 uint8_t
zs_read_data(struct zs_chanstate * cs)426 zs_read_data(struct zs_chanstate *cs)
427 {
428 uint8_t val;
429
430 val = *cs->cs_reg_data;
431 ZS_DELAY();
432 return val;
433 }
434
435 void
zs_write_data(struct zs_chanstate * cs,uint8_t val)436 zs_write_data(struct zs_chanstate *cs, uint8_t val)
437 {
438
439 *cs->cs_reg_data = val;
440 ZS_DELAY();
441 }
442
443 void
zs_abort(struct zs_chanstate * cs)444 zs_abort(struct zs_chanstate *cs)
445 {
446
447 #ifdef DDB
448 Debugger();
449 #endif
450 }
451
452 /*
453 * Polled input char.
454 */
455 int
zs_getc(void * arg)456 zs_getc(void *arg)
457 {
458 struct zs_chanstate *cs = arg;
459 int s, c;
460 uint8_t rr0;
461
462 s = splhigh();
463 /* Wait for a character to arrive. */
464 do {
465 rr0 = *cs->cs_reg_csr;
466 ZS_DELAY();
467 } while ((rr0 & ZSRR0_RX_READY) == 0);
468
469 c = *cs->cs_reg_data;
470 ZS_DELAY();
471 splx(s);
472
473 return c;
474 }
475
476 /*
477 * Polled output char.
478 */
479 void
zs_putc(void * arg,int c)480 zs_putc(void *arg, int c)
481 {
482 struct zs_chanstate *cs = arg;
483 int s;
484 uint8_t rr0;
485
486 s = splhigh();
487 /* Wait for transmitter to become ready. */
488 do {
489 rr0 = *cs->cs_reg_csr;
490 ZS_DELAY();
491 } while ((rr0 & ZSRR0_TX_READY) == 0);
492
493 *cs->cs_reg_data = c;
494 ZS_DELAY();
495 splx(s);
496 }
497
498 void
zscnprobe(struct consdev * cn)499 zscnprobe(struct consdev *cn)
500 {
501
502 cn->cn_pri = (console_present != 0 && cobalt_id == COBALT_ID_QUBE2700)
503 ? CN_NORMAL : CN_DEAD;
504 }
505
506 void
zscninit(struct consdev * cn)507 zscninit(struct consdev *cn)
508 {
509 struct zs_chanstate *cs;
510
511 extern const struct cdevsw zstty_cdevsw;
512
513 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
514
515 zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */
516
517 zs_conschan = cs = &zs_conschan_store;
518
519 /* Setup temporary chanstate. */
520 cs->cs_reg_csr = zs_cons + ZS_CSR;
521 cs->cs_reg_data = zs_cons + ZS_DATA;
522
523 /* Initialize the pending registers. */
524 memcpy(cs->cs_preg, zs_init_reg, 16);
525 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
526
527 cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED);
528 cs->cs_preg[13] = 0;
529 cs->cs_defspeed = ZS_DEFSPEED;
530
531 /* Clear the master interrupt enable. */
532 zs_write_reg(cs, 9, 0);
533
534 /* Reset the whole SCC chip. */
535 zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
536
537 /* Copy "pending" to "current" and H/W */
538 zs_loadchannelregs(cs);
539 }
540
541 int
zscngetc(dev_t dev)542 zscngetc(dev_t dev)
543 {
544
545 return zs_getc((void *)zs_conschan);
546 }
547
548 void
zscnputc(dev_t dev,int c)549 zscnputc(dev_t dev, int c)
550 {
551
552 zs_putc((void *)zs_conschan, c);
553 }
554