1 /* $NetBSD: i80321_pci.c,v 1.19 2022/09/27 06:36:43 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * PCI configuration support for i80321 I/O Processor chip.
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: i80321_pci.c,v 1.19 2022/09/27 06:36:43 skrll Exp $");
44
45 #include "opt_pci.h"
46 #include "opt_i80321.h"
47 #include "pci.h"
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/device.h>
52 #include <sys/bus.h>
53
54 #include <uvm/uvm_extern.h>
55
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pciconf.h>
58 #include <dev/pci/ppbreg.h>
59
60 #include <arm/locore.h>
61
62 #include <arm/xscale/i80321reg.h>
63 #include <arm/xscale/i80321var.h>
64
65 void i80321_pci_attach_hook(device_t, device_t,
66 struct pcibus_attach_args *);
67 int i80321_pci_bus_maxdevs(void *, int);
68 pcitag_t i80321_pci_make_tag(void *, int, int, int);
69 void i80321_pci_decompose_tag(void *, pcitag_t, int *, int *,
70 int *);
71 pcireg_t i80321_pci_conf_read(void *, pcitag_t, int);
72 void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t);
73 void i80321_pci_conf_interrupt(void *, int, int, int, int, int *);
74
75 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
76 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
77
78 void
i80321_pci_init(pci_chipset_tag_t pc,void * cookie)79 i80321_pci_init(pci_chipset_tag_t pc, void *cookie)
80 {
81 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
82 struct i80321_softc *sc = cookie;
83 struct pciconf_resources *pcires;
84 uint32_t busno;
85 #endif
86
87 pc->pc_conf_v = cookie;
88 pc->pc_attach_hook = i80321_pci_attach_hook;
89 pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs;
90 pc->pc_make_tag = i80321_pci_make_tag;
91 pc->pc_decompose_tag = i80321_pci_decompose_tag;
92 pc->pc_conf_read = i80321_pci_conf_read;
93 pc->pc_conf_write = i80321_pci_conf_write;
94 pc->pc_conf_interrupt = i80321_pci_conf_interrupt;
95
96 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
97 /*
98 * Configure the PCI bus.
99 *
100 * XXX We need to revisit this. We only configure the Secondary
101 * bus (and its children). The bus configure code needs changes
102 * to support how the busses are arranged on this chip. We also
103 * need to only configure devices in the private device space on
104 * the Secondary bus.
105 */
106
107 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
108 busno = PCIXSR_BUSNO(busno);
109 if (busno == 0xff)
110 busno = 0;
111
112 pcires = pciconf_resource_init();
113
114 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
115 sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset,
116 VERDE_OUT_XLATE_IO_WIN_SIZE - sc->sc_ioout_xlate_offset);
117
118 #ifdef I80321_USE_DIRECT_WIN
119 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
120 VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP,
121 VERDE_OUT_DIRECT_WIN_SIZE - VERDE_OUT_DIRECT_WIN_SKIP);
122 #else
123 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
124 sc->sc_owin[0].owin_xlate_lo, VERDE_OUT_XLATE_MEM_WIN_SIZE);
125 #endif
126
127 aprint_normal_dev(sc->sc_dev, "configuring PCI bus\n");
128 pci_configure_bus(pc, pcires, busno, arm_dcache_align);
129
130 pciconf_resource_fini(pcires);
131 #endif
132 }
133
134 void
i80321_pci_conf_interrupt(void * v,int a,int b,int c,int d,int * p)135 i80321_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p)
136 {
137 }
138
139 void
i80321_pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)140 i80321_pci_attach_hook(device_t parent, device_t self,
141 struct pcibus_attach_args *pba)
142 {
143
144 /* Nothing to do. */
145 }
146
147 int
i80321_pci_bus_maxdevs(void * v,int busno)148 i80321_pci_bus_maxdevs(void *v, int busno)
149 {
150
151 return (32);
152 }
153
154 pcitag_t
i80321_pci_make_tag(void * v,int b,int d,int f)155 i80321_pci_make_tag(void *v, int b, int d, int f)
156 {
157
158 return ((b << 16) | (d << 11) | (f << 8));
159 }
160
161 void
i80321_pci_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)162 i80321_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
163 {
164
165 if (bp != NULL)
166 *bp = (tag >> 16) & 0xff;
167 if (dp != NULL)
168 *dp = (tag >> 11) & 0x1f;
169 if (fp != NULL)
170 *fp = (tag >> 8) & 0x7;
171 }
172
173 struct pciconf_state {
174 uint32_t ps_addr_val;
175
176 int ps_b, ps_d, ps_f;
177 };
178
179 static int
i80321_pci_conf_setup(struct i80321_softc * sc,pcitag_t tag,int offset,struct pciconf_state * ps)180 i80321_pci_conf_setup(struct i80321_softc *sc, pcitag_t tag, int offset,
181 struct pciconf_state *ps)
182 {
183 uint32_t busno;
184
185 if ((unsigned int)offset >= PCI_CONF_SIZE)
186 return (1);
187
188 i80321_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
189
190 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
191 busno = PCIXSR_BUSNO(busno);
192 if (busno == 0xff)
193 busno = 0;
194
195 /*
196 * If the bus # is the same as our own, then use Type 0 cycles,
197 * else use Type 1.
198 *
199 * XXX We should filter out all non-private devices here!
200 * XXX How does private space interact with PCI-PCI bridges?
201 */
202 if (ps->ps_b == busno) {
203 if (ps->ps_d > (31 - 16))
204 return (1);
205 /*
206 * NOTE: PCI-X requires that that devices updated their
207 * PCIXSR on every config write with the device number
208 * specified in AD[15:11]. If we don't set this field,
209 * each device could end of thinking it is at device 0,
210 * which can cause a number of problems. Doing this
211 * unconditionally should be OK when only PCI devices
212 * are present.
213 */
214 ps->ps_addr_val = (1U << (ps->ps_d + 16)) |
215 (ps->ps_d << 11) | (ps->ps_f << 8) | offset;
216 } else {
217 /* The tag is already in the correct format. */
218 ps->ps_addr_val = tag | offset | 1;
219 }
220
221 return (0);
222 }
223
224 pcireg_t
i80321_pci_conf_read(void * v,pcitag_t tag,int offset)225 i80321_pci_conf_read(void *v, pcitag_t tag, int offset)
226 {
227 struct i80321_softc *sc = v;
228 struct pciconf_state ps;
229 vaddr_t va;
230 uint32_t isr;
231 pcireg_t rv;
232 u_int s;
233
234 if (i80321_pci_conf_setup(sc, tag, offset, &ps))
235 return ((pcireg_t) -1);
236
237 PCI_CONF_LOCK(s);
238
239 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
240 ps.ps_addr_val);
241
242 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh);
243 if (badaddr_read((void *) (va + ATU_OCCDR), sizeof(rv), &rv)) {
244 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
245 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR,
246 isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
247 ATUISR_PTAT|ATUISR_PMPE));
248 #if 0
249 printf("conf_read: %d/%d/%d bad address\n",
250 ps.ps_b, ps.ps_d, ps.ps_f);
251 #endif
252 rv = (pcireg_t) -1;
253 }
254
255 PCI_CONF_UNLOCK(s);
256
257 return (rv);
258 }
259
260 void
i80321_pci_conf_write(void * v,pcitag_t tag,int offset,pcireg_t val)261 i80321_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
262 {
263 struct i80321_softc *sc = v;
264 struct pciconf_state ps;
265 u_int s;
266
267 if (i80321_pci_conf_setup(sc, tag, offset, &ps))
268 return;
269
270 PCI_CONF_LOCK(s);
271
272 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
273 ps.ps_addr_val);
274 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, val);
275
276 PCI_CONF_UNLOCK(s);
277 }
278