1 /* $NetBSD: zynq_platform.c,v 1.11 2023/04/07 08:55:31 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2019 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Nick Hudson
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "opt_console.h"
33 #include "opt_soc.h"
34
35 #include "arml2cc.h"
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.11 2023/04/07 08:55:31 skrll Exp $");
39
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/cpu.h>
43 #include <sys/device.h>
44
45 #include <dev/fdt/fdtvar.h>
46 #include <arm/fdt/arm_fdtvar.h>
47
48 #include <uvm/uvm_extern.h>
49
50 #include <machine/bootconfig.h>
51
52 #include <arm/cortex/a9tmr_var.h>
53 #include <arm/cortex/scu_reg.h>
54 #include <arm/xilinx/zynq_uartreg.h>
55
56 #include <evbarm/fdt/platform.h>
57
58 #include <libfdt.h>
59
60 #include <arm/cortex/pl310_var.h>
61
62 #include <arm/arm32/machdep.h>
63
64 #define ZYNQ_REF_FREQ 24000000
65 #define ZYNQ7000_DDR_PBASE 0x00000000
66 #define ZYNQ7000_DDR_SIZE 0x40000000
67
68 #define ZYNQ_IOREG_VBASE KERNEL_IO_VBASE
69 #define ZYNQ_IOREG_PBASE 0xe0000000
70 #define ZYNQ_IOREG_SIZE 0x00200000
71
72 #define ZYNQ_SLCR_VBASE (ZYNQ_IOREG_VBASE + ZYNQ_IOREG_SIZE)
73 #define ZYNQ_SLCR_PBASE 0xf8000000
74 #define ZYNQ_SLCR_SIZE 0x00100000
75
76 #define ZYNQ_GPV_VBASE (ZYNQ_SLCR_VBASE + ZYNQ_SLCR_SIZE)
77 #define ZYNQ_GPV_PBASE 0xf8900000
78 #define ZYNQ_GPV_SIZE 0x00100000
79
80 #define ZYNQ_ARMCORE_VBASE (ZYNQ_GPV_VBASE + ZYNQ_GPV_SIZE)
81 #define ZYNQ_ARMCORE_PBASE 0xf8f00000
82 #define ZYNQ_ARMCORE_SIZE 0x00100000
83
84 #define ZYNQ_OCM_VBASE (ZYNQ_ARMCORE_VBASE + ZYNQ_ARMCORE_SIZE)
85 #define ZYNQ_OCM_PBASE 0xfff00000
86 #define ZYNQ_OCM_SIZE 0x00100000
87
88 #define ZYNQ_ARMCORE_SCU_BASE 0x00000000
89 #define ZYNQ_ARMCORE_L2C_BASE 0x00002000
90
91 #define ZYNQ7000_CPU1_ENTRY 0xfffffff0
92 #define ZYNQ7000_CPU1_ENTRY_SZ 4
93
94 /* SLCR registers */
95 #define SLCR_UNLOCK 0x008
96 #define UNLOCK_KEY 0xdf0d
97 #define PSS_RST_CTRL 0x200
98 #define SOFT_RST __BIT(0)
99
100 extern struct bus_space arm_generic_bs_tag;
101 extern struct arm32_bus_dma_tag arm_generic_dma_tag;
102
103 void zynq_platform_early_putchar(char);
104
105 static const struct pmap_devmap *
zynq_platform_devmap(void)106 zynq_platform_devmap(void)
107 {
108 static const struct pmap_devmap devmap[] = {
109 DEVMAP_ENTRY(ZYNQ_IOREG_VBASE,
110 ZYNQ_IOREG_PBASE,
111 ZYNQ_IOREG_SIZE),
112 DEVMAP_ENTRY(ZYNQ_SLCR_VBASE,
113 ZYNQ_SLCR_PBASE,
114 ZYNQ_SLCR_SIZE),
115 DEVMAP_ENTRY(ZYNQ_GPV_VBASE,
116 ZYNQ_GPV_PBASE,
117 ZYNQ_GPV_SIZE),
118 DEVMAP_ENTRY(ZYNQ_ARMCORE_VBASE,
119 ZYNQ_ARMCORE_PBASE,
120 ZYNQ_ARMCORE_SIZE),
121 DEVMAP_ENTRY(ZYNQ_OCM_VBASE,
122 ZYNQ_OCM_PBASE,
123 ZYNQ_OCM_SIZE),
124 DEVMAP_ENTRY_END
125 };
126
127 return devmap;
128 }
129
130 static void
zynq_platform_init_attach_args(struct fdt_attach_args * faa)131 zynq_platform_init_attach_args(struct fdt_attach_args *faa)
132 {
133 faa->faa_bst = &arm_generic_bs_tag;
134 faa->faa_dmat = &arm_generic_dma_tag;
135 }
136
137 void __noasan
zynq_platform_early_putchar(char c)138 zynq_platform_early_putchar(char c)
139 {
140 #ifdef CONSADDR
141 #define CONSADDR_VA ((CONSADDR - ZYNQ_IOREG_PBASE) + ZYNQ_IOREG_VBASE)
142 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
143 (volatile uint32_t *)CONSADDR_VA :
144 (volatile uint32_t *)CONSADDR;
145
146 /* QEMU needs CR_TXEN to be set and CR_TXDIS to be unset */
147 uartaddr[UART_CONTROL / 4] = CR_TXEN;
148 while ((le32toh(uartaddr[UART_CHNL_INT_STS / 4]) & STS_TEMPTY) == 0)
149 ;
150
151 uartaddr[UART_TX_RX_FIFO / 4] = htole32(c);
152 #endif
153 }
154
155 static void
zynq_platform_device_register(device_t dev,void * aux)156 zynq_platform_device_register(device_t dev, void *aux)
157 {
158 }
159
160 static u_int
zynq_platform_uart_freq(void)161 zynq_platform_uart_freq(void)
162 {
163 return ZYNQ_REF_FREQ;
164 }
165
166 #ifdef MULTIPROCESSOR
167 static int
zynq_platform_mpstart(void)168 zynq_platform_mpstart(void)
169 {
170 bus_space_tag_t bst = &arm_generic_bs_tag;
171 bus_space_handle_t bsh;
172 uint32_t val;
173 int error;
174 u_int i;
175
176 /* Invalidate all SCU cache tags and enable SCU. */
177 bsh = ZYNQ_ARMCORE_VBASE + ZYNQ_ARMCORE_SCU_BASE;
178 bus_space_write_4(bst, bsh, SCU_INV_ALL_REG, 0xffff);
179 val = bus_space_read_4(bst, bsh, SCU_CTL);
180 bus_space_write_4(bst, bsh, SCU_CTL, val | SCU_CTL_SCU_ENA);
181 armv7_dcache_wbinv_all();
182
183 /* Write start address for CPU1. */
184 error = bus_space_map(bst, ZYNQ7000_CPU1_ENTRY,
185 ZYNQ7000_CPU1_ENTRY_SZ, 0, &bsh);
186 if (error) {
187 panic("%s: Couldn't map OCM: %d", __func__, error);
188 }
189 bus_space_write_4(bst, bsh, 0, KERN_VTOPHYS((vaddr_t)cpu_mpstart));
190 bus_space_unmap(bst, bsh, ZYNQ7000_CPU1_ENTRY_SZ);
191
192 dsb(sy);
193 sev();
194
195 const u_int cpuindex = 1;
196 for (i = 0x10000000; i > 0; i--) {
197 if (cpu_hatched_p(cpuindex)) {
198 break;
199 }
200 }
201 if (i == 0) {
202 aprint_error("cpu%d: WARNING: AP failed to start\n",
203 cpuindex);
204 return EIO;
205 }
206
207 return 0;
208 }
209 #endif
210
211 #define ZYNQ_ARM_PL310_BASE ZYNQ_ARMCORE_VBASE + ZYNQ_ARMCORE_L2C_BASE
212
213 static void
zynq_platform_bootstrap(void)214 zynq_platform_bootstrap(void)
215 {
216 #if NARML2CC > 0
217 const bus_space_handle_t pl310_bh = ZYNQ_ARM_PL310_BASE;
218 arml2cc_init(&arm_generic_bs_tag, pl310_bh, 0);
219 #endif
220
221 arm_fdt_cpu_bootstrap();
222
223 void *fdt_data = __UNCONST(fdtbus_get_data());
224 const int chosen_off = fdt_path_offset(fdt_data, "/chosen");
225 if (chosen_off < 0)
226 return;
227
228 if (match_bootconf_option(boot_args, "console", "fb")) {
229 const int framebuffer_off =
230 fdt_path_offset(fdt_data, "/chosen/framebuffer");
231 if (framebuffer_off >= 0) {
232 const char *status = fdt_getprop(fdt_data,
233 framebuffer_off, "status", NULL);
234 if (status == NULL || strncmp(status, "ok", 2) == 0) {
235 fdt_setprop_string(fdt_data, chosen_off,
236 "stdout-path", "/chosen/framebuffer");
237 }
238 }
239 } else if (match_bootconf_option(boot_args, "console", "serial")) {
240 fdt_setprop_string(fdt_data, chosen_off,
241 "stdout-path", "serial0:115200n8");
242 }
243 }
244
245 static void
zynq_platform_reset(void)246 zynq_platform_reset(void)
247 {
248 bus_space_tag_t bst = &arm_generic_bs_tag;
249 bus_space_handle_t bsh = ZYNQ_SLCR_VBASE;
250
251 bus_space_write_4(bst, bsh, SLCR_UNLOCK, UNLOCK_KEY);
252 bus_space_write_4(bst, bsh, PSS_RST_CTRL, SOFT_RST);
253 }
254
255 static const struct fdt_platform zynq_platform = {
256 .fp_devmap = zynq_platform_devmap,
257 .fp_bootstrap = zynq_platform_bootstrap,
258 .fp_init_attach_args = zynq_platform_init_attach_args,
259 .fp_device_register = zynq_platform_device_register,
260 .fp_reset = zynq_platform_reset,
261 .fp_delay = a9tmr_delay,
262 .fp_uart_freq = zynq_platform_uart_freq,
263 #ifdef MULTIPROCESSOR
264 .fp_mpstart = zynq_platform_mpstart,
265 #endif
266 };
267
268
269 FDT_PLATFORM(zynq, "xlnx,zynq-7000", &zynq_platform);
270