1 /* $NetBSD: sunxi_rtc.c,v 1.10 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: sunxi_rtc.c,v 1.10 2021/01/27 03:10:20 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/mutex.h>
38
39 #include <dev/clock_subr.h>
40 #include <dev/clk/clk_backend.h>
41
42 #include <dev/fdt/fdtvar.h>
43
44 #define SUN4I_RTC_YY_MM_DD_REG 0x04
45 #define SUN4I_RTC_LEAP __BIT(22)
46 #define SUN4I_RTC_YEAR __BITS(21,16)
47 #define SUN4I_RTC_MONTH __BITS(11,8)
48 #define SUN4I_RTC_DAY __BITS(4,0)
49 #define SUN4I_RTC_HH_MM_SS_REG 0x08
50 #define SUN4I_RTC_WK_NO __BITS(31,29)
51 #define SUN4I_RTC_HOUR __BITS(20,16)
52 #define SUN4I_RTC_MINUTE __BITS(13,8)
53 #define SUN4I_RTC_SECOND __BITS(5,0)
54 #define SUN4I_RTC_BASE_YEAR 2010
55
56 #define SUN7I_RTC_YY_MM_DD_REG 0x04
57 #define SUN7I_RTC_LEAP __BIT(24)
58 #define SUN7I_RTC_YEAR __BITS(23,16)
59 #define SUN7I_RTC_MONTH __BITS(11,8)
60 #define SUN7I_RTC_DAY __BITS(4,0)
61 #define SUN7I_RTC_HH_MM_SS_REG 0x08
62 #define SUN7I_RTC_WK_NO __BITS(31,29)
63 #define SUN7I_RTC_HOUR __BITS(20,16)
64 #define SUN7I_RTC_MINUTE __BITS(13,8)
65 #define SUN7I_RTC_SECOND __BITS(5,0)
66 #define SUN7I_RTC_BASE_YEAR 1970
67
68 #define SUN6I_LOSC_CTRL_REG 0x00
69 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
70 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS __BIT(15)
71 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC __BIT(9)
72 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC __BIT(8)
73 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC __BIT(7)
74 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN __BIT(4)
75 #define SUN6I_LOSC_CTRL_EXT_OSC __BIT(0)
76
77 #define SUN6I_INTOSC_CLK_PRESCAL_REG 0x08
78 #define SUN6I_INTOSC_CLK_PRESCAL __BITS(0,4)
79
80 #define SUN6I_RTC_YY_MM_DD_REG 0x10
81 #define SUN6I_RTC_LEAP __BIT(22)
82 #define SUN6I_RTC_YEAR __BITS(21,16)
83 #define SUN6I_RTC_MONTH __BITS(11,8)
84 #define SUN6I_RTC_DAY __BITS(4,0)
85 #define SUN6I_RTC_HH_MM_SS_REG 0x14
86 #define SUN6I_RTC_WK_NO __BITS(31,29)
87 #define SUN6I_RTC_HOUR __BITS(20,16)
88 #define SUN6I_RTC_MINUTE __BITS(13,8)
89 #define SUN6I_RTC_SECOND __BITS(5,0)
90 #define SUN6I_RTC_BASE_YEAR 2000
91
92 #define SUN6I_RTC_LOSC_OUT_GATING_REG 0x60
93 #define SUN6I_RTC_LOSC_OUT_EN __BIT(0)
94
95 struct sunxi_rtc_config {
96 bus_size_t yy_mm_dd_reg;
97 uint32_t leap, year, month, day;
98 bus_size_t hh_mm_ss_reg;
99 uint32_t wk_no, hour, minute, second;
100 u_int base_year;
101
102 u_int iosc_rate;
103 u_int fixed_prescaler;
104 uint32_t ext_losc_en;
105 uint32_t auto_swt_bypass;
106 u_int flags;
107 };
108
109 #define SUNXI_RTC_F_HAS_VAR_PRESCALER __BIT(0)
110
111 static const struct sunxi_rtc_config sun4i_rtc_config = {
112 .yy_mm_dd_reg = SUN4I_RTC_YY_MM_DD_REG,
113 .leap = SUN4I_RTC_LEAP,
114 .year = SUN4I_RTC_YEAR,
115 .month = SUN4I_RTC_MONTH,
116 .day = SUN4I_RTC_DAY,
117 .hh_mm_ss_reg = SUN4I_RTC_HH_MM_SS_REG,
118 .wk_no = SUN4I_RTC_WK_NO,
119 .hour = SUN4I_RTC_HOUR,
120 .minute = SUN4I_RTC_MINUTE,
121 .second = SUN4I_RTC_SECOND,
122 .base_year = SUN4I_RTC_BASE_YEAR,
123 };
124
125 static const struct sunxi_rtc_config sun6i_a31_rtc_config = {
126 .yy_mm_dd_reg = SUN6I_RTC_YY_MM_DD_REG,
127 .leap = SUN6I_RTC_LEAP,
128 .year = SUN6I_RTC_YEAR,
129 .month = SUN6I_RTC_MONTH,
130 .day = SUN6I_RTC_DAY,
131 .hh_mm_ss_reg = SUN6I_RTC_HH_MM_SS_REG,
132 .wk_no = SUN6I_RTC_WK_NO,
133 .hour = SUN6I_RTC_HOUR,
134 .minute = SUN6I_RTC_MINUTE,
135 .second = SUN6I_RTC_SECOND,
136 .base_year = SUN6I_RTC_BASE_YEAR,
137
138 .iosc_rate = 667000,
139 .flags = SUNXI_RTC_F_HAS_VAR_PRESCALER,
140 };
141
142 static const struct sunxi_rtc_config sun7i_rtc_config = {
143 .yy_mm_dd_reg = SUN7I_RTC_YY_MM_DD_REG,
144 .leap = SUN7I_RTC_LEAP,
145 .year = SUN7I_RTC_YEAR,
146 .month = SUN7I_RTC_MONTH,
147 .day = SUN7I_RTC_DAY,
148 .hh_mm_ss_reg = SUN7I_RTC_HH_MM_SS_REG,
149 .wk_no = SUN7I_RTC_WK_NO,
150 .hour = SUN7I_RTC_HOUR,
151 .minute = SUN7I_RTC_MINUTE,
152 .second = SUN7I_RTC_SECOND,
153 .base_year = SUN7I_RTC_BASE_YEAR,
154 };
155
156 static const struct sunxi_rtc_config sun8i_a23_rtc_config = {
157 .yy_mm_dd_reg = SUN6I_RTC_YY_MM_DD_REG,
158 .leap = SUN6I_RTC_LEAP,
159 .year = SUN6I_RTC_YEAR,
160 .month = SUN6I_RTC_MONTH,
161 .day = SUN6I_RTC_DAY,
162 .hh_mm_ss_reg = SUN6I_RTC_HH_MM_SS_REG,
163 .wk_no = SUN6I_RTC_WK_NO,
164 .hour = SUN6I_RTC_HOUR,
165 .minute = SUN6I_RTC_MINUTE,
166 .second = SUN6I_RTC_SECOND,
167 .base_year = SUN6I_RTC_BASE_YEAR,
168
169 .iosc_rate = 667000,
170 .flags = SUNXI_RTC_F_HAS_VAR_PRESCALER,
171 };
172
173 static const struct sunxi_rtc_config sun8i_r40_rtc_config = {
174 .yy_mm_dd_reg = SUN6I_RTC_YY_MM_DD_REG,
175 .leap = SUN6I_RTC_LEAP,
176 .year = SUN6I_RTC_YEAR,
177 .month = SUN6I_RTC_MONTH,
178 .day = SUN6I_RTC_DAY,
179 .hh_mm_ss_reg = SUN6I_RTC_HH_MM_SS_REG,
180 .wk_no = SUN6I_RTC_WK_NO,
181 .hour = SUN6I_RTC_HOUR,
182 .minute = SUN6I_RTC_MINUTE,
183 .second = SUN6I_RTC_SECOND,
184 .base_year = SUN6I_RTC_BASE_YEAR,
185
186 .iosc_rate = 16000000,
187 .fixed_prescaler = 512,
188 };
189
190 static const struct sunxi_rtc_config sun8i_v3_rtc_config = {
191 .yy_mm_dd_reg = SUN6I_RTC_YY_MM_DD_REG,
192 .leap = SUN6I_RTC_LEAP,
193 .year = SUN6I_RTC_YEAR,
194 .month = SUN6I_RTC_MONTH,
195 .day = SUN6I_RTC_DAY,
196 .hh_mm_ss_reg = SUN6I_RTC_HH_MM_SS_REG,
197 .wk_no = SUN6I_RTC_WK_NO,
198 .hour = SUN6I_RTC_HOUR,
199 .minute = SUN6I_RTC_MINUTE,
200 .second = SUN6I_RTC_SECOND,
201 .base_year = SUN6I_RTC_BASE_YEAR,
202
203 .iosc_rate = 32000,
204 };
205
206 static const struct sunxi_rtc_config sun8i_h3_rtc_config = {
207 .yy_mm_dd_reg = SUN6I_RTC_YY_MM_DD_REG,
208 .leap = SUN6I_RTC_LEAP,
209 .year = SUN6I_RTC_YEAR,
210 .month = SUN6I_RTC_MONTH,
211 .day = SUN6I_RTC_DAY,
212 .hh_mm_ss_reg = SUN6I_RTC_HH_MM_SS_REG,
213 .wk_no = SUN6I_RTC_WK_NO,
214 .hour = SUN6I_RTC_HOUR,
215 .minute = SUN6I_RTC_MINUTE,
216 .second = SUN6I_RTC_SECOND,
217 .base_year = SUN6I_RTC_BASE_YEAR,
218
219 .iosc_rate = 16000000,
220 .fixed_prescaler = 32,
221 .flags = SUNXI_RTC_F_HAS_VAR_PRESCALER,
222 };
223
224 static const struct sunxi_rtc_config sun50i_h6_rtc_config = {
225 .yy_mm_dd_reg = SUN6I_RTC_YY_MM_DD_REG,
226 .leap = SUN6I_RTC_LEAP,
227 .year = SUN6I_RTC_YEAR,
228 .month = SUN6I_RTC_MONTH,
229 .day = SUN6I_RTC_DAY,
230 .hh_mm_ss_reg = SUN6I_RTC_HH_MM_SS_REG,
231 .wk_no = SUN6I_RTC_WK_NO,
232 .hour = SUN6I_RTC_HOUR,
233 .minute = SUN6I_RTC_MINUTE,
234 .second = SUN6I_RTC_SECOND,
235 .base_year = SUN6I_RTC_BASE_YEAR,
236
237 .iosc_rate = 16000000,
238 .fixed_prescaler = 32,
239 .auto_swt_bypass = SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS,
240 .ext_losc_en = SUN6I_LOSC_CTRL_EXT_LOSC_EN,
241 .flags = SUNXI_RTC_F_HAS_VAR_PRESCALER,
242 };
243
244 static const struct device_compatible_entry compat_data[] = {
245 { .compat = "allwinner,sun4i-a10-rtc",
246 .data = &sun4i_rtc_config },
247 { .compat = "allwinner,sun6i-a31-rtc",
248 .data = &sun6i_a31_rtc_config },
249 { .compat = "allwinner,sun7i-a20-rtc",
250 .data = &sun7i_rtc_config },
251 { .compat = "allwinner,sun8i-a23-rtc",
252 .data = &sun8i_a23_rtc_config },
253 { .compat = "allwinner,sun8i-r40-rtc",
254 .data = &sun8i_r40_rtc_config },
255 { .compat = "allwinner,sun8i-v3-rtc",
256 .data = &sun8i_v3_rtc_config },
257 { .compat = "allwinner,sun8i-h3-rtc",
258 .data = &sun8i_h3_rtc_config },
259 { .compat = "allwinner,sun50i-h5-rtc",
260 .data = &sun8i_h3_rtc_config },
261 { .compat = "allwinner,sun50i-h6-rtc",
262 .data = &sun50i_h6_rtc_config },
263
264 DEVICE_COMPAT_EOL
265 };
266
267 #define SUNXI_RTC_CLK_LOSC 0
268 #define SUNXI_RTC_CLK_LOSC_GATE 1
269 #define SUNXI_RTC_CLK_IOSC 2
270 #define SUNXI_RTC_NCLKS 3
271
272 struct sunxi_rtc_softc {
273 device_t sc_dev;
274 bus_space_tag_t sc_bst;
275 bus_space_handle_t sc_bsh;
276 struct todr_chip_handle sc_todr;
277 const struct sunxi_rtc_config *sc_conf;
278
279 int sc_phandle;
280
281 struct clk *sc_parent_clk; /* external oscillator */
282
283 /*
284 * We export up to 3 clocks:
285 * [0] The local oscillator output
286 * [1] Gated version of [0]
287 * [2] The internal oscillator
288 *
289 * The local oscillator is driven either by the internal
290 * oscillator (less precise) or an external oscillator.
291 *
292 * Note that these are the order they appear in the device
293 * tree "clock-output-names" property for our node. Not
294 * all flavors of the Allwinner SoCs export all of these
295 * clocks, so we export only those that appear in the
296 * "clock-output-names" property.
297 */
298 const char *sc_clk_names[SUNXI_RTC_NCLKS];
299 struct clk sc_clks[SUNXI_RTC_NCLKS];
300 kmutex_t sc_clk_mutex;
301 struct clk_domain sc_clkdom;
302 };
303
304 #define RTC_READ(sc, reg) \
305 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
306 #define RTC_WRITE(sc, reg, val) \
307 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
308
309 static int sunxi_rtc_match(device_t, cfdata_t, void *);
310 static void sunxi_rtc_attach(device_t, device_t, void *);
311
312 static int sunxi_rtc_gettime(todr_chip_handle_t, struct clock_ymdhms *);
313 static int sunxi_rtc_settime(todr_chip_handle_t, struct clock_ymdhms *);
314
315 static struct clk *
316 sunxi_rtc_clk_get(void *, const char *);
317 static u_int sunxi_rtc_clk_get_rate(void *, struct clk *);
318 static int sunxi_rtc_clk_enable(void *, struct clk *);
319 static int sunxi_rtc_clk_disable(void *, struct clk *);
320 static int sunxi_rtc_clk_set_parent(void *, struct clk *, struct clk *);
321 static struct clk *
322 sunxi_rtc_clk_get_parent(void *, struct clk *);
323
324 static const struct clk_funcs sunxi_rtc_clk_funcs = {
325 .get = sunxi_rtc_clk_get,
326 .get_rate = sunxi_rtc_clk_get_rate,
327 .enable = sunxi_rtc_clk_enable,
328 .disable = sunxi_rtc_clk_disable,
329 .set_parent = sunxi_rtc_clk_set_parent,
330 .get_parent = sunxi_rtc_clk_get_parent,
331 };
332
333 static struct clk *
sunxi_rtc_clock_decode(device_t dev,int cc_phandle,const void * data,size_t len)334 sunxi_rtc_clock_decode(device_t dev, int cc_phandle, const void *data,
335 size_t len)
336 {
337 struct sunxi_rtc_softc * const sc = device_private(dev);
338
339 if (len != 4)
340 return NULL;
341
342 const u_int clock_id = be32dec(data);
343 if (clock_id >= SUNXI_RTC_NCLKS)
344 return NULL;
345
346 if (sc->sc_clk_names[clock_id] == NULL)
347 return NULL;
348
349 return &sc->sc_clks[clock_id];
350 }
351
352 static const struct fdtbus_clock_controller_func sunxi_rtc_fdtclock_funcs = {
353 .decode = sunxi_rtc_clock_decode,
354 };
355
356 CFATTACH_DECL_NEW(sunxi_rtc, sizeof(struct sunxi_rtc_softc),
357 sunxi_rtc_match, sunxi_rtc_attach, NULL, NULL);
358
359 static int
sunxi_rtc_match(device_t parent,cfdata_t cf,void * aux)360 sunxi_rtc_match(device_t parent, cfdata_t cf, void *aux)
361 {
362 struct fdt_attach_args * const faa = aux;
363
364 return of_compatible_match(faa->faa_phandle, compat_data);
365 }
366
367 static void
sunxi_rtc_attach(device_t parent,device_t self,void * aux)368 sunxi_rtc_attach(device_t parent, device_t self, void *aux)
369 {
370 struct sunxi_rtc_softc * const sc = device_private(self);
371 struct fdt_attach_args * const faa = aux;
372 const int phandle = faa->faa_phandle;
373 bus_addr_t addr;
374 bus_size_t size;
375
376 sc->sc_phandle = phandle;
377
378 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
379 aprint_error(": couldn't get registers\n");
380 return;
381 }
382
383 sc->sc_dev = self;
384 sc->sc_bst = faa->faa_bst;
385 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
386 aprint_error(": couldn't map registers\n");
387 return;
388 }
389 sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data;
390
391 aprint_naive("\n");
392 aprint_normal(": RTC\n");
393
394 mutex_init(&sc->sc_clk_mutex, MUTEX_DEFAULT, IPL_HIGH);
395
396 sc->sc_todr.cookie = sc;
397 sc->sc_todr.todr_gettime_ymdhms = sunxi_rtc_gettime;
398 sc->sc_todr.todr_settime_ymdhms = sunxi_rtc_settime;
399
400 fdtbus_todr_attach(self, phandle, &sc->sc_todr);
401
402 sc->sc_parent_clk = fdtbus_clock_get_index(phandle, 0);
403
404 if (sc->sc_parent_clk == NULL || sc->sc_conf->iosc_rate == 0)
405 return;
406
407 uint32_t reg = SUN6I_LOSC_CTRL_KEY;
408 if (sc->sc_conf->auto_swt_bypass) {
409 /*
410 * Disable auto-switching to the internal oscillator
411 * if the external oscillator disappears.
412 */
413 reg |= sc->sc_conf->auto_swt_bypass;
414 RTC_WRITE(sc, SUN6I_LOSC_CTRL_REG, reg);
415 }
416
417 /* Switch to the external oscillator by default. */
418 reg |= SUN6I_LOSC_CTRL_EXT_OSC | sc->sc_conf->ext_losc_en;
419 RTC_WRITE(sc, SUN6I_LOSC_CTRL_REG, reg);
420
421 sc->sc_clkdom.name = device_xname(sc->sc_dev);
422 sc->sc_clkdom.funcs = &sunxi_rtc_clk_funcs;
423 sc->sc_clkdom.priv = sc;
424
425 unsigned int i;
426 for (i = 0; i < SUNXI_RTC_NCLKS; i++) {
427 sc->sc_clk_names[i] = fdtbus_get_string_index(phandle,
428 "clock-output-names", i);
429 if (sc->sc_clk_names[i] == NULL)
430 break;
431 sc->sc_clks[i].domain = &sc->sc_clkdom;
432 sc->sc_clks[i].name = sc->sc_clk_names[i];
433 clk_attach(&sc->sc_clks[i]);
434 }
435
436 fdtbus_register_clock_controller(sc->sc_dev, sc->sc_phandle,
437 &sunxi_rtc_fdtclock_funcs);
438 }
439
440 static int
sunxi_rtc_gettime(todr_chip_handle_t tch,struct clock_ymdhms * dt)441 sunxi_rtc_gettime(todr_chip_handle_t tch, struct clock_ymdhms *dt)
442 {
443 struct sunxi_rtc_softc *sc = tch->cookie;
444 const struct sunxi_rtc_config *conf = sc->sc_conf;
445
446 const uint32_t yymmdd = RTC_READ(sc, conf->yy_mm_dd_reg);
447 const uint32_t hhmmss = RTC_READ(sc, conf->hh_mm_ss_reg);
448
449 dt->dt_year = __SHIFTOUT(yymmdd, conf->year) + conf->base_year;
450 dt->dt_mon = __SHIFTOUT(yymmdd, conf->month);
451 dt->dt_day = __SHIFTOUT(yymmdd, conf->day);
452 dt->dt_wday = __SHIFTOUT(hhmmss, conf->wk_no);
453 dt->dt_hour = __SHIFTOUT(hhmmss, conf->hour);
454 dt->dt_min = __SHIFTOUT(hhmmss, conf->minute);
455 dt->dt_sec = __SHIFTOUT(hhmmss, conf->second);
456
457 return 0;
458 }
459
460 static int
sunxi_rtc_settime(todr_chip_handle_t tch,struct clock_ymdhms * dt)461 sunxi_rtc_settime(todr_chip_handle_t tch, struct clock_ymdhms *dt)
462 {
463 struct sunxi_rtc_softc *sc = tch->cookie;
464 const struct sunxi_rtc_config *conf = sc->sc_conf;
465 uint32_t yymmdd, hhmmss, maxyear;
466
467 /*
468 * Sanity check the date before writing it back
469 */
470 if (dt->dt_year < conf->base_year) {
471 aprint_normal_dev(sc->sc_dev, "year pre the epoch: %" PRIu64
472 ", not writing back time\n", dt->dt_year);
473 return EIO;
474 }
475 maxyear = __SHIFTOUT(0xffffffff, conf->year) + conf->base_year;
476 if (dt->dt_year > maxyear) {
477 aprint_normal_dev(sc->sc_dev, "year exceeds available field:"
478 " %" PRIu64 ", not writing back time\n", dt->dt_year);
479 return EIO;
480 }
481
482 yymmdd = __SHIFTIN(dt->dt_year - conf->base_year, conf->year);
483 yymmdd |= __SHIFTIN(dt->dt_mon, conf->month);
484 yymmdd |= __SHIFTIN(dt->dt_day, conf->day);
485
486 hhmmss = __SHIFTIN(dt->dt_wday, conf->wk_no);
487 hhmmss |= __SHIFTIN(dt->dt_hour, conf->hour);
488 hhmmss |= __SHIFTIN(dt->dt_min, conf->minute);
489 hhmmss |= __SHIFTIN(dt->dt_sec, conf->second);
490
491 RTC_WRITE(sc, conf->yy_mm_dd_reg, yymmdd);
492 RTC_WRITE(sc, conf->hh_mm_ss_reg, hhmmss);
493
494 return 0;
495 }
496
497 static struct clk *
sunxi_rtc_clk_get(void * priv,const char * name)498 sunxi_rtc_clk_get(void *priv, const char *name)
499 {
500 struct sunxi_rtc_softc * const sc = priv;
501 u_int i;
502
503 for (i = 0; i < SUNXI_RTC_NCLKS; i++) {
504 if (sc->sc_clk_names[i] != NULL &&
505 strcmp(sc->sc_clk_names[i], name) == 0) {
506 return &sc->sc_clks[i];
507 }
508 }
509
510 return NULL;
511 }
512
513 static u_int
sunxi_rtc_clk_get_rate(void * priv,struct clk * clk)514 sunxi_rtc_clk_get_rate(void *priv, struct clk *clk)
515 {
516 struct sunxi_rtc_softc * const sc = priv;
517
518 if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC]) {
519 KASSERT(sc->sc_clk_names[SUNXI_RTC_CLK_IOSC] != NULL);
520 KASSERT(sc->sc_conf->iosc_rate != 0);
521 return sc->sc_conf->iosc_rate;
522 }
523
524 KASSERT(sc->sc_parent_clk != NULL);
525 u_int parent_rate = clk_get_rate(sc->sc_parent_clk);
526 uint32_t prescaler = 0;
527
528 if (RTC_READ(sc, SUN6I_LOSC_CTRL_REG) & SUN6I_LOSC_CTRL_EXT_OSC)
529 return parent_rate;
530
531 if (sc->sc_conf->fixed_prescaler)
532 parent_rate /= sc->sc_conf->fixed_prescaler;
533
534 if (sc->sc_conf->flags & SUNXI_RTC_F_HAS_VAR_PRESCALER) {
535 prescaler =
536 __SHIFTOUT(RTC_READ(sc, SUN6I_INTOSC_CLK_PRESCAL_REG),
537 SUN6I_INTOSC_CLK_PRESCAL);
538 }
539
540 return parent_rate / (prescaler + 1);
541 }
542
543 static int
sunxi_rtc_clk_enable(void * priv,struct clk * clk)544 sunxi_rtc_clk_enable(void *priv, struct clk *clk)
545 {
546 struct sunxi_rtc_softc * const sc = priv;
547
548 if (clk != &sc->sc_clks[SUNXI_RTC_CLK_LOSC_GATE])
549 return 0;
550
551 mutex_enter(&sc->sc_clk_mutex);
552 uint32_t reg = RTC_READ(sc, SUN6I_RTC_LOSC_OUT_GATING_REG);
553 if ((reg & SUN6I_RTC_LOSC_OUT_EN) == 0) {
554 reg |= SUN6I_RTC_LOSC_OUT_EN;
555 RTC_WRITE(sc, SUN6I_RTC_LOSC_OUT_GATING_REG, reg);
556 }
557 mutex_exit(&sc->sc_clk_mutex);
558
559 return 0;
560 }
561
562 static int
sunxi_rtc_clk_disable(void * priv,struct clk * clk)563 sunxi_rtc_clk_disable(void *priv, struct clk *clk)
564 {
565 struct sunxi_rtc_softc * const sc = priv;
566
567 if (clk != &sc->sc_clks[SUNXI_RTC_CLK_LOSC_GATE])
568 return EINVAL;
569
570 mutex_enter(&sc->sc_clk_mutex);
571 uint32_t reg = RTC_READ(sc, SUN6I_RTC_LOSC_OUT_GATING_REG);
572 if (reg & SUN6I_RTC_LOSC_OUT_EN) {
573 reg &= ~SUN6I_RTC_LOSC_OUT_EN;
574 RTC_WRITE(sc, SUN6I_RTC_LOSC_OUT_GATING_REG, reg);
575 }
576 mutex_exit(&sc->sc_clk_mutex);
577
578 return 0;
579 }
580
581 static int
sunxi_rtc_clk_set_parent(void * priv,struct clk * clk,struct clk * parent_clk)582 sunxi_rtc_clk_set_parent(void *priv, struct clk *clk, struct clk *parent_clk)
583 {
584 struct sunxi_rtc_softc * const sc = priv;
585
586 if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC])
587 return EINVAL;
588
589 if (parent_clk != sc->sc_parent_clk &&
590 parent_clk != &sc->sc_clks[SUNXI_RTC_CLK_IOSC])
591 return EINVAL;
592
593 mutex_enter(&sc->sc_clk_mutex);
594 uint32_t reg = RTC_READ(sc, SUN6I_LOSC_CTRL_REG);
595 if (parent_clk == sc->sc_parent_clk)
596 reg |= SUN6I_LOSC_CTRL_EXT_OSC | sc->sc_conf->ext_losc_en;
597 else
598 reg &= ~(SUN6I_LOSC_CTRL_EXT_OSC | sc->sc_conf->ext_losc_en);
599 RTC_WRITE(sc, SUN6I_LOSC_CTRL_REG, reg | SUN6I_LOSC_CTRL_KEY);
600 mutex_exit(&sc->sc_clk_mutex);
601
602 return 0;
603 }
604
605 static struct clk *
sunxi_rtc_clk_get_parent(void * priv,struct clk * clk)606 sunxi_rtc_clk_get_parent(void *priv, struct clk *clk)
607 {
608 struct sunxi_rtc_softc * const sc = priv;
609 uint32_t reg;
610
611 if (clk == &sc->sc_clks[SUNXI_RTC_CLK_IOSC])
612 return NULL;
613
614 reg = RTC_READ(sc, SUN6I_LOSC_CTRL_REG);
615 if (reg & SUN6I_LOSC_CTRL_EXT_OSC)
616 return sc->sc_parent_clk;
617
618 /*
619 * We switch to the external oscillator at attach time becacuse
620 * it's higher quality than the internal one. If we haven't
621 * exported the internal oscillator to the clock tree, then
622 * we shouldn't get here.
623 */
624 KASSERT(sc->sc_clk_names[SUNXI_RTC_CLK_IOSC] != NULL);
625 return &sc->sc_clks[SUNXI_RTC_CLK_IOSC];
626 }
627