1 /* $NetBSD: sunxi_pwm.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: sunxi_pwm.c,v 1.7 2021/01/27 03:10:20 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/intr.h>
37 #include <sys/systm.h>
38 #include <sys/time.h>
39
40 #include <dev/pwm/pwmvar.h>
41
42 #include <dev/fdt/fdtvar.h>
43
44 #define PWM_CH_CTRL 0x00
45 #define PWM0_RDY __BIT(28)
46 #define PWM0_BYPASS __BIT(9)
47 #define PWM_CH0_PUL_START __BIT(8)
48 #define PWM_CHANNEL0_MODE __BIT(7)
49 #define SCLK_CH0_GATING __BIT(6)
50 #define PWM_CH0_ACT_STA __BIT(5)
51 #define PWM_CH0_EN __BIT(4)
52 #define PWM_CH0_PRESCAL __BITS(3,0)
53 #define PWM_CH0_PERIOD 0x04
54 #define PWM_CH0_ENTIRE_CYS __BITS(31,16)
55 #define PWM_CH0_ENTIRE_ACT_CYS __BITS(15,0)
56
57 enum sunxi_pwm_type {
58 PWM_A64 = 1,
59 };
60
61 static const struct device_compatible_entry compat_data[] = {
62 { .compat = "allwinner,sun50i-a64-pwm", .value = PWM_A64 },
63 DEVICE_COMPAT_EOL
64 };
65
66 struct sunxi_pwm_softc {
67 device_t sc_dev;
68 bus_space_tag_t sc_bst;
69 bus_space_handle_t sc_bsh;
70
71 struct pwm_controller sc_pwm;
72 struct pwm_config sc_conf;
73
74 u_int sc_clkfreq;
75 };
76
77 #define PWM_READ(sc, reg) \
78 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
79 #define PWM_WRITE(sc, reg, val) \
80 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
81
82 static pwm_tag_t
sunxi_pwm_get_tag(device_t dev,const void * data,size_t len)83 sunxi_pwm_get_tag(device_t dev, const void *data, size_t len)
84 {
85 struct sunxi_pwm_softc * const sc = device_private(dev);
86 const u_int *pwm = data;
87
88 if (len != 16)
89 return NULL;
90
91 const u_int index = be32toh(pwm[1]);
92 if (index != 0)
93 return NULL;
94
95 const u_int period = be32toh(pwm[2]);
96 const u_int polarity = be32toh(pwm[3]);
97
98 sc->sc_conf.period = period;
99 sc->sc_conf.polarity = polarity ? PWM_ACTIVE_LOW : PWM_ACTIVE_HIGH;
100
101 return &sc->sc_pwm;
102 }
103
104 static struct fdtbus_pwm_controller_func sunxi_pwm_funcs = {
105 .get_tag = sunxi_pwm_get_tag
106 };
107
108 static int
sunxi_pwm_enable(pwm_tag_t pwm,bool enable)109 sunxi_pwm_enable(pwm_tag_t pwm, bool enable)
110 {
111 struct sunxi_pwm_softc * const sc = device_private(pwm->pwm_dev);
112 uint32_t ctrl, octrl;
113
114 octrl = ctrl = PWM_READ(sc, PWM_CH_CTRL);
115 if (enable)
116 ctrl |= (PWM_CH0_EN | SCLK_CH0_GATING);
117 else
118 ctrl &= ~(PWM_CH0_EN | SCLK_CH0_GATING);
119
120 if (ctrl != octrl)
121 PWM_WRITE(sc, PWM_CH_CTRL, ctrl);
122
123 return 0;
124 }
125
126 static int
sunxi_pwm_get_config(pwm_tag_t pwm,struct pwm_config * conf)127 sunxi_pwm_get_config(pwm_tag_t pwm, struct pwm_config *conf)
128 {
129 struct sunxi_pwm_softc * const sc = device_private(pwm->pwm_dev);
130 uint32_t ctrl, ch_period;
131
132 ctrl = PWM_READ(sc, PWM_CH_CTRL);
133 ch_period = PWM_READ(sc, PWM_CH0_PERIOD);
134
135 const uint64_t rate = sc->sc_clkfreq / 120;
136 const u_int cycles = __SHIFTOUT(ch_period, PWM_CH0_ENTIRE_CYS) + 1;
137 const u_int act_cycles = __SHIFTOUT(ch_period, PWM_CH0_ENTIRE_ACT_CYS);
138
139 conf->polarity = (ctrl & PWM_CH0_ACT_STA) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
140 conf->period = (u_int)(((uint64_t)cycles * 1000000000) / rate);
141 conf->duty_cycle = (u_int)(((uint64_t)act_cycles * 1000000000) / rate);
142
143 return 0;
144 }
145
146 static int
sunxi_pwm_set_config(pwm_tag_t pwm,const struct pwm_config * conf)147 sunxi_pwm_set_config(pwm_tag_t pwm, const struct pwm_config *conf)
148 {
149 struct sunxi_pwm_softc * const sc = device_private(pwm->pwm_dev);
150 uint32_t ctrl, ch_period;
151
152 ctrl = PWM_READ(sc, PWM_CH_CTRL);
153 if (ctrl & PWM0_RDY)
154 return EBUSY;
155
156 ctrl &= ~PWM0_BYPASS; /* Prescaler /120 = 200 kHz */
157 ctrl &= ~PWM_CH0_PRESCAL;
158 ctrl |= __SHIFTIN(0, PWM_CH0_PRESCAL);
159
160 ctrl &= ~PWM_CHANNEL0_MODE; /* Cycle mode */
161 if (conf->polarity == PWM_ACTIVE_HIGH)
162 ctrl |= PWM_CH0_ACT_STA;
163 else
164 ctrl &= ~PWM_CH0_ACT_STA;
165
166 const uint64_t rate = sc->sc_clkfreq / 120;
167 const u_int cycles = (u_int)((conf->period * rate) / 1000000000);
168 const u_int act_cycles = (u_int)((conf->duty_cycle * rate) / 1000000000);
169
170 ch_period = __SHIFTIN(cycles - 1, PWM_CH0_ENTIRE_CYS);
171 ch_period |= __SHIFTIN(act_cycles, PWM_CH0_ENTIRE_ACT_CYS);
172
173 PWM_WRITE(sc, PWM_CH0_PERIOD, ch_period);
174 PWM_WRITE(sc, PWM_CH_CTRL, ctrl);
175
176 sc->sc_conf = *conf;
177
178 return 0;
179 }
180
181 static int
sunxi_pwm_match(device_t parent,cfdata_t cf,void * aux)182 sunxi_pwm_match(device_t parent, cfdata_t cf, void *aux)
183 {
184 struct fdt_attach_args * const faa = aux;
185
186 return of_compatible_match(faa->faa_phandle, compat_data);
187 }
188
189 static void
sunxi_pwm_attach(device_t parent,device_t self,void * aux)190 sunxi_pwm_attach(device_t parent, device_t self, void *aux)
191 {
192 struct sunxi_pwm_softc * const sc = device_private(self);
193 struct fdt_attach_args * const faa = aux;
194 const int phandle = faa->faa_phandle;
195 struct clk *clk;
196 bus_addr_t addr;
197 bus_size_t size;
198 int error;
199
200 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
201 aprint_error(": couldn't get registers\n");
202 return;
203 }
204
205 clk = fdtbus_clock_get_index(phandle, 0);
206 if (clk == NULL) {
207 aprint_error(": couldn't get clock\n");
208 return;
209 }
210
211 sc->sc_dev = self;
212 sc->sc_clkfreq = clk_get_rate(clk);
213 sc->sc_bst = faa->faa_bst;
214 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
215 if (error) {
216 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d",
217 addr, error);
218 return;
219 }
220
221 aprint_naive("\n");
222 aprint_normal(": PWM\n");
223
224 sc->sc_pwm.pwm_enable = sunxi_pwm_enable;
225 sc->sc_pwm.pwm_get_config = sunxi_pwm_get_config;
226 sc->sc_pwm.pwm_set_config = sunxi_pwm_set_config;
227 sc->sc_pwm.pwm_dev = self;
228
229 fdtbus_register_pwm_controller(self, phandle,
230 &sunxi_pwm_funcs);
231 }
232
233 CFATTACH_DECL_NEW(sunxi_pwm, sizeof(struct sunxi_pwm_softc),
234 sunxi_pwm_match, sunxi_pwm_attach, NULL, NULL);
235