1 /* $NetBSD: sunxi_i2s.c,v 1.12 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: sunxi_i2s.c,v 1.12 2021/01/27 03:10:20 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/cpu.h>
35 #include <sys/device.h>
36 #include <sys/kmem.h>
37 #include <sys/gpio.h>
38
39 #include <sys/audioio.h>
40 #include <dev/audio/audio_if.h>
41 #include <dev/audio/linear.h>
42
43 #include <dev/fdt/fdtvar.h>
44
45 #define SUNXI_I2S_CLK_RATE 24576000
46 #define SUNXI_I2S_SAMPLE_RATE 48000
47
48 #define DA_CTL 0x00
49 #define DA_CTL_BCLK_OUT __BIT(18) /* sun8i */
50 #define DA_CLK_LRCK_OUT __BIT(17) /* sun8i */
51 #define DA_CTL_SDO_EN __BIT(8)
52 #define DA_CTL_MS __BIT(5) /* sun4i */
53 #define DA_CTL_PCM __BIT(4) /* sun4i */
54 #define DA_CTL_MODE_SEL __BITS(5,4) /* sun8i */
55 #define DA_CTL_MODE_SEL_PCM 0
56 #define DA_CTL_MODE_SEL_LJ 1
57 #define DA_CTL_MODE_SEL_RJ 2
58 #define DA_CTL_TXEN __BIT(2)
59 #define DA_CTL_RXEN __BIT(1)
60 #define DA_CTL_GEN __BIT(0)
61 #define DA_FAT0 0x04
62 #define DA_FAT0_LRCK_PERIOD __BITS(17,8) /* sun8i */
63 #define DA_FAT0_LRCP __BIT(7)
64 #define DA_LRCP_NORMAL 0
65 #define DA_LRCP_INVERTED 1
66 #define DA_FAT0_BCP __BIT(6)
67 #define DA_BCP_NORMAL 0
68 #define DA_BCP_INVERTED 1
69 #define DA_FAT0_SR __BITS(5,4)
70 #define DA_FAT0_WSS __BITS(3,2)
71 #define DA_FAT0_FMT __BITS(1,0)
72 #define DA_FMT_I2S 0
73 #define DA_FMT_LJ 1
74 #define DA_FMT_RJ 2
75 #define DA_FAT1 0x08
76 #define DA_ISTA 0x0c
77 #define DA_RXFIFO 0x10
78 #define DA_FCTL 0x14
79 #define DA_FCTL_HUB_EN __BIT(31)
80 #define DA_FCTL_FTX __BIT(25)
81 #define DA_FCTL_FRX __BIT(24)
82 #define DA_FCTL_TXIM __BIT(2)
83 #define DA_FCTL_RXIM __BITS(1,0)
84 #define DA_FSTA 0x18
85 #define DA_INT 0x1c
86 #define DA_INT_TX_DRQ __BIT(7)
87 #define DA_INT_RX_DRQ __BIT(3)
88 #define DA_TXFIFO 0x20
89 #define DA_CLKD 0x24
90 #define DA_CLKD_MCLKO_EN_SUN8I __BIT(8)
91 #define DA_CLKD_MCLKO_EN_SUN4I __BIT(7)
92 #define DA_CLKD_BCLKDIV_SUN8I __BITS(7,4)
93 #define DA_CLKD_BCLKDIV_SUN4I __BITS(6,4)
94 #define DA_CLKD_BCLKDIV_8 3
95 #define DA_CLKD_BCLKDIV_16 5
96 #define DA_CLKD_MCLKDIV __BITS(3,0)
97 #define DA_CLKD_MCLKDIV_1 0
98 #define DA_TXCNT 0x28
99 #define DA_RXCNT 0x2c
100 #define DA_CHCFG 0x30 /* sun8i */
101 #define DA_CHCFG_TX_SLOT_HIZ __BIT(9)
102 #define DA_CHCFG_TXN_STATE __BIT(8)
103 #define DA_CHCFG_RX_SLOT_NUM __BITS(6,4)
104 #define DA_CHCFG_TX_SLOT_NUM __BITS(2,0)
105
106 #define DA_CHSEL_OFFSET __BITS(13,12) /* sun8i */
107 #define DA_CHSEL_EN __BITS(11,4)
108 #define DA_CHSEL_SEL __BITS(2,0)
109
110 enum sunxi_i2s_type {
111 SUNXI_I2S_SUN4I,
112 SUNXI_I2S_SUN8I,
113 };
114
115 struct sunxi_i2s_config {
116 const char *name;
117 enum sunxi_i2s_type type;
118 bus_size_t txchsel;
119 bus_size_t txchmap;
120 bus_size_t rxchsel;
121 bus_size_t rxchmap;
122 };
123
124 static const struct sunxi_i2s_config sun50i_a64_codec_config = {
125 .name = "Audio Codec (digital part)",
126 .type = SUNXI_I2S_SUN4I,
127 .txchsel = 0x30,
128 .txchmap = 0x34,
129 .rxchsel = 0x38,
130 .rxchmap = 0x3c,
131 };
132
133 static const struct sunxi_i2s_config sun8i_h3_config = {
134 .name = "I2S/PCM controller",
135 .type = SUNXI_I2S_SUN8I,
136 .txchsel = 0x34,
137 .txchmap = 0x44,
138 .rxchsel = 0x54,
139 .rxchmap = 0x58,
140 };
141
142 static const struct device_compatible_entry compat_data[] = {
143 { .compat = "allwinner,sun50i-a64-codec-i2s",
144 .data = &sun50i_a64_codec_config },
145 { .compat = "allwinner,sun8i-h3-i2s",
146 .data = &sun8i_h3_config },
147
148 DEVICE_COMPAT_EOL
149 };
150
151 struct sunxi_i2s_softc;
152
153 struct sunxi_i2s_chan {
154 struct sunxi_i2s_softc *ch_sc;
155 u_int ch_mode;
156
157 struct fdtbus_dma *ch_dma;
158 struct fdtbus_dma_req ch_req;
159
160 audio_params_t ch_params;
161
162 bus_addr_t ch_start_phys;
163 bus_addr_t ch_end_phys;
164 bus_addr_t ch_cur_phys;
165 int ch_blksize;
166
167 void (*ch_intr)(void *);
168 void *ch_intrarg;
169 };
170
171 struct sunxi_i2s_dma {
172 LIST_ENTRY(sunxi_i2s_dma) dma_list;
173 bus_dmamap_t dma_map;
174 void *dma_addr;
175 size_t dma_size;
176 bus_dma_segment_t dma_segs[1];
177 int dma_nsegs;
178 };
179
180 struct sunxi_i2s_softc {
181 device_t sc_dev;
182 bus_space_tag_t sc_bst;
183 bus_space_handle_t sc_bsh;
184 bus_dma_tag_t sc_dmat;
185 int sc_phandle;
186 bus_addr_t sc_baseaddr;
187 struct clk *sc_clk;
188
189 const struct sunxi_i2s_config *sc_cfg;
190
191 LIST_HEAD(, sunxi_i2s_dma) sc_dmalist;
192
193 kmutex_t sc_lock;
194 kmutex_t sc_intr_lock;
195
196 struct audio_format sc_format;
197
198 struct sunxi_i2s_chan sc_pchan;
199 struct sunxi_i2s_chan sc_rchan;
200
201 struct audio_dai_device sc_dai;
202 };
203
204 #define I2S_TYPE(sc) ((sc)->sc_cfg->type)
205
206 #define I2S_READ(sc, reg) \
207 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
208 #define I2S_WRITE(sc, reg, val) \
209 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
210
211 static const u_int sun4i_i2s_bclk_divmap[] = {
212 [0] = 2,
213 [1] = 4,
214 [2] = 6,
215 [3] = 8,
216 [4] = 12,
217 [5] = 16,
218 };
219
220 static const u_int sun4i_i2s_mclk_divmap[] = {
221 [0] = 1,
222 [1] = 2,
223 [2] = 4,
224 [3] = 6,
225 [4] = 8,
226 [5] = 12,
227 [6] = 16,
228 [7] = 24,
229 };
230
231 static const u_int sun8i_i2s_divmap[] = {
232 [1] = 1,
233 [2] = 2,
234 [3] = 4,
235 [4] = 6,
236 [5] = 8,
237 [6] = 12,
238 [7] = 16,
239 [8] = 24,
240 [9] = 32,
241 [10] = 48,
242 [11] = 64,
243 [12] = 96,
244 [13] = 128,
245 [14] = 176,
246 [15] = 192,
247 };
248
249 static u_int
sunxi_i2s_div_to_regval(const u_int * divmap,u_int divmaplen,u_int div)250 sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div)
251 {
252 u_int n;
253
254 for (n = 0; n < divmaplen; n++)
255 if (divmap[n] == div)
256 return n;
257
258 return -1;
259 }
260
261 static int
sunxi_i2s_allocdma(struct sunxi_i2s_softc * sc,size_t size,size_t align,struct sunxi_i2s_dma * dma)262 sunxi_i2s_allocdma(struct sunxi_i2s_softc *sc, size_t size,
263 size_t align, struct sunxi_i2s_dma *dma)
264 {
265 int error;
266
267 dma->dma_size = size;
268 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0,
269 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK);
270 if (error)
271 return error;
272
273 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs,
274 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
275 if (error)
276 goto free;
277
278 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs,
279 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map);
280 if (error)
281 goto unmap;
282
283 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr,
284 dma->dma_size, NULL, BUS_DMA_WAITOK);
285 if (error)
286 goto destroy;
287
288 return 0;
289
290 destroy:
291 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
292 unmap:
293 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size);
294 free:
295 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs);
296
297 return error;
298 }
299
300 static void
sunxi_i2s_freedma(struct sunxi_i2s_softc * sc,struct sunxi_i2s_dma * dma)301 sunxi_i2s_freedma(struct sunxi_i2s_softc *sc, struct sunxi_i2s_dma *dma)
302 {
303 bus_dmamap_unload(sc->sc_dmat, dma->dma_map);
304 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
305 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size);
306 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs);
307 }
308
309 static int
sunxi_i2s_transfer(struct sunxi_i2s_chan * ch)310 sunxi_i2s_transfer(struct sunxi_i2s_chan *ch)
311 {
312 bus_dma_segment_t seg;
313
314 seg.ds_addr = ch->ch_cur_phys;
315 seg.ds_len = ch->ch_blksize;
316 ch->ch_req.dreq_segs = &seg;
317 ch->ch_req.dreq_nsegs = 1;
318
319 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req);
320 }
321
322 static int
sunxi_i2s_query_format(void * priv,audio_format_query_t * afp)323 sunxi_i2s_query_format(void *priv, audio_format_query_t *afp)
324 {
325 struct sunxi_i2s_softc * const sc = priv;
326
327 return audio_query_format(&sc->sc_format, 1, afp);
328 }
329
330 static int
sunxi_i2s_set_format(void * priv,int setmode,const audio_params_t * play,const audio_params_t * rec,audio_filter_reg_t * pfil,audio_filter_reg_t * rfil)331 sunxi_i2s_set_format(void *priv, int setmode,
332 const audio_params_t *play, const audio_params_t *rec,
333 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
334 {
335
336 return 0;
337 }
338
339 static void *
sunxi_i2s_allocm(void * priv,int dir,size_t size)340 sunxi_i2s_allocm(void *priv, int dir, size_t size)
341 {
342 struct sunxi_i2s_softc * const sc = priv;
343 struct sunxi_i2s_dma *dma;
344 int error;
345
346 dma = kmem_alloc(sizeof(*dma), KM_SLEEP);
347
348 error = sunxi_i2s_allocdma(sc, size, 16, dma);
349 if (error) {
350 kmem_free(dma, sizeof(*dma));
351 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n",
352 error);
353 return NULL;
354 }
355
356 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list);
357
358 return dma->dma_addr;
359 }
360
361 static void
sunxi_i2s_freem(void * priv,void * addr,size_t size)362 sunxi_i2s_freem(void *priv, void *addr, size_t size)
363 {
364 struct sunxi_i2s_softc * const sc = priv;
365 struct sunxi_i2s_dma *dma;
366
367 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list)
368 if (dma->dma_addr == addr) {
369 sunxi_i2s_freedma(sc, dma);
370 LIST_REMOVE(dma, dma_list);
371 kmem_free(dma, sizeof(*dma));
372 break;
373 }
374 }
375
376 static int
sunxi_i2s_get_props(void * priv)377 sunxi_i2s_get_props(void *priv)
378 {
379 struct sunxi_i2s_softc * const sc = priv;
380 int props = 0;
381
382 if (sc->sc_pchan.ch_dma != NULL)
383 props |= AUDIO_PROP_PLAYBACK;
384 if (sc->sc_rchan.ch_dma != NULL)
385 props |= AUDIO_PROP_CAPTURE;
386 if (sc->sc_pchan.ch_dma != NULL && sc->sc_rchan.ch_dma != NULL)
387 props |= AUDIO_PROP_FULLDUPLEX;
388
389 return props;
390 }
391
392 static int
sunxi_i2s_trigger_output(void * priv,void * start,void * end,int blksize,void (* intr)(void *),void * intrarg,const audio_params_t * params)393 sunxi_i2s_trigger_output(void *priv, void *start, void *end, int blksize,
394 void (*intr)(void *), void *intrarg, const audio_params_t *params)
395 {
396 struct sunxi_i2s_softc * const sc = priv;
397 struct sunxi_i2s_chan *ch = &sc->sc_pchan;
398 struct sunxi_i2s_dma *dma;
399 bus_addr_t pstart;
400 bus_size_t psize;
401 uint32_t val;
402 int error;
403
404 if (ch->ch_dma == NULL)
405 return EIO;
406
407 pstart = 0;
408 psize = (uintptr_t)end - (uintptr_t)start;
409
410 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list)
411 if (dma->dma_addr == start) {
412 pstart = dma->dma_map->dm_segs[0].ds_addr;
413 break;
414 }
415 if (pstart == 0) {
416 device_printf(sc->sc_dev, "bad addr %p\n", start);
417 return EINVAL;
418 }
419
420 ch->ch_intr = intr;
421 ch->ch_intrarg = intrarg;
422 ch->ch_start_phys = ch->ch_cur_phys = pstart;
423 ch->ch_end_phys = pstart + psize;
424 ch->ch_blksize = blksize;
425
426 /* Flush FIFO */
427 val = I2S_READ(sc, DA_FCTL);
428 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX);
429 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX);
430
431 /* Reset TX sample counter */
432 I2S_WRITE(sc, DA_TXCNT, 0);
433
434 /* Enable transmitter block */
435 val = I2S_READ(sc, DA_CTL);
436 I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN);
437
438 /* Enable TX DRQ */
439 val = I2S_READ(sc, DA_INT);
440 I2S_WRITE(sc, DA_INT, val | DA_INT_TX_DRQ);
441
442 /* Start DMA transfer */
443 error = sunxi_i2s_transfer(ch);
444 if (error != 0) {
445 aprint_error_dev(sc->sc_dev,
446 "failed to start DMA transfer: %d\n", error);
447 return error;
448 }
449
450 return 0;
451 }
452
453 static int
sunxi_i2s_trigger_input(void * priv,void * start,void * end,int blksize,void (* intr)(void *),void * intrarg,const audio_params_t * params)454 sunxi_i2s_trigger_input(void *priv, void *start, void *end, int blksize,
455 void (*intr)(void *), void *intrarg, const audio_params_t *params)
456 {
457 struct sunxi_i2s_softc * const sc = priv;
458 struct sunxi_i2s_chan *ch = &sc->sc_rchan;
459 struct sunxi_i2s_dma *dma;
460 bus_addr_t pstart;
461 bus_size_t psize;
462 uint32_t val;
463 int error;
464
465 if (ch->ch_dma == NULL)
466 return EIO;
467
468 pstart = 0;
469 psize = (uintptr_t)end - (uintptr_t)start;
470
471 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list)
472 if (dma->dma_addr == start) {
473 pstart = dma->dma_map->dm_segs[0].ds_addr;
474 break;
475 }
476 if (pstart == 0) {
477 device_printf(sc->sc_dev, "bad addr %p\n", start);
478 return EINVAL;
479 }
480
481 ch->ch_intr = intr;
482 ch->ch_intrarg = intrarg;
483 ch->ch_start_phys = ch->ch_cur_phys = pstart;
484 ch->ch_end_phys = pstart + psize;
485 ch->ch_blksize = blksize;
486
487 /* Flush FIFO */
488 val = I2S_READ(sc, DA_FCTL);
489 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX);
490 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX);
491
492 /* Reset RX sample counter */
493 I2S_WRITE(sc, DA_RXCNT, 0);
494
495 /* Enable receiver block */
496 val = I2S_READ(sc, DA_CTL);
497 I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN);
498
499 /* Enable RX DRQ */
500 val = I2S_READ(sc, DA_INT);
501 I2S_WRITE(sc, DA_INT, val | DA_INT_RX_DRQ);
502
503 /* Start DMA transfer */
504 error = sunxi_i2s_transfer(ch);
505 if (error != 0) {
506 aprint_error_dev(sc->sc_dev,
507 "failed to start DMA transfer: %d\n", error);
508 return error;
509 }
510
511 return 0;
512 }
513
514 static int
sunxi_i2s_halt_output(void * priv)515 sunxi_i2s_halt_output(void *priv)
516 {
517 struct sunxi_i2s_softc * const sc = priv;
518 struct sunxi_i2s_chan *ch = &sc->sc_pchan;
519 uint32_t val;
520
521 if (ch->ch_dma == NULL)
522 return EIO;
523
524 /* Disable DMA channel */
525 fdtbus_dma_halt(ch->ch_dma);
526
527 /* Disable transmitter block */
528 val = I2S_READ(sc, DA_CTL);
529 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN);
530
531 /* Disable TX DRQ */
532 val = I2S_READ(sc, DA_INT);
533 I2S_WRITE(sc, DA_INT, val & ~DA_INT_TX_DRQ);
534
535 ch->ch_intr = NULL;
536 ch->ch_intrarg = NULL;
537
538 return 0;
539 }
540
541 static int
sunxi_i2s_halt_input(void * priv)542 sunxi_i2s_halt_input(void *priv)
543 {
544 struct sunxi_i2s_softc * const sc = priv;
545 struct sunxi_i2s_chan *ch = &sc->sc_rchan;
546 uint32_t val;
547
548 if (ch->ch_dma == NULL)
549 return EIO;
550
551 /* Disable DMA channel */
552 fdtbus_dma_halt(ch->ch_dma);
553
554 /* Disable receiver block */
555 val = I2S_READ(sc, DA_CTL);
556 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN);
557
558 /* Disable RX DRQ */
559 val = I2S_READ(sc, DA_INT);
560 I2S_WRITE(sc, DA_INT, val & ~DA_INT_RX_DRQ);
561
562 return 0;
563 }
564
565 static void
sunxi_i2s_get_locks(void * priv,kmutex_t ** intr,kmutex_t ** thread)566 sunxi_i2s_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread)
567 {
568 struct sunxi_i2s_softc * const sc = priv;
569
570 *intr = &sc->sc_intr_lock;
571 *thread = &sc->sc_lock;
572 }
573
574 static const struct audio_hw_if sunxi_i2s_hw_if = {
575 .query_format = sunxi_i2s_query_format,
576 .set_format = sunxi_i2s_set_format,
577 .allocm = sunxi_i2s_allocm,
578 .freem = sunxi_i2s_freem,
579 .get_props = sunxi_i2s_get_props,
580 .trigger_output = sunxi_i2s_trigger_output,
581 .trigger_input = sunxi_i2s_trigger_input,
582 .halt_output = sunxi_i2s_halt_output,
583 .halt_input = sunxi_i2s_halt_input,
584 .get_locks = sunxi_i2s_get_locks,
585 };
586
587 static void
sunxi_i2s_dmaintr(void * priv)588 sunxi_i2s_dmaintr(void *priv)
589 {
590 struct sunxi_i2s_chan * const ch = priv;
591 struct sunxi_i2s_softc * const sc = ch->ch_sc;
592
593 mutex_enter(&sc->sc_intr_lock);
594 ch->ch_cur_phys += ch->ch_blksize;
595 if (ch->ch_cur_phys >= ch->ch_end_phys)
596 ch->ch_cur_phys = ch->ch_start_phys;
597
598 if (ch->ch_intr) {
599 ch->ch_intr(ch->ch_intrarg);
600 sunxi_i2s_transfer(ch);
601 }
602 mutex_exit(&sc->sc_intr_lock);
603 }
604
605 static int
sunxi_i2s_chan_init(struct sunxi_i2s_softc * sc,struct sunxi_i2s_chan * ch,u_int mode,const char * dmaname)606 sunxi_i2s_chan_init(struct sunxi_i2s_softc *sc,
607 struct sunxi_i2s_chan *ch, u_int mode, const char *dmaname)
608 {
609 ch->ch_sc = sc;
610 ch->ch_mode = mode;
611 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_i2s_dmaintr, ch);
612 if (ch->ch_dma == NULL)
613 return ENXIO;
614
615 if (mode == AUMODE_PLAY) {
616 ch->ch_req.dreq_dir = FDT_DMA_WRITE;
617 ch->ch_req.dreq_dev_phys =
618 sc->sc_baseaddr + DA_TXFIFO;
619 } else {
620 ch->ch_req.dreq_dir = FDT_DMA_READ;
621 ch->ch_req.dreq_dev_phys =
622 sc->sc_baseaddr + DA_RXFIFO;
623 }
624 ch->ch_req.dreq_mem_opt.opt_bus_width = 16;
625 ch->ch_req.dreq_mem_opt.opt_burst_len = 8;
626 ch->ch_req.dreq_dev_opt.opt_bus_width = 16;
627 ch->ch_req.dreq_dev_opt.opt_burst_len = 8;
628
629 return 0;
630 }
631
632 static int
sunxi_i2s_dai_set_sysclk(audio_dai_tag_t dai,u_int rate,int dir)633 sunxi_i2s_dai_set_sysclk(audio_dai_tag_t dai, u_int rate, int dir)
634 {
635 struct sunxi_i2s_softc * const sc = audio_dai_private(dai);
636 int bclk_val, mclk_val;
637 uint32_t val;
638 int error;
639
640 error = clk_set_rate(sc->sc_clk, SUNXI_I2S_CLK_RATE);
641 if (error != 0) {
642 aprint_error_dev(sc->sc_dev,
643 "couldn't set mod clock rate to %u Hz: %d\n", SUNXI_I2S_CLK_RATE, error);
644 return error;
645 }
646 error = clk_enable(sc->sc_clk);
647 if (error != 0) {
648 aprint_error_dev(sc->sc_dev,
649 "couldn't enable mod clock: %d\n", error);
650 return error;
651 }
652
653 const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : SUNXI_I2S_CLK_RATE;
654
655 const u_int bclk_div = bclk_prate / (2 * 32 * SUNXI_I2S_SAMPLE_RATE);
656 const u_int mclk_div = SUNXI_I2S_CLK_RATE / rate;
657
658 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
659 bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap,
660 __arraycount(sun4i_i2s_bclk_divmap), bclk_div);
661 mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap,
662 __arraycount(sun4i_i2s_mclk_divmap), mclk_div);
663 } else {
664 bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap,
665 __arraycount(sun8i_i2s_divmap), bclk_div);
666 mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap,
667 __arraycount(sun8i_i2s_divmap), mclk_div);
668 }
669 if (bclk_val == -1 || mclk_val == -1) {
670 aprint_error_dev(sc->sc_dev, "couldn't configure bclk/mclk dividers\n");
671 return EIO;
672 }
673
674 val = I2S_READ(sc, DA_CLKD);
675 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
676 val |= DA_CLKD_MCLKO_EN_SUN4I;
677 val &= ~DA_CLKD_BCLKDIV_SUN4I;
678 val |= __SHIFTIN(bclk_val, DA_CLKD_BCLKDIV_SUN4I);
679 } else {
680 val |= DA_CLKD_MCLKO_EN_SUN8I;
681 val &= ~DA_CLKD_BCLKDIV_SUN8I;
682 val |= __SHIFTIN(bclk_val, DA_CLKD_BCLKDIV_SUN8I);
683 }
684 val &= ~DA_CLKD_MCLKDIV;
685 val |= __SHIFTIN(mclk_val, DA_CLKD_MCLKDIV);
686 I2S_WRITE(sc, DA_CLKD, val);
687
688 return 0;
689 }
690
691 static int
sunxi_i2s_dai_set_format(audio_dai_tag_t dai,u_int format)692 sunxi_i2s_dai_set_format(audio_dai_tag_t dai, u_int format)
693 {
694 struct sunxi_i2s_softc * const sc = audio_dai_private(dai);
695 uint32_t ctl, fat0, chsel;
696 u_int offset;
697
698 const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);
699 const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);
700 const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);
701
702 ctl = I2S_READ(sc, DA_CTL);
703 fat0 = I2S_READ(sc, DA_FAT0);
704
705 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
706 fat0 &= ~DA_FAT0_FMT;
707 switch (fmt) {
708 case AUDIO_DAI_FORMAT_I2S:
709 fat0 |= __SHIFTIN(DA_FMT_I2S, DA_FAT0_FMT);
710 break;
711 case AUDIO_DAI_FORMAT_RJ:
712 fat0 |= __SHIFTIN(DA_FMT_RJ, DA_FAT0_FMT);
713 break;
714 case AUDIO_DAI_FORMAT_LJ:
715 fat0 |= __SHIFTIN(DA_FMT_LJ, DA_FAT0_FMT);
716 break;
717 default:
718 return EINVAL;
719 }
720 ctl &= ~DA_CTL_PCM;
721 } else {
722 ctl &= ~DA_CTL_MODE_SEL;
723 switch (fmt) {
724 case AUDIO_DAI_FORMAT_I2S:
725 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL);
726 offset = 1;
727 break;
728 case AUDIO_DAI_FORMAT_LJ:
729 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL);
730 offset = 0;
731 break;
732 case AUDIO_DAI_FORMAT_RJ:
733 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_RJ, DA_CTL_MODE_SEL);
734 offset = 0;
735 break;
736 case AUDIO_DAI_FORMAT_DSPA:
737 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL);
738 offset = 1;
739 break;
740 case AUDIO_DAI_FORMAT_DSPB:
741 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL);
742 offset = 0;
743 break;
744 default:
745 return EINVAL;
746 }
747
748 chsel = I2S_READ(sc, sc->sc_cfg->txchsel);
749 chsel &= ~DA_CHSEL_OFFSET;
750 chsel |= __SHIFTIN(offset, DA_CHSEL_OFFSET);
751 I2S_WRITE(sc, sc->sc_cfg->txchsel, chsel);
752
753 chsel = I2S_READ(sc, sc->sc_cfg->rxchsel);
754 chsel &= ~DA_CHSEL_OFFSET;
755 chsel |= __SHIFTIN(offset, DA_CHSEL_OFFSET);
756 I2S_WRITE(sc, sc->sc_cfg->rxchsel, chsel);
757 }
758
759 fat0 &= ~(DA_FAT0_LRCP|DA_FAT0_BCP);
760 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
761 if (AUDIO_DAI_POLARITY_B(pol))
762 fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP);
763 if (AUDIO_DAI_POLARITY_F(pol))
764 fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP);
765 } else {
766 if (AUDIO_DAI_POLARITY_B(pol))
767 fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP);
768 if (!AUDIO_DAI_POLARITY_F(pol))
769 fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP);
770
771 fat0 &= ~DA_FAT0_LRCK_PERIOD;
772 fat0 |= __SHIFTIN(32 - 1, DA_FAT0_LRCK_PERIOD);
773 }
774
775 switch (clk) {
776 case AUDIO_DAI_CLOCK_CBM_CFM:
777 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
778 ctl |= DA_CTL_MS; /* codec is master */
779 } else {
780 ctl &= ~DA_CTL_BCLK_OUT;
781 ctl &= ~DA_CLK_LRCK_OUT;
782 }
783 break;
784 case AUDIO_DAI_CLOCK_CBS_CFS:
785 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
786 ctl &= ~DA_CTL_MS; /* codec is slave */
787 } else {
788 ctl |= DA_CTL_BCLK_OUT;
789 ctl |= DA_CLK_LRCK_OUT;
790 }
791 break;
792 default:
793 return EINVAL;
794 }
795
796 I2S_WRITE(sc, DA_CTL, ctl);
797 I2S_WRITE(sc, DA_FAT0, fat0);
798
799 return 0;
800 }
801
802 static audio_dai_tag_t
sunxi_i2s_dai_get_tag(device_t dev,const void * data,size_t len)803 sunxi_i2s_dai_get_tag(device_t dev, const void *data, size_t len)
804 {
805 struct sunxi_i2s_softc * const sc = device_private(dev);
806
807 if (len != 4)
808 return NULL;
809
810 return &sc->sc_dai;
811 }
812
813 static struct fdtbus_dai_controller_func sunxi_i2s_dai_funcs = {
814 .get_tag = sunxi_i2s_dai_get_tag
815 };
816
817 static int
sunxi_i2s_clock_init(struct sunxi_i2s_softc * sc)818 sunxi_i2s_clock_init(struct sunxi_i2s_softc *sc)
819 {
820 const int phandle = sc->sc_phandle;
821 struct fdtbus_reset *rst;
822 struct clk *clk;
823 int error;
824
825 sc->sc_clk = fdtbus_clock_get(phandle, "mod");
826 if (sc->sc_clk == NULL) {
827 aprint_error(": couldn't find mod clock\n");
828 return ENXIO;
829 }
830
831 /* Enable APB clock */
832 clk = fdtbus_clock_get(phandle, "apb");
833 if (clk == NULL) {
834 aprint_error(": couldn't find apb clock\n");
835 return ENXIO;
836 }
837 error = clk_enable(clk);
838 if (error != 0) {
839 aprint_error(": couldn't enable apb clock: %d\n", error);
840 return error;
841 }
842
843 /* De-assert reset */
844 rst = fdtbus_reset_get_index(phandle, 0);
845 if (rst == NULL) {
846 aprint_error(": couldn't find reset\n");
847 return ENXIO;
848 }
849 error = fdtbus_reset_deassert(rst);
850 if (error != 0) {
851 aprint_error(": couldn't de-assert reset: %d\n", error);
852 return error;
853 }
854
855 return 0;
856 }
857
858 static int
sunxi_i2s_match(device_t parent,cfdata_t cf,void * aux)859 sunxi_i2s_match(device_t parent, cfdata_t cf, void *aux)
860 {
861 struct fdt_attach_args * const faa = aux;
862
863 return of_compatible_match(faa->faa_phandle, compat_data);
864 }
865
866 static void
sunxi_i2s_attach(device_t parent,device_t self,void * aux)867 sunxi_i2s_attach(device_t parent, device_t self, void *aux)
868 {
869 struct sunxi_i2s_softc * const sc = device_private(self);
870 struct fdt_attach_args * const faa = aux;
871 const int phandle = faa->faa_phandle;
872 bus_addr_t addr;
873 bus_size_t size;
874 uint32_t val;
875
876 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
877 aprint_error(": couldn't get registers\n");
878 return;
879 }
880
881 sc->sc_dev = self;
882 sc->sc_phandle = phandle;
883 sc->sc_baseaddr = addr;
884 sc->sc_bst = faa->faa_bst;
885 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
886 aprint_error(": couldn't map registers\n");
887 return;
888 }
889 sc->sc_dmat = faa->faa_dmat;
890 LIST_INIT(&sc->sc_dmalist);
891 sc->sc_cfg = of_compatible_lookup(phandle, compat_data)->data;
892 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
893 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
894
895 if (sunxi_i2s_clock_init(sc) != 0)
896 return;
897
898 /* At least one of these needs to succeed */
899 sunxi_i2s_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx");
900 sunxi_i2s_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx");
901 if (sc->sc_pchan.ch_dma == NULL && sc->sc_rchan.ch_dma == NULL) {
902 aprint_error(": couldn't setup channels\n");
903 return;
904 }
905
906 aprint_naive("\n");
907 aprint_normal(": %s\n", sc->sc_cfg->name);
908
909 /* Reset */
910 val = I2S_READ(sc, DA_CTL);
911 val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN);
912 I2S_WRITE(sc, DA_CTL, val);
913
914 val = I2S_READ(sc, DA_FCTL);
915 val &= ~(DA_FCTL_FTX|DA_FCTL_FRX);
916 I2S_WRITE(sc, DA_FCTL, val);
917
918 I2S_WRITE(sc, DA_TXCNT, 0);
919 I2S_WRITE(sc, DA_RXCNT, 0);
920
921 /* Enable */
922 val = I2S_READ(sc, DA_CTL);
923 val |= DA_CTL_GEN;
924 I2S_WRITE(sc, DA_CTL, val);
925 val |= DA_CTL_SDO_EN;
926 I2S_WRITE(sc, DA_CTL, val);
927
928 /* Setup channels */
929 I2S_WRITE(sc, sc->sc_cfg->txchmap, 0x76543210);
930 val = I2S_READ(sc, sc->sc_cfg->txchsel);
931 val &= ~DA_CHSEL_EN;
932 val |= __SHIFTIN(3, DA_CHSEL_EN);
933 val &= ~DA_CHSEL_SEL;
934 val |= __SHIFTIN(1, DA_CHSEL_SEL);
935 I2S_WRITE(sc, sc->sc_cfg->txchsel, val);
936 I2S_WRITE(sc, sc->sc_cfg->rxchmap, 0x76543210);
937 val = I2S_READ(sc, sc->sc_cfg->rxchsel);
938 val &= ~DA_CHSEL_EN;
939 val |= __SHIFTIN(3, DA_CHSEL_EN);
940 val &= ~DA_CHSEL_SEL;
941 val |= __SHIFTIN(1, DA_CHSEL_SEL);
942 I2S_WRITE(sc, sc->sc_cfg->rxchsel, val);
943
944 if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) {
945 val = I2S_READ(sc, DA_CHCFG);
946 val &= ~DA_CHCFG_TX_SLOT_NUM;
947 val |= __SHIFTIN(1, DA_CHCFG_TX_SLOT_NUM);
948 val &= ~DA_CHCFG_RX_SLOT_NUM;
949 val |= __SHIFTIN(1, DA_CHCFG_RX_SLOT_NUM);
950 I2S_WRITE(sc, DA_CHCFG, val);
951 }
952
953 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD;
954 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE;
955 sc->sc_format.validbits = 16;
956 sc->sc_format.precision = 16;
957 sc->sc_format.channels = 2;
958 sc->sc_format.channel_mask = AUFMT_STEREO;
959 sc->sc_format.frequency_type = 1;
960 sc->sc_format.frequency[0] = SUNXI_I2S_SAMPLE_RATE;
961
962 sc->sc_dai.dai_set_sysclk = sunxi_i2s_dai_set_sysclk;
963 sc->sc_dai.dai_set_format = sunxi_i2s_dai_set_format;
964 sc->sc_dai.dai_hw_if = &sunxi_i2s_hw_if;
965 sc->sc_dai.dai_dev = self;
966 sc->sc_dai.dai_priv = sc;
967 fdtbus_register_dai_controller(self, phandle, &sunxi_i2s_dai_funcs);
968 }
969
970 CFATTACH_DECL_NEW(sunxi_i2s, sizeof(struct sunxi_i2s_softc),
971 sunxi_i2s_match, sunxi_i2s_attach, NULL, NULL);
972