1 /* $NetBSD: sunxi_hdmi.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_ddb.h"
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: sunxi_hdmi.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $");
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/intr.h>
38 #include <sys/kmem.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/proc.h>
42 #include <sys/mutex.h>
43 #include <sys/kthread.h>
44
45 #include <dev/fdt/fdtvar.h>
46 #include <dev/fdt/fdt_port.h>
47
48 #include <dev/i2c/i2cvar.h>
49 #include <dev/i2c/ddcvar.h>
50 #include <dev/i2c/ddcreg.h>
51 #include <dev/videomode/videomode.h>
52 #include <dev/videomode/edidvar.h>
53
54 #include <arm/sunxi/sunxi_hdmireg.h>
55 #include <arm/sunxi/sunxi_display.h>
56
57 enum sunxi_hdmi_type {
58 HDMI_A10 = 1,
59 HDMI_A31,
60 };
61
62 struct sunxi_hdmi_softc {
63 device_t sc_dev;
64 int sc_phandle;
65 enum sunxi_hdmi_type sc_type;
66 bus_space_tag_t sc_bst;
67 bus_space_handle_t sc_bsh;
68 struct clk *sc_clk_ahb;
69 struct clk *sc_clk_mod;
70 struct clk *sc_clk_pll0;
71 struct clk *sc_clk_pll1;
72 void *sc_ih;
73 lwp_t *sc_thread;
74
75 struct i2c_controller sc_ic;
76 kmutex_t sc_exec_lock;
77
78 bool sc_display_connected;
79 char sc_display_vendor[16];
80 char sc_display_product[16];
81
82 u_int sc_display_mode;
83 u_int sc_current_display_mode;
84 #define DISPLAY_MODE_AUTO 0
85 #define DISPLAY_MODE_HDMI 1
86 #define DISPLAY_MODE_DVI 2
87
88 kmutex_t sc_pwr_lock;
89 int sc_pwr_refcount; /* reference who needs HDMI */
90
91 uint32_t sc_ver;
92 unsigned int sc_i2c_blklen;
93
94 struct fdt_device_ports sc_ports;
95 struct fdt_endpoint *sc_in_ep;
96 struct fdt_endpoint *sc_in_rep;
97 struct fdt_endpoint *sc_out_ep;
98 };
99
100 #define HDMI_READ(sc, reg) \
101 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
102 #define HDMI_WRITE(sc, reg, val) \
103 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val));
104
105 #define HDMI_1_3_P(sc) ((sc)->sc_ver == 0x00010003)
106 #define HDMI_1_4_P(sc) ((sc)->sc_ver == 0x00010004)
107
108 static const struct device_compatible_entry compat_data[] = {
109 { .compat = "allwinner,sun4i-a10-hdmi", .value = HDMI_A10},
110 { .compat = "allwinner,sun7i-a20-hdmi", .value = HDMI_A10},
111 DEVICE_COMPAT_EOL
112 };
113
114 static int sunxi_hdmi_match(device_t, cfdata_t, void *);
115 static void sunxi_hdmi_attach(device_t, device_t, void *);
116 static void sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *);
117 static int sunxi_hdmi_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
118 size_t, void *, size_t, int);
119 static int sunxi_hdmi_i2c_xfer(void *, i2c_addr_t, uint8_t, uint8_t,
120 size_t, int, int);
121 static int sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *, int);
122
123 static int sunxi_hdmi_ep_activate(device_t, struct fdt_endpoint *, bool);
124 static int sunxi_hdmi_ep_enable(device_t, struct fdt_endpoint *, bool);
125 static void sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *);
126 static void sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *);
127 static int sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *, uint8_t *,
128 uint8_t);
129 static u_int sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *,
130 const struct edid_info *);
131 static void sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *, bool);
132 static void sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *,
133 const struct videomode *, u_int);
134 static void sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *,
135 const struct videomode *, u_int);
136 static void sunxi_hdmi_hpd(struct sunxi_hdmi_softc *);
137 static void sunxi_hdmi_thread(void *);
138 static int sunxi_hdmi_poweron(struct sunxi_hdmi_softc *, bool);
139 #if 0
140 static int sunxi_hdmi_intr(void *);
141 #endif
142
143 #if defined(DDB)
144 void sunxi_hdmi_dump_regs(void);
145 #endif
146
147 CFATTACH_DECL_NEW(sunxi_hdmi, sizeof(struct sunxi_hdmi_softc),
148 sunxi_hdmi_match, sunxi_hdmi_attach, NULL, NULL);
149
150 static int
sunxi_hdmi_match(device_t parent,cfdata_t cf,void * aux)151 sunxi_hdmi_match(device_t parent, cfdata_t cf, void *aux)
152 {
153 struct fdt_attach_args * const faa = aux;
154
155 return of_compatible_match(faa->faa_phandle, compat_data);
156 }
157
158 static void
sunxi_hdmi_attach(device_t parent,device_t self,void * aux)159 sunxi_hdmi_attach(device_t parent, device_t self, void *aux)
160 {
161 struct sunxi_hdmi_softc *sc = device_private(self);
162 struct fdt_attach_args * const faa = aux;
163 const int phandle = faa->faa_phandle;
164 bus_addr_t addr;
165 bus_size_t size;
166 uint32_t ver;
167
168 sc->sc_dev = self;
169 sc->sc_phandle = phandle;
170 sc->sc_bst = faa->faa_bst;
171
172 sc->sc_type =
173 of_compatible_lookup(faa->faa_phandle, compat_data)->value;
174
175 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
176 aprint_error(": couldn't get registers\n");
177 }
178 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
179 aprint_error(": couldn't map registers\n");
180 return;
181 }
182
183 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb");
184 sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod");
185 sc->sc_clk_pll0 = fdtbus_clock_get(phandle, "pll-0");
186 sc->sc_clk_pll1 = fdtbus_clock_get(phandle, "pll-1");
187
188 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mod == NULL
189 || sc->sc_clk_pll0 == NULL || sc->sc_clk_pll1 == NULL) {
190 aprint_error(": couldn't get clocks\n");
191 aprint_debug_dev(self, "clk ahb %s mod %s pll-0 %s pll-1 %s\n",
192 sc->sc_clk_ahb == NULL ? "missing" : "present",
193 sc->sc_clk_mod == NULL ? "missing" : "present",
194 sc->sc_clk_pll0 == NULL ? "missing" : "present",
195 sc->sc_clk_pll1 == NULL ? "missing" : "present");
196 return;
197 }
198
199 if (clk_enable(sc->sc_clk_ahb) != 0) {
200 aprint_error(": couldn't enable ahb clock\n");
201 return;
202 }
203 ver = HDMI_READ(sc, SUNXI_HDMI_VERSION_ID_REG);
204
205 const int vmaj = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_H);
206 const int vmin = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_L);
207
208 aprint_naive("\n");
209 aprint_normal(": HDMI %d.%d\n", vmaj, vmin);
210
211 sc->sc_ver = ver;
212 sc->sc_i2c_blklen = 16;
213
214 sc->sc_ports.dp_ep_activate = sunxi_hdmi_ep_activate;
215 sc->sc_ports.dp_ep_enable = sunxi_hdmi_ep_enable;
216 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER);
217
218 mutex_init(&sc->sc_pwr_lock, MUTEX_DEFAULT, IPL_NONE);
219 sunxi_hdmi_i2c_init(sc);
220 }
221
222 void
sunxi_hdmi_doreset(void)223 sunxi_hdmi_doreset(void)
224 {
225 device_t dev;
226 struct sunxi_hdmi_softc *sc;
227 int error;
228
229 for (int i = 0;;i++) {
230 dev = device_find_by_driver_unit("sunxihdmi", i);
231 if (dev == NULL)
232 return;
233 sc = device_private(dev);
234
235 error = clk_disable(sc->sc_clk_mod);
236 if (error) {
237 aprint_error_dev(dev, ": couldn't disable mod clock\n");
238 return;
239 }
240
241 #if defined(SUNXI_HDMI_DEBUG)
242 sunxi_hdmi_dump_regs();
243 #endif
244
245 /*
246 * reset device, in case it has been setup by firmware in an
247 * incompatible way
248 */
249 for (int j = 0; j <= 0x500; j += 4) {
250 HDMI_WRITE(sc, j, 0);
251 }
252
253 if (clk_disable(sc->sc_clk_ahb) != 0) {
254 aprint_error_dev(dev, ": couldn't disable ahb clock\n");
255 return;
256 }
257 }
258 }
259
260 static void
sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc * sc)261 sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *sc)
262 {
263 struct i2c_controller *ic = &sc->sc_ic;
264
265 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_NONE);
266
267 iic_tag_init(ic);
268 ic->ic_cookie = sc;
269 ic->ic_exec = sunxi_hdmi_i2c_exec;
270 }
271
272 static int
sunxi_hdmi_i2c_exec(void * priv,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)273 sunxi_hdmi_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr,
274 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
275 {
276 struct sunxi_hdmi_softc *sc = priv;
277 uint8_t *pbuf;
278 uint8_t block;
279 int resid;
280 off_t off;
281 int err;
282
283 mutex_enter(&sc->sc_exec_lock);
284
285 KASSERT(op == I2C_OP_READ_WITH_STOP);
286 KASSERT(addr == DDC_ADDR);
287 KASSERT(cmdlen > 0);
288 KASSERT(buf != NULL);
289
290 err = sunxi_hdmi_i2c_reset(sc, flags);
291 if (err)
292 goto done;
293
294 block = *(const uint8_t *)cmdbuf;
295 off = (block & 1) ? 128 : 0;
296
297 pbuf = buf;
298 resid = len;
299 while (resid > 0) {
300 size_t blklen = uimin(resid, sc->sc_i2c_blklen);
301
302 err = sunxi_hdmi_i2c_xfer(sc, addr, block >> 1, off, blklen,
303 SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_EOREAD, flags);
304 if (err)
305 goto done;
306
307 if (HDMI_1_3_P(sc)) {
308 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh,
309 SUNXI_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen);
310 } else {
311 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh,
312 SUNXI_A31_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen);
313 }
314
315 #ifdef SUNXI_HDMI_DEBUG
316 printf("off=%d:", (int)off);
317 for (int i = 0; i < blklen; i++)
318 printf(" %02x", pbuf[i]);
319 printf("\n");
320 #endif
321
322 pbuf += blklen;
323 off += blklen;
324 resid -= blklen;
325 }
326
327 done:
328 mutex_exit(&sc->sc_exec_lock);
329 return err;
330 }
331
332 static int
sunxi_hdmi_i2c_xfer_1_3(void * priv,i2c_addr_t addr,uint8_t block,uint8_t reg,size_t len,int type,int flags)333 sunxi_hdmi_i2c_xfer_1_3(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg,
334 size_t len, int type, int flags)
335 {
336 struct sunxi_hdmi_softc *sc = priv;
337 uint32_t val;
338 int retry;
339
340 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG);
341 val &= ~SUNXI_HDMI_DDC_CTRL_FIFO_DIR;
342 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);
343
344 val |= __SHIFTIN(block, SUNXI_HDMI_DDC_SLAVE_ADDR_0);
345 val |= __SHIFTIN(0x60, SUNXI_HDMI_DDC_SLAVE_ADDR_1);
346 val |= __SHIFTIN(reg, SUNXI_HDMI_DDC_SLAVE_ADDR_2);
347 val |= __SHIFTIN(addr, SUNXI_HDMI_DDC_SLAVE_ADDR_3);
348 HDMI_WRITE(sc, SUNXI_HDMI_DDC_SLAVE_ADDR_REG, val);
349
350 val = HDMI_READ(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG);
351 val |= SUNXI_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR;
352 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, val);
353
354 HDMI_WRITE(sc, SUNXI_HDMI_DDC_BYTE_COUNTER_REG, len);
355
356 HDMI_WRITE(sc, SUNXI_HDMI_DDC_COMMAND_REG, type);
357
358 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG);
359 val |= SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START;
360 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);
361
362 retry = 1000;
363 while (--retry > 0) {
364 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG);
365 if ((val & SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0)
366 break;
367 delay(1000);
368 }
369 if (retry == 0)
370 return ETIMEDOUT;
371
372 val = HDMI_READ(sc, SUNXI_HDMI_DDC_INT_STATUS_REG);
373 if ((val & SUNXI_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE) == 0) {
374 device_printf(sc->sc_dev, "xfer failed, status=%08x\n", val);
375 return EIO;
376 }
377
378 return 0;
379 }
380
381 static int
sunxi_hdmi_i2c_xfer_1_4(void * priv,i2c_addr_t addr,uint8_t block,uint8_t reg,size_t len,int type,int flags)382 sunxi_hdmi_i2c_xfer_1_4(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg,
383 size_t len, int type, int flags)
384 {
385 struct sunxi_hdmi_softc *sc = priv;
386 uint32_t val;
387 int retry;
388
389 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG);
390 val |= SUNXI_A31_HDMI_DDC_FIFO_CTRL_RST;
391 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG, val);
392
393 val = __SHIFTIN(block, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_SEG_PTR);
394 val |= __SHIFTIN(0x60, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DDC_CMD);
395 val |= __SHIFTIN(reg, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR);
396 val |= __SHIFTIN(addr, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DEV_ADR);
397 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG, val);
398
399 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_COMMAND_REG,
400 __SHIFTIN(len, SUNXI_A31_HDMI_DDC_COMMAND_DTC) |
401 __SHIFTIN(type, SUNXI_A31_HDMI_DDC_COMMAND_CMD));
402
403 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG);
404 val |= SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START;
405 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, val);
406
407 retry = 1000;
408 while (--retry > 0) {
409 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG);
410 if ((val & SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0)
411 break;
412 if (flags & I2C_F_POLL)
413 delay(1000);
414 else
415 kpause("hdmiddc", false, mstohz(10), &sc->sc_exec_lock);
416 }
417 if (retry == 0)
418 return ETIMEDOUT;
419
420 return 0;
421 }
422
423 static int
sunxi_hdmi_i2c_xfer(void * priv,i2c_addr_t addr,uint8_t block,uint8_t reg,size_t len,int type,int flags)424 sunxi_hdmi_i2c_xfer(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg,
425 size_t len, int type, int flags)
426 {
427 struct sunxi_hdmi_softc *sc = priv;
428 int rv;
429
430 if (HDMI_1_3_P(sc)) {
431 rv = sunxi_hdmi_i2c_xfer_1_3(priv, addr, block, reg, len,
432 type, flags);
433 } else {
434 rv = sunxi_hdmi_i2c_xfer_1_4(priv, addr, block, reg, len,
435 type, flags);
436 }
437
438 return rv;
439 }
440
441 static int
sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc * sc,int flags)442 sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *sc, int flags)
443 {
444 uint32_t hpd, ctrl;
445
446 hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG);
447 if ((hpd & SUNXI_HDMI_HPD_HOTPLUG_DET) == 0) {
448 device_printf(sc->sc_dev, "no device detected\n");
449 return ENODEV; /* no device plugged in */
450 }
451
452 if (HDMI_1_3_P(sc)) {
453 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, 0);
454 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG,
455 SUNXI_HDMI_DDC_CTRL_EN | SUNXI_HDMI_DDC_CTRL_SW_RST);
456
457 delay(1000);
458
459 ctrl = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG);
460 if (ctrl & SUNXI_HDMI_DDC_CTRL_SW_RST) {
461 device_printf(sc->sc_dev, "reset failed (1.3)\n");
462 return EBUSY;
463 }
464
465 /* N=5,M=1 */
466 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CLOCK_REG,
467 __SHIFTIN(5, SUNXI_HDMI_DDC_CLOCK_N) |
468 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_M));
469
470 HDMI_WRITE(sc, SUNXI_HDMI_DDC_DBG_REG, 0x300);
471 } else {
472 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG,
473 SUNXI_A31_HDMI_DDC_CTRL_SW_RST);
474
475 /* N=1,M=12 */
476 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CLOCK_REG,
477 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_N) |
478 __SHIFTIN(12, SUNXI_HDMI_DDC_CLOCK_M));
479
480 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG,
481 SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_EN |
482 SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_EN |
483 SUNXI_A31_HDMI_DDC_CTRL_EN);
484 }
485
486 return 0;
487 }
488
489 static int
sunxi_hdmi_ep_activate(device_t dev,struct fdt_endpoint * ep,bool activate)490 sunxi_hdmi_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate)
491 {
492 struct sunxi_hdmi_softc *sc = device_private(dev);
493 struct fdt_endpoint *in_ep, *out_ep;
494 int error;
495
496 /* our input is activated by tcon, we activate our output */
497 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) {
498 panic("sunxi_hdmi_ep_activate: port %d",
499 fdt_endpoint_port_index(ep));
500 }
501
502 if (!activate)
503 return EOPNOTSUPP;
504
505 /* check that out other input is not active */
506 switch (fdt_endpoint_index(ep)) {
507 case 0:
508 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports,
509 SUNXI_PORT_INPUT, 1);
510 break;
511 case 1:
512 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports,
513 SUNXI_PORT_INPUT, 0);
514 break;
515 default:
516 in_ep = NULL;
517 panic("sunxi_hdmi_ep_activate: input index %d",
518 fdt_endpoint_index(ep));
519 }
520 if (in_ep != NULL) {
521 if (fdt_endpoint_is_active(in_ep))
522 return EBUSY;
523 }
524 /* only one output */
525 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports,
526 SUNXI_PORT_OUTPUT, 0);
527 if (out_ep == NULL) {
528 aprint_error_dev(dev, "no output endpoint\n");
529 return ENODEV;
530 }
531 error = fdt_endpoint_activate(out_ep, activate);
532 if (error == 0) {
533 sc->sc_in_ep = ep;
534 sc->sc_in_rep = fdt_endpoint_remote(ep);
535 sc->sc_out_ep = out_ep;
536 sunxi_hdmi_do_enable(sc);
537 return 0;
538 }
539 return error;
540 }
541
542 static int
sunxi_hdmi_ep_enable(device_t dev,struct fdt_endpoint * ep,bool enable)543 sunxi_hdmi_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable)
544 {
545 struct sunxi_hdmi_softc *sc = device_private(dev);
546 int error;
547
548 if (fdt_endpoint_port_index(ep) == SUNXI_PORT_INPUT) {
549 KASSERT(ep == sc->sc_in_ep);
550 if (sc->sc_thread == NULL) {
551 if (enable) {
552 delay(50000);
553 mutex_enter(&sc->sc_pwr_lock);
554 sunxi_hdmi_hpd(sc);
555 mutex_exit(&sc->sc_pwr_lock);
556 kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL,
557 sunxi_hdmi_thread, sc, &sc->sc_thread, "%s",
558 device_xname(dev));
559 }
560 return 0;
561 } else {
562 mutex_enter(&sc->sc_pwr_lock);
563 error = sunxi_hdmi_poweron(sc, enable);
564 mutex_exit(&sc->sc_pwr_lock);
565 return error;
566 }
567 }
568 panic("sunxi_hdmi_ep_enable");
569 }
570
571 static void
sunxi_hdmi_do_enable(struct sunxi_hdmi_softc * sc)572 sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *sc)
573 {
574 /* complete attach */
575 struct clk *clk;
576 int error;
577 uint32_t dbg0_reg;
578
579 if (clk_enable(sc->sc_clk_ahb) != 0) {
580 aprint_error_dev(sc->sc_dev, "couldn't enable ahb clock\n");
581 return;
582 }
583 /* assume tcon0 uses pll3, tcon1 uses pll7 */
584 switch(fdt_endpoint_index(sc->sc_in_ep)) {
585 case 0:
586 clk = sc->sc_clk_pll0;
587 dbg0_reg = (0<<21);
588 break;
589 case 1:
590 clk = sc->sc_clk_pll1;
591 dbg0_reg = (1<<21);
592 break;
593 default:
594 panic("sunxi_hdmi pll");
595 }
596 error = clk_set_rate(clk, 270000000);
597 if (error) {
598 clk = clk_get_parent(clk);
599 /* probably because this is pllx2 */
600 error = clk_set_rate(clk, 270000000);
601 }
602 if (error) {
603 aprint_error_dev(sc->sc_dev, ": couldn't init pll clock\n");
604 return;
605 }
606 error = clk_set_parent(sc->sc_clk_mod, clk);
607 if (error) {
608 aprint_error_dev(sc->sc_dev, ": couldn't set mod clock parent\n");
609 return;
610 }
611 error = clk_enable(sc->sc_clk_mod);
612 if (error) {
613 aprint_error_dev(sc->sc_dev, ": couldn't enable mod clock\n");
614 return;
615 }
616 delay(1000);
617
618 HDMI_WRITE(sc, SUNXI_HDMI_CTRL_REG, SUNXI_HDMI_CTRL_MODULE_EN);
619 delay(1000);
620 if (sc->sc_type == HDMI_A10) {
621 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0xfe800000);
622 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x00d8c830);
623 } else if (sc->sc_type == HDMI_A31) {
624 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0x7e80000f);
625 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x01ded030);
626 }
627 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, dbg0_reg);
628 delay(1000);
629 }
630
631 #define EDID_BLOCK_SIZE 128
632
633 static int
sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc * sc,uint8_t * data,uint8_t block)634 sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *sc, uint8_t *data,
635 uint8_t block)
636 {
637 i2c_tag_t tag = &sc->sc_ic;
638 uint8_t wbuf[2];
639 int error;
640
641 if ((error = iic_acquire_bus(tag, 0)) != 0)
642 return error;
643
644 wbuf[0] = block; /* start address */
645
646 error = iic_exec(tag, I2C_OP_READ_WITH_STOP, DDC_ADDR, wbuf, 1,
647 data, EDID_BLOCK_SIZE, 0);
648 iic_release_bus(tag, 0);
649 return error;
650 }
651
652 static void
sunxi_hdmi_read_edid(struct sunxi_hdmi_softc * sc)653 sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *sc)
654 {
655 const struct videomode *mode;
656 char *edid;
657 struct edid_info *eip;
658 int retry = 4;
659 u_int display_mode;
660
661 edid = kmem_zalloc(EDID_BLOCK_SIZE, KM_SLEEP);
662 eip = kmem_zalloc(sizeof(struct edid_info), KM_SLEEP);
663
664 while (--retry > 0) {
665 if (!sunxi_hdmi_read_edid_block(sc, edid, 0))
666 break;
667 }
668 if (retry == 0) {
669 device_printf(sc->sc_dev, "failed to read EDID\n");
670 } else {
671 if (edid_parse(edid, eip) != 0) {
672 device_printf(sc->sc_dev, "failed to parse EDID\n");
673 }
674 #ifdef SUNXI_HDMI_DEBUG
675 else {
676 edid_print(eip);
677 }
678 #endif
679 }
680
681 if (sc->sc_display_mode == DISPLAY_MODE_AUTO)
682 display_mode = sunxi_hdmi_get_display_mode(sc, eip);
683 else
684 display_mode = sc->sc_display_mode;
685
686 const char *forced = sc->sc_display_mode == DISPLAY_MODE_AUTO ?
687 "auto-detected" : "forced";
688 device_printf(sc->sc_dev, "%s mode (%s)\n",
689 display_mode == DISPLAY_MODE_HDMI ? "HDMI" : "DVI", forced);
690
691 strlcpy(sc->sc_display_vendor, eip->edid_vendorname,
692 sizeof(sc->sc_display_vendor));
693 strlcpy(sc->sc_display_product, eip->edid_productname,
694 sizeof(sc->sc_display_product));
695 sc->sc_current_display_mode = display_mode;
696
697 mode = eip->edid_preferred_mode;
698 if (mode == NULL)
699 mode = pick_mode_by_ref(640, 480, 60);
700
701 if (mode != NULL) {
702 sunxi_hdmi_video_enable(sc, false);
703 fdt_endpoint_enable(sc->sc_in_ep, false);
704 delay(20000);
705
706 sunxi_tcon1_set_videomode(
707 fdt_endpoint_device(sc->sc_in_rep), mode);
708 sunxi_hdmi_set_videomode(sc, mode, display_mode);
709 sunxi_hdmi_set_audiomode(sc, mode, display_mode);
710 fdt_endpoint_enable(sc->sc_in_ep, true);
711 delay(20000);
712 sunxi_hdmi_video_enable(sc, true);
713 }
714 kmem_free(edid, EDID_BLOCK_SIZE);
715 kmem_free(eip, sizeof(struct edid_info));
716 }
717
718 static u_int
sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc * sc,const struct edid_info * ei)719 sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *sc,
720 const struct edid_info *ei)
721 {
722 char *edid;
723 bool found_hdmi = false;
724 unsigned int n, p;
725 edid = kmem_zalloc(EDID_BLOCK_SIZE, KM_SLEEP);
726
727 /*
728 * Scan through extension blocks, looking for a CEA-861-D v3
729 * block. If an HDMI Vendor-Specific Data Block (HDMI VSDB) is
730 * found in that, assume HDMI mode.
731 */
732 for (n = 1; n <= MIN(ei->edid_ext_block_count, 4); n++) {
733 if (sunxi_hdmi_read_edid_block(sc, edid, n)) {
734 #ifdef SUNXI_HDMI_DEBUG
735 device_printf(sc->sc_dev,
736 "Failed to read EDID block %d\n", n);
737 #endif
738 break;
739 }
740
741 #ifdef SUNXI_HDMI_DEBUG
742 device_printf(sc->sc_dev, "EDID block #%d:\n", n);
743 #endif
744
745 const uint8_t tag = edid[0];
746 const uint8_t rev = edid[1];
747 const uint8_t off = edid[2];
748
749 #ifdef SUNXI_HDMI_DEBUG
750 device_printf(sc->sc_dev, " Tag %d, Revision %d, Offset %d\n",
751 tag, rev, off);
752 device_printf(sc->sc_dev, " Flags: 0x%02x\n", edid[3]);
753 #endif
754
755 /* We are looking for a CEA-861-D tag (02h) with revision 3 */
756 if (tag != 0x02 || rev != 3)
757 continue;
758 /*
759 * CEA data block collection starts at byte 4, so the
760 * DTD blocks must start after it.
761 */
762 if (off <= 4)
763 continue;
764
765 /* Parse the CEA data blocks */
766 for (p = 4; p < off;) {
767 const uint8_t btag = (edid[p] >> 5) & 0x7;
768 const uint8_t blen = edid[p] & 0x1f;
769
770 #ifdef SUNXI_HDMI_DEBUG
771 device_printf(sc->sc_dev, " CEA data block @ %d\n", p);
772 device_printf(sc->sc_dev, " Tag %d, Length %d\n",
773 btag, blen);
774 #endif
775
776 /* Make sure the length is sane */
777 if (p + blen + 1 > off)
778 break;
779 /* Looking for a VSDB tag */
780 if (btag != 3)
781 goto next_block;
782 /* HDMI VSDB is at least 5 bytes long */
783 if (blen < 5)
784 goto next_block;
785
786 #ifdef SUNXI_HDMI_DEBUG
787 device_printf(sc->sc_dev, " ID: %02x%02x%02x\n",
788 edid[p + 1], edid[p + 2], edid[p + 3]);
789 #endif
790
791 /* HDMI 24-bit IEEE registration ID is 0x000C03 */
792 if (memcmp(&edid[p + 1], "\x03\x0c\x00", 3) == 0)
793 found_hdmi = true;
794
795 next_block:
796 p += (1 + blen);
797 }
798 }
799
800 kmem_free(edid, EDID_BLOCK_SIZE);
801 return found_hdmi ? DISPLAY_MODE_HDMI : DISPLAY_MODE_DVI;
802 }
803
804 static void
sunxi_hdmi_video_enable(struct sunxi_hdmi_softc * sc,bool enable)805 sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *sc, bool enable)
806 {
807 uint32_t val;
808
809 fdt_endpoint_enable(sc->sc_out_ep, enable);
810
811 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG);
812 val &= ~SUNXI_HDMI_VID_CTRL_SRC_SEL;
813 #ifdef SUNXI_HDMI_CBGEN
814 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_CBGEN,
815 SUNXI_HDMI_VID_CTRL_SRC_SEL);
816 #else
817 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_RGB,
818 SUNXI_HDMI_VID_CTRL_SRC_SEL);
819 #endif
820 if (enable) {
821 val |= SUNXI_HDMI_VID_CTRL_VIDEO_EN;
822 } else {
823 val &= ~SUNXI_HDMI_VID_CTRL_VIDEO_EN;
824 }
825 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val);
826
827 #if defined(SUNXI_HDMI_DEBUG)
828 sunxi_hdmi_dump_regs();
829 #endif
830 }
831
832 static void
sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc * sc,const struct videomode * mode,u_int display_mode)833 sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *sc,
834 const struct videomode *mode, u_int display_mode)
835 {
836 uint32_t val;
837 const u_int dblscan_p = !!(mode->flags & VID_DBLSCAN);
838 const u_int interlace_p = !!(mode->flags & VID_INTERLACE);
839 const u_int phsync_p = !!(mode->flags & VID_PHSYNC);
840 const u_int pvsync_p = !!(mode->flags & VID_PVSYNC);
841 const u_int hfp = mode->hsync_start - mode->hdisplay;
842 const u_int hspw = mode->hsync_end - mode->hsync_start;
843 const u_int hbp = mode->htotal - mode->hsync_start;
844 const u_int vfp = mode->vsync_start - mode->vdisplay;
845 const u_int vspw = mode->vsync_end - mode->vsync_start;
846 const u_int vbp = mode->vtotal - mode->vsync_start;
847 struct clk *clk_pll;
848 int parent_rate;
849 int best_div, best_dbl, best_diff;
850 int target_rate = mode->dot_clock * 1000;
851
852 #ifdef SUNXI_HDMI_DEBUG
853 device_printf(sc->sc_dev,
854 "dblscan %d, interlace %d, phsync %d, pvsync %d\n",
855 dblscan_p, interlace_p, phsync_p, pvsync_p);
856 device_printf(sc->sc_dev, "h: %u %u %u %u\n",
857 mode->hdisplay, hbp, hfp, hspw);
858 device_printf(sc->sc_dev, "v: %u %u %u %u\n",
859 mode->vdisplay, vbp, vfp, vspw);
860 #endif
861
862 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, 0xffffffff);
863
864 /* assume tcon0 uses pll3, tcon1 uses pll7 */
865 switch(fdt_endpoint_index(sc->sc_in_ep)) {
866 case 0:
867 clk_pll = sc->sc_clk_pll0;
868 break;
869 case 1:
870 clk_pll = sc->sc_clk_pll1;
871 break;
872 default:
873 panic("sunxi_hdmi pll");
874 }
875 parent_rate = clk_get_rate(clk_pll);
876 KASSERT(parent_rate > 0);
877 best_div = best_dbl = 0;
878 best_diff = INT_MAX;
879 for (int d = 2; d > 0 && best_diff != 0; d--) {
880 for (int m = 1; m <= 16 && best_diff != 0; m++) {
881 int cur_rate = parent_rate / m / d;
882 int diff = abs(target_rate - cur_rate);
883 if (diff >= 0 && diff < best_diff) {
884 best_diff = diff;
885 best_div = m;
886 best_dbl = d;
887 }
888 }
889 }
890
891 #ifdef SUNXI_HDMI_DEBUG
892 device_printf(sc->sc_dev, "parent rate: %d\n", parent_rate);
893 device_printf(sc->sc_dev, "dot_clock: %d\n", mode->dot_clock);
894 device_printf(sc->sc_dev, "clkdiv: %d\n", best_div);
895 device_printf(sc->sc_dev, "clkdbl: %c\n", (best_dbl == 1) ? 'Y' : 'N');
896 #endif
897
898 if (best_div == 0) {
899 device_printf(sc->sc_dev, "ERROR: TCON clk not configured\n");
900 return;
901 }
902
903 uint32_t pll_ctrl, pad_ctrl0, pad_ctrl1;
904 if (HDMI_1_4_P(sc)) {
905 pad_ctrl0 = 0x7e8000ff;
906 pad_ctrl1 = 0x01ded030;
907 pll_ctrl = 0xba48a308;
908 pll_ctrl |= __SHIFTIN(best_div - 1, SUNXI_HDMI_PLL_CTRL_PREDIV);
909 } else {
910 pad_ctrl0 = 0xfe800000;
911 pad_ctrl1 = 0x00d8c830;
912 pll_ctrl = 0xfa4ef708;
913 pll_ctrl |= __SHIFTIN(best_div, SUNXI_HDMI_PLL_CTRL_PREDIV);
914 }
915 if (best_dbl == 2)
916 pad_ctrl1 |= 0x40;
917
918 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, pad_ctrl0);
919 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, pad_ctrl1);
920 HDMI_WRITE(sc, SUNXI_HDMI_PLL_CTRL_REG, pll_ctrl);
921 /* assume tcon0 uses pll3, tcon1 uses pll7 */
922 switch(fdt_endpoint_index(sc->sc_in_ep)) {
923 case 0:
924 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (0<<21));
925 break;
926 case 1:
927 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (1<<21));
928 break;
929 default:
930 panic("sunxi_hdmi pll");
931 }
932
933 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG);
934 val &= ~SUNXI_HDMI_VID_CTRL_HDMI_MODE;
935 if (display_mode == DISPLAY_MODE_DVI) {
936 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_DVI,
937 SUNXI_HDMI_VID_CTRL_HDMI_MODE);
938 } else {
939 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_HDMI,
940 SUNXI_HDMI_VID_CTRL_HDMI_MODE);
941 }
942 val &= ~SUNXI_HDMI_VID_CTRL_REPEATER_SEL;
943 if (dblscan_p) {
944 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_REPEATER_SEL_2X,
945 SUNXI_HDMI_VID_CTRL_REPEATER_SEL);
946 }
947 val &= ~SUNXI_HDMI_VID_CTRL_OUTPUT_FMT;
948 if (interlace_p) {
949 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_OUTPUT_FMT_INTERLACE,
950 SUNXI_HDMI_VID_CTRL_OUTPUT_FMT);
951 }
952 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val);
953
954 val = __SHIFTIN((mode->hdisplay << dblscan_p) - 1,
955 SUNXI_HDMI_VID_TIMING_0_ACT_H);
956 val |= __SHIFTIN(mode->vdisplay - 1,
957 SUNXI_HDMI_VID_TIMING_0_ACT_V);
958 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_0_REG, val);
959
960 val = __SHIFTIN((hbp << dblscan_p) - 1,
961 SUNXI_HDMI_VID_TIMING_1_HBP);
962 val |= __SHIFTIN(vbp - 1,
963 SUNXI_HDMI_VID_TIMING_1_VBP);
964 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_1_REG, val);
965
966 val = __SHIFTIN((hfp << dblscan_p) - 1,
967 SUNXI_HDMI_VID_TIMING_2_HFP);
968 val |= __SHIFTIN(vfp - 1,
969 SUNXI_HDMI_VID_TIMING_2_VFP);
970 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_2_REG, val);
971
972 val = __SHIFTIN((hspw << dblscan_p) - 1,
973 SUNXI_HDMI_VID_TIMING_3_HSPW);
974 val |= __SHIFTIN(vspw - 1,
975 SUNXI_HDMI_VID_TIMING_3_VSPW);
976 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_3_REG, val);
977
978 val = 0;
979 if (phsync_p) {
980 val |= SUNXI_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL;
981 }
982 if (pvsync_p) {
983 val |= SUNXI_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL;
984 }
985 val |= __SHIFTIN(SUNXI_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL,
986 SUNXI_HDMI_VID_TIMING_4_TX_CLOCK);
987 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_4_REG, val);
988
989 /* Packet control */
990 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT0_REG, 0);
991 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT1_REG, 0);
992 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL0_REG, 0x00005321);
993 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL1_REG, 0x0000000f);
994 }
995
996 static void
sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc * sc,const struct videomode * mode,u_int display_mode)997 sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *sc,
998 const struct videomode *mode, u_int display_mode)
999 {
1000 uint32_t cts, n, val;
1001
1002 /*
1003 * Before changing audio parameters, disable and reset the
1004 * audio module. Wait for the soft reset bit to clear before
1005 * configuring the audio parameters.
1006 */
1007 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG);
1008 val &= ~SUNXI_HDMI_AUD_CTRL_EN;
1009 val |= SUNXI_HDMI_AUD_CTRL_RST;
1010 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val);
1011 do {
1012 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG);
1013 } while (val & SUNXI_HDMI_AUD_CTRL_RST);
1014
1015 /* No audio support in DVI mode */
1016 if (display_mode != DISPLAY_MODE_HDMI) {
1017 return;
1018 }
1019
1020 /* DMA & FIFO control */
1021 val = HDMI_READ(sc, SUNXI_HDMI_ADMA_CTRL_REG);
1022 if (sc->sc_type == HDMI_A31) {
1023 val |= SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* NDMA */
1024 } else {
1025 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* DDMA */
1026 }
1027 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_SAMPLE_RATE;
1028 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_SAMPLE_LAYOUT;
1029 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_WORD_LEN;
1030 val &= ~SUNXI_HDMI_ADMA_CTRL_DATA_SEL;
1031 HDMI_WRITE(sc, SUNXI_HDMI_ADMA_CTRL_REG, val);
1032
1033 /* Audio format control */
1034 val = HDMI_READ(sc, SUNXI_HDMI_AUD_FMT_REG);
1035 val &= ~SUNXI_HDMI_AUD_FMT_SRC_SEL;
1036 val &= ~SUNXI_HDMI_AUD_FMT_SEL;
1037 val &= ~SUNXI_HDMI_AUD_FMT_DSD_FMT;
1038 val &= ~SUNXI_HDMI_AUD_FMT_LAYOUT;
1039 val &= ~SUNXI_HDMI_AUD_FMT_SRC_CH_CFG;
1040 val |= __SHIFTIN(1, SUNXI_HDMI_AUD_FMT_SRC_CH_CFG);
1041 HDMI_WRITE(sc, SUNXI_HDMI_AUD_FMT_REG, val);
1042
1043 /* PCM control (channel map) */
1044 HDMI_WRITE(sc, SUNXI_HDMI_AUD_PCM_CTRL_REG, 0x76543210);
1045
1046 /* Clock setup */
1047 n = 6144; /* 48 kHz */
1048 cts = ((mode->dot_clock * 10) * (n / 128)) / 480;
1049 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTS_REG, cts);
1050 HDMI_WRITE(sc, SUNXI_HDMI_AUD_N_REG, n);
1051
1052 /* Audio PCM channel status 0 */
1053 val = __SHIFTIN(SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_48,
1054 SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ);
1055 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS0_REG, val);
1056
1057 /* Audio PCM channel status 1 */
1058 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG);
1059 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_CGMS_A;
1060 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_ORIGINAL_FS;
1061 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN;
1062 val |= __SHIFTIN(5, SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN);
1063 val |= SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN_MAX;
1064 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG, val);
1065
1066 /* Re-enable */
1067 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG);
1068 val |= SUNXI_HDMI_AUD_CTRL_EN;
1069 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val);
1070
1071 #if defined(SUNXI_HDMI_DEBUG)
1072 sunxi_hdmi_dump_regs();
1073 #endif
1074 }
1075
1076 static void
sunxi_hdmi_hpd(struct sunxi_hdmi_softc * sc)1077 sunxi_hdmi_hpd(struct sunxi_hdmi_softc *sc)
1078 {
1079 uint32_t hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG);
1080 bool con = !!(hpd & SUNXI_HDMI_HPD_HOTPLUG_DET);
1081
1082 KASSERT(mutex_owned(&sc->sc_pwr_lock));
1083 if (sc->sc_display_connected == con)
1084 return;
1085
1086 if (con) {
1087 device_printf(sc->sc_dev, "display connected\n");
1088 sc->sc_pwr_refcount = 1;
1089 sunxi_hdmi_read_edid(sc);
1090 } else {
1091 device_printf(sc->sc_dev, "display disconnected\n");
1092 sc->sc_pwr_refcount = 0;
1093 sunxi_hdmi_video_enable(sc, false);
1094 fdt_endpoint_enable(sc->sc_in_ep, false);
1095 sunxi_tcon1_set_videomode(
1096 fdt_endpoint_device(sc->sc_in_rep), NULL);
1097 }
1098
1099 sc->sc_display_connected = con;
1100 }
1101
1102 static void
sunxi_hdmi_thread(void * priv)1103 sunxi_hdmi_thread(void *priv)
1104 {
1105 struct sunxi_hdmi_softc *sc = priv;
1106
1107 for (;;) {
1108 mutex_enter(&sc->sc_pwr_lock);
1109 sunxi_hdmi_hpd(sc);
1110 mutex_exit(&sc->sc_pwr_lock);
1111 kpause("hdmihotplug", false, mstohz(1000), NULL);
1112 }
1113 }
1114
1115 static int
sunxi_hdmi_poweron(struct sunxi_hdmi_softc * sc,bool enable)1116 sunxi_hdmi_poweron(struct sunxi_hdmi_softc *sc, bool enable)
1117 {
1118 int error = 0;
1119 KASSERT(mutex_owned(&sc->sc_pwr_lock));
1120 if (!sc->sc_display_connected)
1121 return EOPNOTSUPP;
1122 if (enable) {
1123 KASSERT(sc->sc_pwr_refcount >= 0);
1124 if (sc->sc_pwr_refcount == 0) {
1125 error = fdt_endpoint_enable(sc->sc_in_ep, true);
1126 if (error)
1127 return error;
1128 sunxi_hdmi_video_enable(sc, true);
1129 }
1130 sc->sc_pwr_refcount++;
1131 } else {
1132 sc->sc_pwr_refcount--;
1133 KASSERT(sc->sc_pwr_refcount >= 0);
1134 if (sc->sc_pwr_refcount == 0) {
1135 sunxi_hdmi_video_enable(sc, false);
1136 error = fdt_endpoint_enable(sc->sc_in_ep, false);
1137 }
1138 }
1139 return error;
1140 }
1141 #if 0
1142 static int
1143 sunxi_hdmi_intr(void *priv)
1144 {
1145 struct sunxi_hdmi_softc *sc = priv;
1146 uint32_t intsts;
1147
1148 intsts = HDMI_READ(sc, SUNXI_HDMI_INT_STATUS_REG);
1149 if (!(intsts & 0x73))
1150 return 0;
1151
1152 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, intsts);
1153
1154 device_printf(sc->sc_dev, "INT_STATUS %08X\n", intsts);
1155
1156 return 1;
1157 }
1158 #endif
1159
1160 #if 0 /* XXX audio */
1161 void
1162 sunxi_hdmi_get_info(struct sunxi_hdmi_info *info)
1163 {
1164 struct sunxi_hdmi_softc *sc;
1165 device_t dev;
1166
1167 memset(info, 0, sizeof(*info));
1168
1169 dev = device_find_by_driver_unit("sunxihdmi", 0);
1170 if (dev == NULL) {
1171 info->display_connected = false;
1172 return;
1173 }
1174 sc = device_private(dev);
1175
1176 info->display_connected = sc->sc_display_connected;
1177 if (info->display_connected) {
1178 strlcpy(info->display_vendor, sc->sc_display_vendor,
1179 sizeof(info->display_vendor));
1180 strlcpy(info->display_product, sc->sc_display_product,
1181 sizeof(info->display_product));
1182 info->display_hdmimode =
1183 sc->sc_current_display_mode == DISPLAY_MODE_HDMI;
1184 }
1185 }
1186 #endif
1187
1188 #if defined(SUNXI_HDMI_DEBUG)
1189 void
sunxi_hdmi_dump_regs(void)1190 sunxi_hdmi_dump_regs(void)
1191 {
1192 static const struct {
1193 const char *name;
1194 uint16_t reg;
1195 } regs[] = {
1196 { "CTRL", SUNXI_HDMI_CTRL_REG },
1197 { "INT_STATUS", SUNXI_HDMI_INT_STATUS_REG },
1198 { "VID_CTRL", SUNXI_HDMI_VID_CTRL_REG },
1199 { "VID_TIMING_0", SUNXI_HDMI_VID_TIMING_0_REG },
1200 { "VID_TIMING_1", SUNXI_HDMI_VID_TIMING_1_REG },
1201 { "VID_TIMING_2", SUNXI_HDMI_VID_TIMING_2_REG },
1202 { "VID_TIMING_3", SUNXI_HDMI_VID_TIMING_3_REG },
1203 { "VID_TIMING_4", SUNXI_HDMI_VID_TIMING_4_REG },
1204 { "PAD_CTRL0", SUNXI_HDMI_PAD_CTRL0_REG },
1205 { "PAD_CTRL1", SUNXI_HDMI_PAD_CTRL1_REG },
1206 { "PLL_CTRL", SUNXI_HDMI_PLL_CTRL_REG },
1207 { "PLL_DBG0", SUNXI_HDMI_PLL_DBG0_REG },
1208 { "PLL_DBG1", SUNXI_HDMI_PLL_DBG1_REG },
1209 };
1210 struct sunxi_hdmi_softc *sc;
1211 device_t dev;
1212
1213 dev = device_find_by_driver_unit("sunxihdmi", 0);
1214 if (dev == NULL)
1215 return;
1216 sc = device_private(dev);
1217
1218 for (int i = 0; i < __arraycount(regs); i++) {
1219 printf("%s: 0x%08x\n", regs[i].name,
1220 HDMI_READ(sc, regs[i].reg));
1221 }
1222 }
1223 #endif
1224