1 /*-
2 * Copyright (c) 2012 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Paul Fleischer <paul@xpg.dk>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /* Derived from s3c2410.c */
31 /*
32 * Copyright (c) 2003, 2005 Genetec corporation. All rights reserved.
33 * Written by Hiroyuki Bessho for Genetec corporation.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. The name of Genetec corporation may not be used to endorse
44 * or promote products derived from this software without specific prior
45 * written permission.
46 *
47 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
57 * POSSIBILITY OF SUCH DAMAGE.
58 */
59
60 #include <sys/cdefs.h>
61 __KERNEL_RCSID(0, "$NetBSD: s3c2440.c,v 1.4 2021/08/07 16:18:45 thorpej Exp $");
62
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/device.h>
66 #include <sys/kernel.h>
67 #include <sys/reboot.h>
68
69 #include <machine/cpu.h>
70 #include <sys/bus.h>
71
72 #include <arm/cpufunc.h>
73 #include <arm/mainbus/mainbus.h>
74 #include <arm/s3c2xx0/s3c2440reg.h>
75 #include <arm/s3c2xx0/s3c2440var.h>
76 #include <arm/s3c2xx0/s3c2440_dma.h>
77
78 #include "locators.h"
79 #include "opt_cpuoptions.h"
80
81 /* prototypes */
82 static int s3c2440_match(device_t, cfdata_t, void *);
83 static void s3c2440_attach(device_t, device_t, void *);
84 static int s3c2440_search(device_t, cfdata_t, const int *, void *);
85
86 /* attach structures */
87 CFATTACH_DECL_NEW(ssio, sizeof(struct s3c24x0_softc), s3c2440_match, s3c2440_attach,
88 NULL, NULL);
89
90 extern struct bus_space s3c2xx0_bs_tag;
91
92 struct s3c2xx0_softc *s3c2xx0_softc;
93
94 #ifdef DEBUG_PORTF
95 volatile uint8_t *portf; /* for debug */
96 #endif
97
98 static int
s3c2440_print(void * aux,const char * name)99 s3c2440_print(void *aux, const char *name)
100 {
101 struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *) aux;
102
103 if (sa->sa_size)
104 aprint_normal(" addr 0x%lx", sa->sa_addr);
105 if (sa->sa_size > 1)
106 aprint_normal("-0x%lx", sa->sa_addr + sa->sa_size - 1);
107 if (sa->sa_intr != SSIOCF_INTR_DEFAULT)
108 aprint_normal(" intr %d", sa->sa_intr);
109 if (sa->sa_index != SSIOCF_INDEX_DEFAULT)
110 aprint_normal(" unit %d", sa->sa_index);
111
112 return (UNCONF);
113 }
114
115 int
s3c2440_match(device_t parent,cfdata_t match,void * aux)116 s3c2440_match(device_t parent, cfdata_t match, void *aux)
117 {
118 return 1;
119 }
120
121 void
s3c2440_attach(device_t parent,device_t self,void * aux)122 s3c2440_attach(device_t parent, device_t self, void *aux)
123 {
124 struct s3c24x0_softc *sc = device_private(self);
125 bus_space_tag_t iot;
126 const char *which_registers; /* for panic message */
127
128 #define FAIL(which) do { \
129 which_registers=(which); goto abort; }while(/*CONSTCOND*/0)
130
131 s3c2xx0_softc = &(sc->sc_sx);
132 sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
133
134 if (bus_space_map(iot,
135 S3C2440_INTCTL_BASE, S3C2440_INTCTL_SIZE,
136 BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh))
137 FAIL("intc");
138 /* tell register addresses to interrupt handler */
139 s3c2440_intr_init(sc);
140
141 /* Map the GPIO registers */
142 if (bus_space_map(iot, S3C2440_GPIO_BASE, S3C2440_GPIO_SIZE,
143 0, &sc->sc_sx.sc_gpio_ioh))
144 FAIL("GPIO");
145 #ifdef DEBUG_PORTF
146 {
147 extern volatile uint8_t *portf;
148 /* make all ports output */
149 bus_space_write_2(iot, sc->sc_sx.sc_gpio_ioh, GPIO_PCONF, 0x5555);
150 portf = (volatile uint8_t *)
151 ((char *)bus_space_vaddr(iot, sc->sc_sx.sc_gpio_ioh) + GPIO_PDATF);
152 }
153 #endif
154
155 #if 1
156 /* Map the DMA controller registers */
157 if (bus_space_map(iot, S3C2440_DMAC_BASE, S3C2440_DMAC_SIZE,
158 0, &sc->sc_sx.sc_dmach))
159 FAIL("DMAC");
160 #endif
161
162 /* Memory controller */
163 if (bus_space_map(iot, S3C2440_MEMCTL_BASE,
164 S3C24X0_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh))
165 FAIL("MEMC");
166 /* Clock manager */
167 if (bus_space_map(iot, S3C2440_CLKMAN_BASE,
168 S3C24X0_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh))
169 FAIL("CLK");
170
171 #if 0
172 /* Real time clock */
173 if (bus_space_map(iot, S3C2410_RTC_BASE,
174 S3C24X0_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh))
175 FAIL("RTC");
176 #endif
177
178 if (bus_space_map(iot, S3C2440_TIMER_BASE,
179 S3C24X0_TIMER_SIZE, 0, &sc->sc_timer_ioh)) {
180 FAIL("TIMER");
181 }
182
183 /* calculate current clock frequency */
184 s3c24x0_clock_freq(&sc->sc_sx);
185 aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
186 sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
187 sc->sc_sx.sc_pclk / 1000000);
188
189 aprint_naive("\n");
190
191 /* get busdma tag for the platform */
192 sc->sc_sx.sc_dmat = s3c2xx0_bus_dma_init(&s3c2xx0_bus_dma);
193
194 s3c2440_dma_init();
195
196 /*
197 * Attach devices.
198 */
199 config_search(self, NULL,
200 CFARGS(.search = s3c2440_search));
201 return;
202
203 abort:
204 panic("%s: unable to map %s registers",
205 device_xname(self), which_registers);
206
207 #undef FAIL
208 }
209
210 int
s3c2440_search(device_t parent,cfdata_t cf,const int * ldesc,void * aux)211 s3c2440_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
212 {
213 struct s3c24x0_softc *sc = device_private(parent);
214 struct s3c2xx0_attach_args aa;
215
216 aa.sa_sc = sc;
217 aa.sa_iot = sc->sc_sx.sc_iot;
218 aa.sa_addr = cf->cf_loc[SSIOCF_ADDR];
219 aa.sa_size = cf->cf_loc[SSIOCF_SIZE];
220 aa.sa_index = cf->cf_loc[SSIOCF_INDEX];
221 aa.sa_intr = cf->cf_loc[SSIOCF_INTR];
222
223 aa.sa_dmat = sc->sc_sx.sc_dmat;
224
225 if (config_probe(parent, cf, &aa))
226 config_attach(parent, cf, &aa, s3c2440_print, CFARGS_NONE);
227
228 return 0;
229 }
230
231 /*
232 * fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register.
233 *
234 * s3c24x0_clock_freq2() is meant to be called from kernel startup routines.
235 * s3c24x0_clock_freq() is for after kernel initialization is done.
236 */
237 void
s3c24x0_clock_freq2(vaddr_t clkman_base,int * fclk,int * hclk,int * pclk)238 s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
239 {
240 uint32_t pllcon, divn, camdivn;
241 int mdiv, pdiv, sdiv;
242 uint32_t f, h, p;
243
244 pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON);
245 divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
246 camdivn = *(volatile uint32_t *)(clkman_base + CLKMAN_CAMDIVN);
247
248 mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
249 pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
250 sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
251
252 f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)) * 2;
253 h = f;
254
255 /* HDIVN of CLKDIVN can have 4 distinct values */
256 switch( (divn & CLKDIVN_HDIVN_MASK) >> CLKDIVN_HDIVN_SHIFT )
257 {
258 case 0:
259 /* 00b: HCLK = FCLK/1*/
260 break;
261 case 1:
262 /* 01b: HCLK = FCLK/2*/
263 h /= 2;
264 break;
265 case 2:
266 /* 10b: HCLK = FCLK/4 when CAMDIVN[9] (HCLK4_HALF) = 0
267 * HCLK = FCLK/8 when CAMDIVN[9] (HCLK4_HALF) = 1 */
268 if( camdivn & CLKCAMDIVN_HCLK4_HALF )
269 h /= 8;
270 else
271 h /= 4;
272 break;
273 case 3:
274 /* 11b: HCLK = FCLK/3 when CAMDIVN[8] (HCLK3_HALF) = 0
275 * HCLK = FCLK/6 when CAMDIVN[8] (HCLK3_HALF) = 1 */
276 if( camdivn & CLKCAMDIVN_HCLK3_HALF )
277 h /= 6;
278 else
279 h /= 3;
280 break;
281 }
282
283 p = h;
284
285 if (divn & CLKDIVN_PDIVN)
286 p /= 2;
287
288 if (fclk) *fclk = f;
289 if (hclk) *hclk = h;
290 if (pclk) *pclk = p;
291
292 }
293
294 void
s3c24x0_clock_freq(struct s3c2xx0_softc * sc)295 s3c24x0_clock_freq(struct s3c2xx0_softc *sc)
296 {
297 s3c24x0_clock_freq2(
298 (vaddr_t)bus_space_vaddr(sc->sc_iot, sc->sc_clkman_ioh),
299 &sc->sc_fclk, &sc->sc_hclk, &sc->sc_pclk);
300 }
301
302 /*
303 * Issue software reset command.
304 * called with MMU off.
305 *
306 * S3C2410 doesn't have sowtware reset bit like S3C2800.
307 * use watch dog timer and make it fire immediately.
308 */
309 void
s3c2440_softreset(void)310 s3c2440_softreset(void)
311 {
312 disable_interrupts(I32_bit|F32_bit);
313
314 *(volatile unsigned int *)(S3C2440_WDT_BASE + WDT_WTCON)
315 = (0 << WTCON_PRESCALE_SHIFT) | WTCON_ENABLE |
316 WTCON_CLKSEL_16 | WTCON_ENRST;
317 }
318
319
320