1 /* $NetBSD: rk_pwm.c,v 1.7 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: rk_pwm.c,v 1.7 2021/01/27 03:10:19 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/intr.h>
37 #include <sys/systm.h>
38 #include <sys/time.h>
39
40 #include <dev/pwm/pwmvar.h>
41
42 #include <dev/fdt/fdtvar.h>
43
44 #define PWM0_CNT 0x00
45 #define PWM0_PERIOD_HPR 0x04
46 #define PWM0_DUTY_LPR 0x08
47 #define PWM0_CTRL 0x0c
48 #define CTRL_RPT __BITS(31,24)
49 #define CTRL_SCALE __BITS(23,16)
50 #define CTRL_PRESCALE __BITS(14,12)
51 #define CTRL_CLK_SEL __BIT(9)
52 #define CTRL_LP_EN __BIT(8)
53 #define CTRL_OUTPUT_MODE __BIT(5)
54 #define CTRL_INACTIVE_POL __BIT(4)
55 #define CTRL_DUTY_POL __BIT(3)
56 #define CTRL_PWM_MODE __BITS(2,1)
57 #define CTRL_PWM_MODE_ONESHOT 0
58 #define CTRL_PWM_MODE_CONTINUOUS 1
59 #define CTRL_PWM_MODE_CAPTURE 2
60 #define CTRL_PWM_EN __BIT(0)
61
62 enum rk_pwm_type {
63 PWM_RK3288 = 1,
64 };
65
66 static const struct device_compatible_entry compat_data[] = {
67 { .compat = "rockchip,rk3288-pwm", .value = PWM_RK3288 },
68 DEVICE_COMPAT_EOL
69 };
70
71 struct rk_pwm_softc {
72 device_t sc_dev;
73 bus_space_tag_t sc_bst;
74 bus_space_handle_t sc_bsh;
75
76 struct pwm_controller sc_pwm;
77 struct pwm_config sc_conf;
78
79 u_int sc_clkfreq;
80 };
81
82 #define PWM_READ(sc, reg) \
83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
84 #define PWM_WRITE(sc, reg, val) \
85 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
86
87 static pwm_tag_t
rk_pwm_get_tag(device_t dev,const void * data,size_t len)88 rk_pwm_get_tag(device_t dev, const void *data, size_t len)
89 {
90 struct rk_pwm_softc * const sc = device_private(dev);
91 const u_int *pwm = data;
92
93 if (len != 16)
94 return NULL;
95
96 const u_int index = be32toh(pwm[1]);
97 if (index != 0)
98 return NULL;
99
100 const u_int period = be32toh(pwm[2]);
101 const u_int polarity = be32toh(pwm[3]);
102
103 sc->sc_conf.period = period;
104 sc->sc_conf.polarity = polarity ? PWM_ACTIVE_LOW : PWM_ACTIVE_HIGH;
105
106 return &sc->sc_pwm;
107 }
108
109 static struct fdtbus_pwm_controller_func rk_pwm_funcs = {
110 .get_tag = rk_pwm_get_tag
111 };
112
113 static int
rk_pwm_enable(pwm_tag_t pwm,bool enable)114 rk_pwm_enable(pwm_tag_t pwm, bool enable)
115 {
116 struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev);
117 uint32_t ctrl, octrl;
118
119 octrl = ctrl = PWM_READ(sc, PWM0_CTRL);
120 if (enable)
121 ctrl |= CTRL_PWM_EN;
122 else
123 ctrl &= ~CTRL_PWM_EN;
124
125 if (ctrl != octrl)
126 PWM_WRITE(sc, PWM0_CTRL, ctrl);
127
128 return 0;
129 }
130
131 static int
rk_pwm_get_config(pwm_tag_t pwm,struct pwm_config * conf)132 rk_pwm_get_config(pwm_tag_t pwm, struct pwm_config *conf)
133 {
134 struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev);
135
136 #if 0
137 /* XXX may be useful someday */
138
139 uint32_t ctrl, period, duty;
140 u_int div;
141
142 ctrl = PWM_READ(sc, PWM0_CTRL);
143 period = PWM_READ(sc, PWM0_PERIOD_HPR);
144 duty = PWM_READ(sc, PWM0_DUTY_LPR);
145
146 if (ctrl & CTRL_CLK_SEL) {
147 div = __SHIFTOUT(ctrl, CTRL_SCALE) * 2;
148 if (div == 0)
149 div = 512;
150 } else {
151 div = 1;
152 }
153 div /= (1 << __SHIFTOUT(ctrl, CTRL_PRESCALE));
154
155 const uint64_t rate = sc->sc_clkfreq / div;
156
157 conf->polarity = (ctrl & CTRL_DUTY_POL) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
158 conf->period = (u_int)(((uint64_t)period * 1000000000) / rate);
159 conf->duty_cycle = (u_int)(((uint64_t)duty * 1000000000) / rate);
160 #else
161 *conf = sc->sc_conf;
162 #endif
163
164 return 0;
165 }
166
167 static int
rk_pwm_set_config(pwm_tag_t pwm,const struct pwm_config * conf)168 rk_pwm_set_config(pwm_tag_t pwm, const struct pwm_config *conf)
169 {
170 struct rk_pwm_softc * const sc = device_private(pwm->pwm_dev);
171 uint32_t ctrl;
172
173 const uint64_t rate = sc->sc_clkfreq;
174 const uint32_t period = (u_int)((conf->period * rate) / 1000000000);
175 const uint32_t duty = (u_int)((conf->duty_cycle * rate) / 1000000000);
176
177 /* Preserve PWM_EN flag */
178 ctrl = PWM_READ(sc, PWM0_CTRL) & CTRL_PWM_EN;
179
180 ctrl |= __SHIFTIN(CTRL_PWM_MODE_CONTINUOUS, CTRL_PWM_MODE);
181 if (conf->polarity == PWM_ACTIVE_HIGH)
182 ctrl |= CTRL_DUTY_POL;
183 else
184 ctrl |= CTRL_INACTIVE_POL;
185
186 PWM_WRITE(sc, PWM0_CTRL, 0);
187 PWM_WRITE(sc, PWM0_PERIOD_HPR, period);
188 PWM_WRITE(sc, PWM0_DUTY_LPR, duty);
189 PWM_WRITE(sc, PWM0_CTRL, ctrl);
190
191 sc->sc_conf = *conf;
192
193 return 0;
194 }
195
196 static int
rk_pwm_match(device_t parent,cfdata_t cf,void * aux)197 rk_pwm_match(device_t parent, cfdata_t cf, void *aux)
198 {
199 struct fdt_attach_args * const faa = aux;
200
201 return of_compatible_match(faa->faa_phandle, compat_data);
202 }
203
204 static void
rk_pwm_attach(device_t parent,device_t self,void * aux)205 rk_pwm_attach(device_t parent, device_t self, void *aux)
206 {
207 struct rk_pwm_softc * const sc = device_private(self);
208 struct fdt_attach_args * const faa = aux;
209 const int phandle = faa->faa_phandle;
210 struct clk *clk;
211 bus_addr_t addr;
212 bus_size_t size;
213 int error;
214
215 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
216 aprint_error(": couldn't get registers\n");
217 return;
218 }
219
220 clk = fdtbus_clock_get_index(phandle, 0);
221 if (clk == NULL) {
222 aprint_error(": couldn't get clock\n");
223 return;
224 }
225
226 sc->sc_dev = self;
227 sc->sc_clkfreq = clk_get_rate(clk);
228 sc->sc_bst = faa->faa_bst;
229 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
230 if (error) {
231 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d",
232 addr, error);
233 return;
234 }
235
236 aprint_naive("\n");
237 aprint_normal(": PWM\n");
238
239 sc->sc_pwm.pwm_enable = rk_pwm_enable;
240 sc->sc_pwm.pwm_get_config = rk_pwm_get_config;
241 sc->sc_pwm.pwm_set_config = rk_pwm_set_config;
242 sc->sc_pwm.pwm_dev = self;
243
244 fdtbus_register_pwm_controller(self, phandle,
245 &rk_pwm_funcs);
246 }
247
248 CFATTACH_DECL_NEW(rk_pwm, sizeof(struct rk_pwm_softc),
249 rk_pwm_match, rk_pwm_attach, NULL, NULL);
250