1*6e54367aSthorpej /* $NetBSD: imxwdog.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $ */
28644267aSskrll
38644267aSskrll /*
48644267aSskrll * Copyright (c) 2010 Genetec Corporation. All rights reserved.
58644267aSskrll * Written by Hiroyuki Bessho for Genetec Corporation.
68644267aSskrll *
78644267aSskrll * Redistribution and use in source and binary forms, with or without
88644267aSskrll * modification, are permitted provided that the following conditions
98644267aSskrll * are met:
108644267aSskrll * 1. Redistributions of source code must retain the above copyright
118644267aSskrll * notice, this list of conditions and the following disclaimer.
128644267aSskrll * 2. Redistributions in binary form must reproduce the above copyright
138644267aSskrll * notice, this list of conditions and the following disclaimer in the
148644267aSskrll * documentation and/or other materials provided with the distribution.
158644267aSskrll *
168644267aSskrll * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
178644267aSskrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
188644267aSskrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
198644267aSskrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
208644267aSskrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
218644267aSskrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
228644267aSskrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
238644267aSskrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
248644267aSskrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
258644267aSskrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
268644267aSskrll * POSSIBILITY OF SUCH DAMAGE.
278644267aSskrll */
288644267aSskrll
298644267aSskrll #include <sys/cdefs.h>
30*6e54367aSthorpej __KERNEL_RCSID(0, "$NetBSD: imxwdog.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $");
318644267aSskrll
328644267aSskrll #include "opt_imx.h"
338644267aSskrll
348644267aSskrll #include <sys/param.h>
358644267aSskrll #include <sys/bus.h>
368644267aSskrll #include <sys/device.h>
378644267aSskrll #include <sys/wdog.h>
388644267aSskrll
398644267aSskrll #include <dev/sysmon/sysmonvar.h>
408644267aSskrll
418644267aSskrll #include <dev/fdt/fdtvar.h>
428644267aSskrll
438644267aSskrll #include <arm/imx/imxwdogreg.h>
448644267aSskrll
458644267aSskrll struct imxwdog_softc {
468644267aSskrll struct sysmon_wdog sc_smw;
478644267aSskrll device_t sc_dev;
488644267aSskrll bus_space_tag_t sc_iot;
498644267aSskrll bus_space_handle_t sc_ioh;
508644267aSskrll
518644267aSskrll u_int sc_wdog_max_period;
528644267aSskrll u_int sc_wdog_period;
538644267aSskrll bool sc_wdog_armed;
548644267aSskrll };
558644267aSskrll
568644267aSskrll #ifndef IMXWDOG_PERIOD_DEFAULT
578644267aSskrll #define IMXWDOG_PERIOD_DEFAULT 10
588644267aSskrll #endif
598644267aSskrll
608644267aSskrll
618644267aSskrll int imxwdog_match(device_t, cfdata_t, void *);
628644267aSskrll void imxwdog_attach(device_t, device_t, void *);
638644267aSskrll
648644267aSskrll
658644267aSskrll CFATTACH_DECL_NEW(imxwdog, sizeof(struct imxwdog_softc),
668644267aSskrll imxwdog_match, imxwdog_attach, NULL, NULL);
678644267aSskrll
68*6e54367aSthorpej static const struct device_compatible_entry compat_data[] = {
69*6e54367aSthorpej { .compat = "fsl,imx21-wdt" },
70*6e54367aSthorpej { .compat = "fsl,imx6q-wdt" },
71*6e54367aSthorpej DEVICE_COMPAT_EOL
72*6e54367aSthorpej };
73*6e54367aSthorpej
748644267aSskrll int
imxwdog_match(device_t parent,cfdata_t cf,void * aux)758644267aSskrll imxwdog_match(device_t parent, cfdata_t cf, void *aux)
768644267aSskrll {
778644267aSskrll struct fdt_attach_args * const faa = aux;
788644267aSskrll
79*6e54367aSthorpej return of_compatible_match(faa->faa_phandle, compat_data);
808644267aSskrll }
818644267aSskrll
828644267aSskrll
838644267aSskrll static inline uint16_t
wdog_read(struct imxwdog_softc * sc,bus_size_t o)848644267aSskrll wdog_read(struct imxwdog_softc *sc, bus_size_t o)
858644267aSskrll {
868644267aSskrll return bus_space_read_2(sc->sc_iot, sc->sc_ioh, o);
878644267aSskrll }
888644267aSskrll
898644267aSskrll static inline void
wdog_write(struct imxwdog_softc * sc,bus_size_t o,uint16_t v)908644267aSskrll wdog_write(struct imxwdog_softc *sc, bus_size_t o, uint16_t v)
918644267aSskrll {
928644267aSskrll bus_space_write_2(sc->sc_iot, sc->sc_ioh, o, v);
938644267aSskrll }
948644267aSskrll
958644267aSskrll static int
wdog_tickle(struct sysmon_wdog * smw)968644267aSskrll wdog_tickle(struct sysmon_wdog *smw)
978644267aSskrll {
988644267aSskrll struct imxwdog_softc * const sc = smw->smw_cookie;
998644267aSskrll
1008644267aSskrll wdog_write(sc, IMX_WDOG_WSR, WSR_MAGIC1);
1018644267aSskrll wdog_write(sc, IMX_WDOG_WSR, WSR_MAGIC2);
1028644267aSskrll
1038644267aSskrll return 0;
1048644267aSskrll }
1058644267aSskrll
1068644267aSskrll static int
wdog_setmode(struct sysmon_wdog * smw)1078644267aSskrll wdog_setmode(struct sysmon_wdog *smw)
1088644267aSskrll {
1098644267aSskrll struct imxwdog_softc * const sc = smw->smw_cookie;
1108644267aSskrll uint16_t reg;
1118644267aSskrll
1128644267aSskrll if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
1138644267aSskrll /* this chip do not support wdt disable */
1148644267aSskrll aprint_debug_dev(sc->sc_dev, "setmode disable\n");
1158644267aSskrll return sc->sc_wdog_armed ? EBUSY : 0;
1168644267aSskrll }
1178644267aSskrll
1188644267aSskrll /*
1198644267aSskrll * If no changes, just tickle it and return.
1208644267aSskrll */
1218644267aSskrll if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
1228644267aSskrll wdog_tickle(smw);
1238644267aSskrll aprint_debug_dev(sc->sc_dev, "setmode refresh\n");
1248644267aSskrll return 0;
1258644267aSskrll }
1268644267aSskrll
1278644267aSskrll /* set default */
1288644267aSskrll if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
1298644267aSskrll sc->sc_wdog_period = IMXWDOG_PERIOD_DEFAULT;
1308644267aSskrll smw->smw_period = IMXWDOG_PERIOD_DEFAULT;
1318644267aSskrll }
1328644267aSskrll
1338644267aSskrll /*
1348644267aSskrll * Make sure we don't overflow the counter.
1358644267aSskrll */
1368644267aSskrll if (smw->smw_period >= sc->sc_wdog_max_period)
1378644267aSskrll return EINVAL;
1388644267aSskrll
1398644267aSskrll sc->sc_wdog_period = smw->smw_period;
1408644267aSskrll sc->sc_wdog_armed = true;
1418644267aSskrll
1428644267aSskrll reg = wdog_read(sc, IMX_WDOG_WCR);
1438644267aSskrll reg &= ~WCR_WT;
1448644267aSskrll reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);
1458644267aSskrll reg |= WCR_WDE;
1468644267aSskrll wdog_write(sc, IMX_WDOG_WCR, reg);
1478644267aSskrll
1488644267aSskrll return 0;
1498644267aSskrll }
1508644267aSskrll
1518644267aSskrll
1528644267aSskrll void
imxwdog_attach(device_t parent,device_t self,void * aux)1538644267aSskrll imxwdog_attach(device_t parent, device_t self, void *aux)
1548644267aSskrll {
1558644267aSskrll struct imxwdog_softc *sc = device_private(self);
1568644267aSskrll struct fdt_attach_args * const faa = aux;
1578644267aSskrll const int phandle = faa->faa_phandle;
1588644267aSskrll bus_space_tag_t bst = faa->faa_bst;
1598644267aSskrll bus_addr_t addr;
1608644267aSskrll bus_size_t size;
1618644267aSskrll
1628644267aSskrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
1638644267aSskrll aprint_error(": couldn't get registers\n");
1648644267aSskrll return;
1658644267aSskrll }
1668644267aSskrll
1678644267aSskrll int error = bus_space_map(bst, addr, size, 0, &sc->sc_ioh);
1688644267aSskrll if (error) {
1698644267aSskrll aprint_error(": couldn't map %" PRIxBUSADDR ": %d", addr, error);
1708644267aSskrll return;
1718644267aSskrll }
1728644267aSskrll
1738644267aSskrll #if 0
1748644267aSskrll char intrstr[128];
1758644267aSskrll if (!fdtbus_intr_str(ifsc->sc_phandle, 0, intrstr, sizeof(intrstr))) {
1768644267aSskrll aprint_error_dev(sc->sc_dev, "failed to decode interrupt\n");
1778644267aSskrll return NULL;
1788644267aSskrll }
17982b8374aSjmcneill ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
18082b8374aSjmcneill imxwdog_intr, sc, device_xname(sc->sc_dev));
1818644267aSskrll if (ih == NULL) {
1828644267aSskrll aprint_error_dev(sc->sc_dev, "failed to establish interrupt on %s\n",
1838644267aSskrll intrstr);
1848644267aSskrll return NULL;
1858644267aSskrll }
1868644267aSskrll aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr);
1878644267aSskrll #endif
1888644267aSskrll
1898644267aSskrll sc->sc_dev = self;
1908644267aSskrll sc->sc_iot = faa->faa_bst;
1918644267aSskrll
1928644267aSskrll sc->sc_wdog_armed = __SHIFTOUT(wdog_read(sc, IMX_WDOG_WCR), WCR_WDE);
1938644267aSskrll /*
1948644267aSskrll * Does the config file tell us to turn on the watchdog?
1958644267aSskrll */
1968644267aSskrll if (device_cfdata(self)->cf_flags & 1)
1978644267aSskrll sc->sc_wdog_armed = true;
1988644267aSskrll
1998644267aSskrll sc->sc_wdog_max_period = 0xff / 2;
2008644267aSskrll sc->sc_wdog_period = IMXWDOG_PERIOD_DEFAULT;
2018644267aSskrll
2028644267aSskrll uint16_t reg = wdog_read(sc, IMX_WDOG_WCR);
2038644267aSskrll reg &= ~WCR_WT;
2048644267aSskrll reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);
2058644267aSskrll wdog_write(sc, IMX_WDOG_WCR, reg);
2068644267aSskrll
2078644267aSskrll aprint_naive("\n");
2088644267aSskrll aprint_normal(": i.MX Watchdog Timer, default period is %u seconds%s\n",
2098644267aSskrll sc->sc_wdog_period,
2108644267aSskrll sc->sc_wdog_armed ? " (armed)" : "");
2118644267aSskrll
2128644267aSskrll sc->sc_smw.smw_name = device_xname(self);
2138644267aSskrll sc->sc_smw.smw_cookie = sc;
2148644267aSskrll sc->sc_smw.smw_setmode = wdog_setmode;
2158644267aSskrll sc->sc_smw.smw_tickle = wdog_tickle;
2168644267aSskrll sc->sc_smw.smw_period = sc->sc_wdog_period;
2178644267aSskrll
2188644267aSskrll if (sysmon_wdog_register(&sc->sc_smw) != 0)
2198644267aSskrll aprint_error_dev(self, "unable to register with sysmon\n");
2208644267aSskrll
2218644267aSskrll if (sc->sc_wdog_armed) {
2228644267aSskrll error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE,
2238644267aSskrll sc->sc_wdog_period);
2248644267aSskrll if (error)
2258644267aSskrll aprint_error_dev(self,
2268644267aSskrll "failed to start kernel tickler: %d\n", error);
2278644267aSskrll else {
2288644267aSskrll reg = wdog_read(sc, IMX_WDOG_WCR);
2298644267aSskrll reg |= WCR_WDE;
2308644267aSskrll wdog_write(sc, IMX_WDOG_WCR, reg);
2318644267aSskrll }
2328644267aSskrll }
2338644267aSskrll }
234