1 /* $NetBSD: imxwdog.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2010 Genetec Corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: imxwdog.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $");
31
32 #include "opt_imx.h"
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/wdog.h>
38
39 #include <dev/sysmon/sysmonvar.h>
40
41 #include <dev/fdt/fdtvar.h>
42
43 #include <arm/imx/imxwdogreg.h>
44
45 struct imxwdog_softc {
46 struct sysmon_wdog sc_smw;
47 device_t sc_dev;
48 bus_space_tag_t sc_iot;
49 bus_space_handle_t sc_ioh;
50
51 u_int sc_wdog_max_period;
52 u_int sc_wdog_period;
53 bool sc_wdog_armed;
54 };
55
56 #ifndef IMXWDOG_PERIOD_DEFAULT
57 #define IMXWDOG_PERIOD_DEFAULT 10
58 #endif
59
60
61 int imxwdog_match(device_t, cfdata_t, void *);
62 void imxwdog_attach(device_t, device_t, void *);
63
64
65 CFATTACH_DECL_NEW(imxwdog, sizeof(struct imxwdog_softc),
66 imxwdog_match, imxwdog_attach, NULL, NULL);
67
68 static const struct device_compatible_entry compat_data[] = {
69 { .compat = "fsl,imx21-wdt" },
70 { .compat = "fsl,imx6q-wdt" },
71 DEVICE_COMPAT_EOL
72 };
73
74 int
imxwdog_match(device_t parent,cfdata_t cf,void * aux)75 imxwdog_match(device_t parent, cfdata_t cf, void *aux)
76 {
77 struct fdt_attach_args * const faa = aux;
78
79 return of_compatible_match(faa->faa_phandle, compat_data);
80 }
81
82
83 static inline uint16_t
wdog_read(struct imxwdog_softc * sc,bus_size_t o)84 wdog_read(struct imxwdog_softc *sc, bus_size_t o)
85 {
86 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, o);
87 }
88
89 static inline void
wdog_write(struct imxwdog_softc * sc,bus_size_t o,uint16_t v)90 wdog_write(struct imxwdog_softc *sc, bus_size_t o, uint16_t v)
91 {
92 bus_space_write_2(sc->sc_iot, sc->sc_ioh, o, v);
93 }
94
95 static int
wdog_tickle(struct sysmon_wdog * smw)96 wdog_tickle(struct sysmon_wdog *smw)
97 {
98 struct imxwdog_softc * const sc = smw->smw_cookie;
99
100 wdog_write(sc, IMX_WDOG_WSR, WSR_MAGIC1);
101 wdog_write(sc, IMX_WDOG_WSR, WSR_MAGIC2);
102
103 return 0;
104 }
105
106 static int
wdog_setmode(struct sysmon_wdog * smw)107 wdog_setmode(struct sysmon_wdog *smw)
108 {
109 struct imxwdog_softc * const sc = smw->smw_cookie;
110 uint16_t reg;
111
112 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
113 /* this chip do not support wdt disable */
114 aprint_debug_dev(sc->sc_dev, "setmode disable\n");
115 return sc->sc_wdog_armed ? EBUSY : 0;
116 }
117
118 /*
119 * If no changes, just tickle it and return.
120 */
121 if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
122 wdog_tickle(smw);
123 aprint_debug_dev(sc->sc_dev, "setmode refresh\n");
124 return 0;
125 }
126
127 /* set default */
128 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
129 sc->sc_wdog_period = IMXWDOG_PERIOD_DEFAULT;
130 smw->smw_period = IMXWDOG_PERIOD_DEFAULT;
131 }
132
133 /*
134 * Make sure we don't overflow the counter.
135 */
136 if (smw->smw_period >= sc->sc_wdog_max_period)
137 return EINVAL;
138
139 sc->sc_wdog_period = smw->smw_period;
140 sc->sc_wdog_armed = true;
141
142 reg = wdog_read(sc, IMX_WDOG_WCR);
143 reg &= ~WCR_WT;
144 reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);
145 reg |= WCR_WDE;
146 wdog_write(sc, IMX_WDOG_WCR, reg);
147
148 return 0;
149 }
150
151
152 void
imxwdog_attach(device_t parent,device_t self,void * aux)153 imxwdog_attach(device_t parent, device_t self, void *aux)
154 {
155 struct imxwdog_softc *sc = device_private(self);
156 struct fdt_attach_args * const faa = aux;
157 const int phandle = faa->faa_phandle;
158 bus_space_tag_t bst = faa->faa_bst;
159 bus_addr_t addr;
160 bus_size_t size;
161
162 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
163 aprint_error(": couldn't get registers\n");
164 return;
165 }
166
167 int error = bus_space_map(bst, addr, size, 0, &sc->sc_ioh);
168 if (error) {
169 aprint_error(": couldn't map %" PRIxBUSADDR ": %d", addr, error);
170 return;
171 }
172
173 #if 0
174 char intrstr[128];
175 if (!fdtbus_intr_str(ifsc->sc_phandle, 0, intrstr, sizeof(intrstr))) {
176 aprint_error_dev(sc->sc_dev, "failed to decode interrupt\n");
177 return NULL;
178 }
179 ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
180 imxwdog_intr, sc, device_xname(sc->sc_dev));
181 if (ih == NULL) {
182 aprint_error_dev(sc->sc_dev, "failed to establish interrupt on %s\n",
183 intrstr);
184 return NULL;
185 }
186 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr);
187 #endif
188
189 sc->sc_dev = self;
190 sc->sc_iot = faa->faa_bst;
191
192 sc->sc_wdog_armed = __SHIFTOUT(wdog_read(sc, IMX_WDOG_WCR), WCR_WDE);
193 /*
194 * Does the config file tell us to turn on the watchdog?
195 */
196 if (device_cfdata(self)->cf_flags & 1)
197 sc->sc_wdog_armed = true;
198
199 sc->sc_wdog_max_period = 0xff / 2;
200 sc->sc_wdog_period = IMXWDOG_PERIOD_DEFAULT;
201
202 uint16_t reg = wdog_read(sc, IMX_WDOG_WCR);
203 reg &= ~WCR_WT;
204 reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);
205 wdog_write(sc, IMX_WDOG_WCR, reg);
206
207 aprint_naive("\n");
208 aprint_normal(": i.MX Watchdog Timer, default period is %u seconds%s\n",
209 sc->sc_wdog_period,
210 sc->sc_wdog_armed ? " (armed)" : "");
211
212 sc->sc_smw.smw_name = device_xname(self);
213 sc->sc_smw.smw_cookie = sc;
214 sc->sc_smw.smw_setmode = wdog_setmode;
215 sc->sc_smw.smw_tickle = wdog_tickle;
216 sc->sc_smw.smw_period = sc->sc_wdog_period;
217
218 if (sysmon_wdog_register(&sc->sc_smw) != 0)
219 aprint_error_dev(self, "unable to register with sysmon\n");
220
221 if (sc->sc_wdog_armed) {
222 error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE,
223 sc->sc_wdog_period);
224 if (error)
225 aprint_error_dev(self,
226 "failed to start kernel tickler: %d\n", error);
227 else {
228 reg = wdog_read(sc, IMX_WDOG_WCR);
229 reg |= WCR_WDE;
230 wdog_write(sc, IMX_WDOG_WCR, reg);
231 }
232 }
233 }
234