1 /* $NetBSD: imx_sdhc.c,v 1.8 2023/05/04 13:29:33 bouyer Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Genetec Corporation. All rights reserved.
5 * Written by Hashimoto Kenichi for Genetec Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: imx_sdhc.c,v 1.8 2023/05/04 13:29:33 bouyer Exp $");
31
32 #include "opt_fdt.h"
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/intr.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/gpio.h>
41
42 #include <dev/sdmmc/sdhcreg.h>
43 #include <dev/sdmmc/sdhcvar.h>
44 #include <dev/sdmmc/sdmmcvar.h>
45
46 #include <dev/fdt/fdtvar.h>
47
48 static int imx_sdhc_match(device_t, cfdata_t, void *);
49 static void imx_sdhc_attach(device_t, device_t, void *);
50
51 static int imx_sdhc_card_detect(struct sdhc_softc *);
52 static int imx_sdhc_write_protect(struct sdhc_softc *);
53
54 struct imx_sdhc_softc {
55 struct sdhc_softc sc_sdhc;
56
57 bus_space_tag_t sc_bst;
58 bus_space_handle_t sc_bsh;
59 bus_size_t sc_bsz;
60
61 struct sdhc_host *sc_host;
62 void *sc_ih;
63
64 struct clk *sc_clk_per;
65 struct fdtbus_regulator *sc_vmmc_supply;
66
67 struct fdtbus_gpio_pin *sc_pin_cd;
68 struct fdtbus_gpio_pin *sc_pin_wp;
69 };
70
71 CFATTACH_DECL_NEW(imx_sdhc, sizeof(struct imx_sdhc_softc),
72 imx_sdhc_match, imx_sdhc_attach, NULL, NULL);
73
74 struct imx6_sdhc_config {
75 uint32_t flags;
76 };
77
78 static const struct imx6_sdhc_config imx6q_config = {
79 .flags = SDHC_FLAG_BROKEN_ADMA2_ZEROLEN |
80 SDHC_FLAG_NO_BUSY_INTR,
81 };
82
83 static const struct imx6_sdhc_config imx7d_config = {
84 .flags = 0
85 };
86
87 static const struct device_compatible_entry compat_data[] = {
88 { .compat = "fsl,imx6q-usdhc", .data = &imx6q_config },
89 { .compat = "fsl,imx6sx-usdhc", .data = &imx6q_config },
90 { .compat = "fsl,imx7d-usdhc", .data = &imx7d_config },
91 DEVICE_COMPAT_EOL
92 };
93
94 static int
imx_sdhc_match(device_t parent,cfdata_t cf,void * aux)95 imx_sdhc_match(device_t parent, cfdata_t cf, void *aux)
96 {
97 struct fdt_attach_args * const faa = aux;
98
99 return of_compatible_match(faa->faa_phandle, compat_data);
100 }
101
102 static void
imx_sdhc_attach(device_t parent,device_t self,void * aux)103 imx_sdhc_attach(device_t parent, device_t self, void *aux)
104 {
105 struct imx_sdhc_softc * const sc = device_private(self);
106 struct fdt_attach_args * const faa = aux;
107 const int phandle = faa->faa_phandle;
108 const struct imx6_sdhc_config *conf;
109 char intrstr[128];
110 bus_addr_t addr;
111 bus_size_t size;
112 u_int bus_width;
113 int error;
114
115 fdtbus_clock_assign(phandle);
116
117 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
118 aprint_error(": couldn't get registers\n");
119 return;
120 }
121
122 sc->sc_clk_per = fdtbus_clock_get(phandle, "per");
123 if (sc->sc_clk_per == NULL) {
124 aprint_error(": couldn't get clock\n");
125 return;
126 }
127
128 if (of_getprop_uint32(phandle, "bus-width", &bus_width))
129 bus_width = 4;
130
131 sc->sc_vmmc_supply = fdtbus_regulator_acquire(phandle, "vmmc-supply");
132
133 conf = of_compatible_lookup(phandle, compat_data)->data;
134
135 sc->sc_sdhc.sc_dev = self;
136 sc->sc_sdhc.sc_dmat = faa->faa_dmat;
137
138 sc->sc_sdhc.sc_clkbase = clk_get_rate(sc->sc_clk_per) / 1000;
139 sc->sc_sdhc.sc_flags =
140 SDHC_FLAG_USE_DMA |
141 SDHC_FLAG_NO_PWR0 |
142 SDHC_FLAG_HAVE_DVS |
143 SDHC_FLAG_32BIT_ACCESS |
144 SDHC_FLAG_USDHC;
145 sc->sc_sdhc.sc_flags |= conf->flags;
146
147 if (bus_width == 8)
148 sc->sc_sdhc.sc_flags |= SDHC_FLAG_8BIT_MODE;
149 if (of_hasprop(phandle, "no-1-8-v"))
150 sc->sc_sdhc.sc_flags |= SDHC_FLAG_NO_1_8_V;
151
152 sc->sc_sdhc.sc_host = &sc->sc_host;
153
154 sc->sc_bst = faa->faa_bst;
155 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
156 if (error) {
157 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
158 return;
159 }
160 sc->sc_bsz = size;
161
162 sc->sc_pin_cd = fdtbus_gpio_acquire(phandle,
163 "cd-gpios", GPIO_PIN_INPUT);
164 if (sc->sc_pin_cd) {
165 sc->sc_sdhc.sc_vendor_card_detect = imx_sdhc_card_detect;
166 sc->sc_sdhc.sc_flags |= SDHC_FLAG_POLL_CARD_DET;
167 }
168
169 sc->sc_pin_wp = fdtbus_gpio_acquire(phandle,
170 "wp-gpios", GPIO_PIN_INPUT);
171 if (sc->sc_pin_wp) {
172 sc->sc_sdhc.sc_vendor_write_protect = imx_sdhc_write_protect;
173 }
174
175 error = clk_enable(sc->sc_clk_per);
176 if (error) {
177 aprint_error(": couldn't enable clock: %d\n", error);
178 return;
179 }
180
181 if (sc->sc_vmmc_supply != NULL) {
182 error = fdtbus_regulator_enable(sc->sc_vmmc_supply);
183 if (error) {
184 aprint_error(": couldn't enable vmmc supply: %d\n", error);
185 return;
186 }
187 }
188
189 aprint_naive("\n");
190 aprint_normal(": SDMMC (%u kHz)\n", sc->sc_sdhc.sc_clkbase);
191
192 if (sc->sc_sdhc.sc_clkbase == 0) {
193 aprint_error_dev(self, "couldn't determine frequency\n");
194 return;
195 }
196
197 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
198 aprint_error_dev(self, "failed to decode interrupt\n");
199 return;
200 }
201
202 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SDMMC,
203 FDT_INTR_MPSAFE, sdhc_intr, &sc->sc_sdhc, device_xname(self));
204 if (sc->sc_ih == NULL) {
205 aprint_error_dev(self, "couldn't establish interrupt on %s\n",
206 intrstr);
207 return;
208 }
209 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
210
211 error = sdhc_host_found(&sc->sc_sdhc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz);
212 if (error) {
213 aprint_error_dev(self, "couldn't initialize host, error = %d\n",
214 error);
215 fdtbus_intr_disestablish(phandle, sc->sc_ih);
216 sc->sc_ih = NULL;
217 return;
218 }
219 }
220
221 static int
imx_sdhc_card_detect(struct sdhc_softc * ssc)222 imx_sdhc_card_detect(struct sdhc_softc *ssc)
223 {
224 struct imx_sdhc_softc *sc = device_private(ssc->sc_dev);
225
226 KASSERT(sc->sc_pin_cd != NULL);
227
228 return fdtbus_gpio_read(sc->sc_pin_cd);
229 }
230
231 static int
imx_sdhc_write_protect(struct sdhc_softc * ssc)232 imx_sdhc_write_protect(struct sdhc_softc *ssc)
233 {
234 struct imx_sdhc_softc *sc = device_private(ssc->sc_dev);
235
236 KASSERT(sc->sc_pin_wp != NULL);
237
238 return fdtbus_gpio_read(sc->sc_pin_wp);
239 }
240
241