1 /* $NetBSD: imx7d_ccm.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _IMX7D_CCM_H 30 #define _IMX7D_CCM_H 31 32 /* 33 * Clocks 34 */ 35 36 #define OSC_24M_CLK 0 37 #define PLL_ARM_MAIN 1 38 #define PLL_ARM_MAIN_CLK 2 39 #define PLL_ARM_MAIN_SRC 3 40 #define PLL_ARM_MAIN_BYPASS 4 41 #define PLL_SYS_MAIN 5 42 #define PLL_SYS_MAIN_CLK 6 43 #define PLL_SYS_MAIN_SRC 7 44 #define PLL_SYS_MAIN_BYPASS 8 45 #define PLL_SYS_MAIN_480M 9 46 #define PLL_SYS_MAIN_240M 10 47 #define PLL_SYS_MAIN_120M 11 48 #define PLL_SYS_MAIN_480M_CLK 12 49 #define PLL_SYS_MAIN_240M_CLK 13 50 #define PLL_SYS_MAIN_120M_CLK 14 51 #define PLL_SYS_PFD0_392M_CLK 15 52 #define PLL_SYS_PFD0_196M 16 53 #define PLL_SYS_PFD0_196M_CLK 17 54 #define PLL_SYS_PFD1_332M_CLK 18 55 #define PLL_SYS_PFD1_166M 19 56 #define PLL_SYS_PFD1_166M_CLK 20 57 #define PLL_SYS_PFD2_270M_CLK 21 58 #define PLL_SYS_PFD2_135M 22 59 #define PLL_SYS_PFD2_135M_CLK 23 60 #define PLL_SYS_PFD3_CLK 24 61 #define PLL_SYS_PFD4_CLK 25 62 #define PLL_SYS_PFD5_CLK 26 63 #define PLL_SYS_PFD6_CLK 27 64 #define PLL_SYS_PFD7_CLK 28 65 #define PLL_ENET_MAIN 29 66 #define PLL_ENET_MAIN_CLK 30 67 #define PLL_ENET_MAIN_SRC 31 68 #define PLL_ENET_MAIN_BYPASS 32 69 #define PLL_ENET_MAIN_500M 33 70 #define PLL_ENET_MAIN_250M 34 71 #define PLL_ENET_MAIN_125M 35 72 #define PLL_ENET_MAIN_100M 36 73 #define PLL_ENET_MAIN_50M 37 74 #define PLL_ENET_MAIN_40M 38 75 #define PLL_ENET_MAIN_25M 39 76 #define PLL_ENET_MAIN_500M_CLK 40 77 #define PLL_ENET_MAIN_250M_CLK 41 78 #define PLL_ENET_MAIN_125M_CLK 42 79 #define PLL_ENET_MAIN_100M_CLK 43 80 #define PLL_ENET_MAIN_50M_CLK 44 81 #define PLL_ENET_MAIN_40M_CLK 45 82 #define PLL_ENET_MAIN_25M_CLK 46 83 #define PLL_DRAM_MAIN 47 84 #define PLL_DRAM_MAIN_CLK 48 85 #define PLL_DRAM_MAIN_SRC 49 86 #define PLL_DRAM_MAIN_BYPASS 50 87 #define PLL_DRAM_MAIN_533M 51 88 #define PLL_DRAM_MAIN_533M_CLK 52 89 #define PLL_AUDIO_MAIN 53 90 #define PLL_AUDIO_MAIN_CLK 54 91 #define PLL_AUDIO_MAIN_SRC 55 92 #define PLL_AUDIO_MAIN_BYPASS 56 93 #define PLL_VIDEO_MAIN_CLK 57 94 #define PLL_VIDEO_MAIN 58 95 #define PLL_VIDEO_MAIN_SRC 59 96 #define PLL_VIDEO_MAIN_BYPASS 60 97 #define USB_MAIN_480M_CLK 61 98 #define ARM_A7_ROOT_CLK 62 99 #define ARM_A7_ROOT_SRC 63 100 #define ARM_A7_ROOT_CG 64 101 #define ARM_A7_ROOT_DIV 65 102 #define ARM_M4_ROOT_CLK 66 103 #define ARM_M4_ROOT_SRC 67 104 #define ARM_M4_ROOT_CG 68 105 #define ARM_M4_ROOT_DIV 69 106 #define ARM_M0_ROOT_CLK 70 107 #define ARM_M0_ROOT_SRC 71 108 #define ARM_M0_ROOT_CG 72 109 #define ARM_M0_ROOT_DIV 73 110 #define MAIN_AXI_ROOT_CLK 74 111 #define MAIN_AXI_ROOT_SRC 75 112 #define MAIN_AXI_ROOT_CG 76 113 #define MAIN_AXI_ROOT_DIV 77 114 #define DISP_AXI_ROOT_CLK 78 115 #define DISP_AXI_ROOT_SRC 79 116 #define DISP_AXI_ROOT_CG 80 117 #define DISP_AXI_ROOT_DIV 81 118 #define ENET_AXI_ROOT_CLK 82 119 #define ENET_AXI_ROOT_SRC 83 120 #define ENET_AXI_ROOT_CG 84 121 #define ENET_AXI_ROOT_DIV 85 122 #define NAND_USDHC_BUS_ROOT_CLK 86 123 #define NAND_USDHC_BUS_ROOT_SRC 87 124 #define NAND_USDHC_BUS_ROOT_CG 88 125 #define NAND_USDHC_BUS_ROOT_DIV 89 126 #define AHB_CHANNEL_ROOT_CLK 90 127 #define AHB_CHANNEL_ROOT_SRC 91 128 #define AHB_CHANNEL_ROOT_CG 92 129 #define AHB_CHANNEL_ROOT_DIV 93 130 #define DRAM_PHYM_ROOT_CLK 94 131 #define DRAM_PHYM_ROOT_SRC 95 132 #define DRAM_PHYM_ROOT_CG 96 133 #define DRAM_PHYM_ROOT_DIV 97 134 #define DRAM_ROOT_CLK 98 135 #define DRAM_ROOT_SRC 99 136 #define DRAM_ROOT_CG 100 137 #define DRAM_ROOT_DIV 101 138 #define DRAM_PHYM_ALT_ROOT_CLK 102 139 #define DRAM_PHYM_ALT_ROOT_SRC 103 140 #define DRAM_PHYM_ALT_ROOT_CG 104 141 #define DRAM_PHYM_ALT_ROOT_DIV 105 142 #define DRAM_ALT_ROOT_CLK 106 143 #define DRAM_ALT_ROOT_SRC 107 144 #define DRAM_ALT_ROOT_CG 108 145 #define DRAM_ALT_ROOT_DIV 109 146 #define USB_HSIC_ROOT_CLK 110 147 #define USB_HSIC_ROOT_SRC 111 148 #define USB_HSIC_ROOT_CG 112 149 #define USB_HSIC_ROOT_DIV 113 150 #define PCIE_CTRL_ROOT_CLK 114 151 #define PCIE_CTRL_ROOT_SRC 115 152 #define PCIE_CTRL_ROOT_CG 116 153 #define PCIE_CTRL_ROOT_DIV 117 154 #define PCIE_PHY_ROOT_CLK 118 155 #define PCIE_PHY_ROOT_SRC 119 156 #define PCIE_PHY_ROOT_CG 120 157 #define PCIE_PHY_ROOT_DIV 121 158 #define EPDC_PIXEL_ROOT_CLK 122 159 #define EPDC_PIXEL_ROOT_SRC 123 160 #define EPDC_PIXEL_ROOT_CG 124 161 #define EPDC_PIXEL_ROOT_DIV 125 162 #define LCDIF_PIXEL_ROOT_CLK 126 163 #define LCDIF_PIXEL_ROOT_SRC 127 164 #define LCDIF_PIXEL_ROOT_CG 128 165 #define LCDIF_PIXEL_ROOT_DIV 129 166 #define MIPI_DSI_ROOT_CLK 130 167 #define MIPI_DSI_ROOT_SRC 131 168 #define MIPI_DSI_ROOT_CG 132 169 #define MIPI_DSI_ROOT_DIV 133 170 #define MIPI_CSI_ROOT_CLK 134 171 #define MIPI_CSI_ROOT_SRC 135 172 #define MIPI_CSI_ROOT_CG 136 173 #define MIPI_CSI_ROOT_DIV 137 174 #define MIPI_DPHY_ROOT_CLK 138 175 #define MIPI_DPHY_ROOT_SRC 139 176 #define MIPI_DPHY_ROOT_CG 140 177 #define MIPI_DPHY_ROOT_DIV 141 178 #define SAI1_ROOT_CLK 142 179 #define SAI1_ROOT_SRC 143 180 #define SAI1_ROOT_CG 144 181 #define SAI1_ROOT_DIV 145 182 #define SAI2_ROOT_CLK 146 183 #define SAI2_ROOT_SRC 147 184 #define SAI2_ROOT_CG 148 185 #define SAI2_ROOT_DIV 149 186 #define SAI3_ROOT_CLK 150 187 #define SAI3_ROOT_SRC 151 188 #define SAI3_ROOT_CG 152 189 #define SAI3_ROOT_DIV 153 190 #define SPDIF_ROOT_CLK 154 191 #define SPDIF_ROOT_SRC 155 192 #define SPDIF_ROOT_CG 156 193 #define SPDIF_ROOT_DIV 157 194 #define ENET1_IPG_ROOT_CLK 158 195 #define ENET1_REF_ROOT_SRC 159 196 #define ENET1_REF_ROOT_CG 160 197 #define ENET1_REF_ROOT_DIV 161 198 #define ENET1_TIME_ROOT_CLK 162 199 #define ENET1_TIME_ROOT_SRC 163 200 #define ENET1_TIME_ROOT_CG 164 201 #define ENET1_TIME_ROOT_DIV 165 202 #define ENET2_IPG_ROOT_CLK 166 203 #define ENET2_REF_ROOT_SRC 167 204 #define ENET2_REF_ROOT_CG 168 205 #define ENET2_REF_ROOT_DIV 169 206 #define ENET2_TIME_ROOT_CLK 170 207 #define ENET2_TIME_ROOT_SRC 171 208 #define ENET2_TIME_ROOT_CG 172 209 #define ENET2_TIME_ROOT_DIV 173 210 #define ENET_PHY_REF_ROOT_CLK 174 211 #define ENET_PHY_REF_ROOT_SRC 175 212 #define ENET_PHY_REF_ROOT_CG 176 213 #define ENET_PHY_REF_ROOT_DIV 177 214 #define EIM_ROOT_CLK 178 215 #define EIM_ROOT_SRC 179 216 #define EIM_ROOT_CG 180 217 #define EIM_ROOT_DIV 181 218 #define NAND_ROOT_CLK 182 219 #define NAND_ROOT_SRC 183 220 #define NAND_ROOT_CG 184 221 #define NAND_ROOT_DIV 185 222 #define QSPI_ROOT_CLK 186 223 #define QSPI_ROOT_SRC 187 224 #define QSPI_ROOT_CG 188 225 #define QSPI_ROOT_DIV 189 226 #define USDHC1_ROOT_CLK 190 227 #define USDHC1_ROOT_SRC 191 228 #define USDHC1_ROOT_CG 192 229 #define USDHC1_ROOT_DIV 193 230 #define USDHC2_ROOT_CLK 194 231 #define USDHC2_ROOT_SRC 195 232 #define USDHC2_ROOT_CG 196 233 #define USDHC2_ROOT_DIV 197 234 #define USDHC3_ROOT_CLK 198 235 #define USDHC3_ROOT_SRC 199 236 #define USDHC3_ROOT_CG 200 237 #define USDHC3_ROOT_DIV 201 238 #define CAN1_ROOT_CLK 202 239 #define CAN1_ROOT_SRC 203 240 #define CAN1_ROOT_CG 204 241 #define CAN1_ROOT_DIV 205 242 #define CAN2_ROOT_CLK 206 243 #define CAN2_ROOT_SRC 207 244 #define CAN2_ROOT_CG 208 245 #define CAN2_ROOT_DIV 209 246 #define I2C1_ROOT_CLK 210 247 #define I2C1_ROOT_SRC 211 248 #define I2C1_ROOT_CG 212 249 #define I2C1_ROOT_DIV 213 250 #define I2C2_ROOT_CLK 214 251 #define I2C2_ROOT_SRC 215 252 #define I2C2_ROOT_CG 216 253 #define I2C2_ROOT_DIV 217 254 #define I2C3_ROOT_CLK 218 255 #define I2C3_ROOT_SRC 219 256 #define I2C3_ROOT_CG 220 257 #define I2C3_ROOT_DIV 221 258 #define I2C4_ROOT_CLK 222 259 #define I2C4_ROOT_SRC 223 260 #define I2C4_ROOT_CG 224 261 #define I2C4_ROOT_DIV 225 262 #define UART1_ROOT_CLK 226 263 #define UART1_ROOT_SRC 227 264 #define UART1_ROOT_CG 228 265 #define UART1_ROOT_DIV 229 266 #define UART2_ROOT_CLK 230 267 #define UART2_ROOT_SRC 231 268 #define UART2_ROOT_CG 232 269 #define UART2_ROOT_DIV 233 270 #define UART3_ROOT_CLK 234 271 #define UART3_ROOT_SRC 235 272 #define UART3_ROOT_CG 236 273 #define UART3_ROOT_DIV 237 274 #define UART4_ROOT_CLK 238 275 #define UART4_ROOT_SRC 239 276 #define UART4_ROOT_CG 240 277 #define UART4_ROOT_DIV 241 278 #define UART5_ROOT_CLK 242 279 #define UART5_ROOT_SRC 243 280 #define UART5_ROOT_CG 244 281 #define UART5_ROOT_DIV 245 282 #define UART6_ROOT_CLK 246 283 #define UART6_ROOT_SRC 247 284 #define UART6_ROOT_CG 248 285 #define UART6_ROOT_DIV 249 286 #define UART7_ROOT_CLK 250 287 #define UART7_ROOT_SRC 251 288 #define UART7_ROOT_CG 252 289 #define UART7_ROOT_DIV 253 290 #define ECSPI1_ROOT_CLK 254 291 #define ECSPI1_ROOT_SRC 255 292 #define ECSPI1_ROOT_CG 256 293 #define ECSPI1_ROOT_DIV 257 294 #define ECSPI2_ROOT_CLK 258 295 #define ECSPI2_ROOT_SRC 259 296 #define ECSPI2_ROOT_CG 260 297 #define ECSPI2_ROOT_DIV 261 298 #define ECSPI3_ROOT_CLK 262 299 #define ECSPI3_ROOT_SRC 263 300 #define ECSPI3_ROOT_CG 264 301 #define ECSPI3_ROOT_DIV 265 302 #define ECSPI4_ROOT_CLK 266 303 #define ECSPI4_ROOT_SRC 267 304 #define ECSPI4_ROOT_CG 268 305 #define ECSPI4_ROOT_DIV 269 306 #define PWM1_ROOT_CLK 270 307 #define PWM1_ROOT_SRC 271 308 #define PWM1_ROOT_CG 272 309 #define PWM1_ROOT_DIV 273 310 #define PWM2_ROOT_CLK 274 311 #define PWM2_ROOT_SRC 275 312 #define PWM2_ROOT_CG 276 313 #define PWM2_ROOT_DIV 277 314 #define PWM3_ROOT_CLK 278 315 #define PWM3_ROOT_SRC 279 316 #define PWM3_ROOT_CG 280 317 #define PWM3_ROOT_DIV 281 318 #define PWM4_ROOT_CLK 282 319 #define PWM4_ROOT_SRC 283 320 #define PWM4_ROOT_CG 284 321 #define PWM4_ROOT_DIV 285 322 #define FLEXTIMER1_ROOT_CLK 286 323 #define FLEXTIMER1_ROOT_SRC 287 324 #define FLEXTIMER1_ROOT_CG 288 325 #define FLEXTIMER1_ROOT_DIV 289 326 #define FLEXTIMER2_ROOT_CLK 290 327 #define FLEXTIMER2_ROOT_SRC 291 328 #define FLEXTIMER2_ROOT_CG 292 329 #define FLEXTIMER2_ROOT_DIV 293 330 #define SIM1_ROOT_CLK 294 331 #define SIM1_ROOT_SRC 295 332 #define SIM1_ROOT_CG 296 333 #define SIM1_ROOT_DIV 297 334 #define SIM2_ROOT_CLK 298 335 #define SIM2_ROOT_SRC 299 336 #define SIM2_ROOT_CG 300 337 #define SIM2_ROOT_DIV 301 338 #define GPT1_ROOT_CLK 302 339 #define GPT1_ROOT_SRC 303 340 #define GPT1_ROOT_CG 304 341 #define GPT1_ROOT_DIV 305 342 #define GPT2_ROOT_CLK 306 343 #define GPT2_ROOT_SRC 307 344 #define GPT2_ROOT_CG 308 345 #define GPT2_ROOT_DIV 309 346 #define GPT3_ROOT_CLK 310 347 #define GPT3_ROOT_SRC 311 348 #define GPT3_ROOT_CG 312 349 #define GPT3_ROOT_DIV 313 350 #define GPT4_ROOT_CLK 314 351 #define GPT4_ROOT_SRC 315 352 #define GPT4_ROOT_CG 316 353 #define GPT4_ROOT_DIV 317 354 #define TRACE_ROOT_CLK 318 355 #define TRACE_ROOT_SRC 319 356 #define TRACE_ROOT_CG 320 357 #define TRACE_ROOT_DIV 321 358 #define WDOG1_ROOT_CLK 322 359 #define WDOG_ROOT_SRC 323 360 #define WDOG_ROOT_CG 324 361 #define WDOG_ROOT_DIV 325 362 #define CSI_MCLK_ROOT_CLK 326 363 #define CSI_MCLK_ROOT_SRC 327 364 #define CSI_MCLK_ROOT_CG 328 365 #define CSI_MCLK_ROOT_DIV 329 366 #define AUDIO_MCLK_ROOT_CLK 330 367 #define AUDIO_MCLK_ROOT_SRC 331 368 #define AUDIO_MCLK_ROOT_CG 332 369 #define AUDIO_MCLK_ROOT_DIV 333 370 #define WRCLK_ROOT_CLK 334 371 #define WRCLK_ROOT_SRC 335 372 #define WRCLK_ROOT_CG 336 373 #define WRCLK_ROOT_DIV 337 374 #define CLKO1_ROOT_SRC 338 375 #define CLKO1_ROOT_CG 339 376 #define CLKO1_ROOT_DIV 340 377 #define CLKO2_ROOT_SRC 341 378 #define CLKO2_ROOT_CG 342 379 #define CLKO2_ROOT_DIV 343 380 #define MAIN_AXI_ROOT_PRE_DIV 344 381 #define DISP_AXI_ROOT_PRE_DIV 345 382 #define ENET_AXI_ROOT_PRE_DIV 346 383 #define NAND_USDHC_BUS_ROOT_PRE_DIV 347 384 #define AHB_CHANNEL_ROOT_PRE_DIV 348 385 #define USB_HSIC_ROOT_PRE_DIV 349 386 #define PCIE_CTRL_ROOT_PRE_DIV 350 387 #define PCIE_PHY_ROOT_PRE_DIV 351 388 #define EPDC_PIXEL_ROOT_PRE_DIV 352 389 #define LCDIF_PIXEL_ROOT_PRE_DIV 353 390 #define MIPI_DSI_ROOT_PRE_DIV 354 391 #define MIPI_CSI_ROOT_PRE_DIV 355 392 #define MIPI_DPHY_ROOT_PRE_DIV 356 393 #define SAI1_ROOT_PRE_DIV 357 394 #define SAI2_ROOT_PRE_DIV 358 395 #define SAI3_ROOT_PRE_DIV 359 396 #define SPDIF_ROOT_PRE_DIV 360 397 #define ENET1_REF_ROOT_PRE_DIV 361 398 #define ENET1_TIME_ROOT_PRE_DIV 362 399 #define ENET2_REF_ROOT_PRE_DIV 363 400 #define ENET2_TIME_ROOT_PRE_DIV 364 401 #define ENET_PHY_REF_ROOT_PRE_DIV 365 402 #define EIM_ROOT_PRE_DIV 366 403 #define NAND_ROOT_PRE_DIV 367 404 #define QSPI_ROOT_PRE_DIV 368 405 #define USDHC1_ROOT_PRE_DIV 369 406 #define USDHC2_ROOT_PRE_DIV 370 407 #define USDHC3_ROOT_PRE_DIV 371 408 #define CAN1_ROOT_PRE_DIV 372 409 #define CAN2_ROOT_PRE_DIV 373 410 #define I2C1_ROOT_PRE_DIV 374 411 #define I2C2_ROOT_PRE_DIV 375 412 #define I2C3_ROOT_PRE_DIV 376 413 #define I2C4_ROOT_PRE_DIV 377 414 #define UART1_ROOT_PRE_DIV 378 415 #define UART2_ROOT_PRE_DIV 379 416 #define UART3_ROOT_PRE_DIV 380 417 #define UART4_ROOT_PRE_DIV 381 418 #define UART5_ROOT_PRE_DIV 382 419 #define UART6_ROOT_PRE_DIV 383 420 #define UART7_ROOT_PRE_DIV 384 421 #define ECSPI1_ROOT_PRE_DIV 385 422 #define ECSPI2_ROOT_PRE_DIV 386 423 #define ECSPI3_ROOT_PRE_DIV 387 424 #define ECSPI4_ROOT_PRE_DIV 388 425 #define PWM1_ROOT_PRE_DIV 389 426 #define PWM2_ROOT_PRE_DIV 390 427 #define PWM3_ROOT_PRE_DIV 391 428 #define PWM4_ROOT_PRE_DIV 392 429 #define FLEXTIMER1_ROOT_PRE_DIV 393 430 #define FLEXTIMER2_ROOT_PRE_DIV 394 431 #define SIM1_ROOT_PRE_DIV 395 432 #define SIM2_ROOT_PRE_DIV 396 433 #define GPT1_ROOT_PRE_DIV 397 434 #define GPT2_ROOT_PRE_DIV 398 435 #define GPT3_ROOT_PRE_DIV 399 436 #define GPT4_ROOT_PRE_DIV 400 437 #define TRACE_ROOT_PRE_DIV 401 438 #define WDOG_ROOT_PRE_DIV 402 439 #define CSI_MCLK_ROOT_PRE_DIV 403 440 #define AUDIO_MCLK_ROOT_PRE_DIV 404 441 #define WRCLK_ROOT_PRE_DIV 405 442 #define CLKO1_ROOT_PRE_DIV 406 443 #define CLKO2_ROOT_PRE_DIV 407 444 #define DRAM_PHYM_ALT_ROOT_PRE_DIV 408 445 #define DRAM_ALT_ROOT_PRE_DIV 409 446 #define LVDS1_IN_CLK 410 447 #define LVDS1_OUT_SEL 411 448 #define LVDS1_OUT_CLK 412 449 #define CLK_DUMMY 413 450 #define GPT_3M_CLK 414 451 #define OCRAM_CLK 415 452 #define OCRAM_S_CLK 416 453 #define WDOG2_ROOT_CLK 417 454 #define WDOG3_ROOT_CLK 418 455 #define WDOG4_ROOT_CLK 419 456 #define SDMA_CORE_CLK 420 457 #define USB1_MAIN_480M_CLK 421 458 #define USB_CTRL_CLK 422 459 #define USB_PHY1_CLK 423 460 #define USB_PHY2_CLK 424 461 #define IPG_ROOT_CLK 425 462 #define SAI1_IPG_CLK 426 463 #define SAI2_IPG_CLK 427 464 #define SAI3_IPG_CLK 428 465 #define PLL_AUDIO_TEST_DIV 429 466 #define PLL_AUDIO_POST_DIV 430 467 #define PLL_VIDEO_TEST_DIV 431 468 #define PLL_VIDEO_POST_DIV 432 469 #define MU_ROOT_CLK 433 470 #define SEMA4_HS_ROOT_CLK 434 471 #define PLL_DRAM_TEST_DIV 435 472 #define ADC_ROOT_CLK 436 473 #define CLK_ARM 437 474 #define CKIL 438 475 #define OCOTP_CLK 439 476 #define NAND_RAWNAND_CLK 440 477 #define NAND_USDHC_BUS_RAWNAND_CLK 441 478 #define SNVS_CLK 442 479 #define CAAM_CLK 443 480 #define KPP_ROOT_CLK 444 481 482 #endif /* !_IMX7D_CCM_H */ 483