1 /* $NetBSD: imx7_gpc.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $ */
2 /*-
3 * Copyright (c) 2019 Genetec Corporation. All rights reserved.
4 * Written by Hashimoto Kenichi for Genetec Corporation.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: imx7_gpc.c,v 1.3 2021/01/27 03:10:20 thorpej Exp $");
29
30 #include "opt_fdt.h"
31
32 #define _INTR_PRIVATE
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37
38 #include <arm/nxp/imx6var.h>
39 #include <arm/nxp/imx6_reg.h>
40 #include <arm/nxp/imx6_gpcreg.h>
41
42 #include <arm/cortex/gic_intr.h>
43
44 #include <dev/fdt/fdtvar.h>
45
46 #define GPC_PCG_CPU_0_1_MAPPING 0xec
47 #define OTG2_A53_DOMAIN __BIT(5)
48 #define OTG1_A53_DOMAIN __BIT(4)
49
50 #define GPC_PU_PGC_SW_PUP_REQ 0xf8
51 #define USB_OTG2_SW_PUP_REQ __BIT(3)
52 #define USB_OTG1_SW_PUP_REQ __BIT(2)
53
54 #define IMXGPC_MAXCPUS 4
55
56 /* Mapping of CPU number to GPC_IMR1_COREx base offset */
57 static const bus_size_t imx7gpc_imr_base[IMXGPC_MAXCPUS] = {
58 0x30,
59 0x40,
60 0x1c0,
61 0x1d0,
62 };
63
64 #define GPC_IMRn_COREx(n,x) (imx7gpc_imr_base[(x)] + (n) * 0x4)
65
66 struct imx7gpc_softc {
67 device_t sc_dev;
68
69 bus_space_tag_t sc_iot;
70 bus_space_handle_t sc_ioh;
71 };
72
73 static int imx7gpc_match(device_t, struct cfdata *, void *);
74 static void imx7gpc_attach(device_t, device_t, void *);
75
76 static void imx7gpc_powerup(struct imx7gpc_softc *, uint32_t, uint32_t);
77 static void imx7gpc_mask(struct imx7gpc_softc *, u_int, bool);
78 static void imx7gpc_unmask(struct imx7gpc_softc *, u_int, bool);
79
80 static void *imx7gpc_establish(device_t, u_int *, int, int,
81 int (*)(void *), void *, const char *);
82 static void imx7gpc_disestablish(device_t, void *);
83 static bool imx7gpc_intrstr(device_t, u_int *, char *, size_t);
84
85 struct fdtbus_interrupt_controller_func imx7gpc_funcs = {
86 .establish = imx7gpc_establish,
87 .disestablish = imx7gpc_disestablish,
88 .intrstr = imx7gpc_intrstr
89 };
90
91 CFATTACH_DECL_NEW(imx7gpc, sizeof(struct imx7gpc_softc),
92 imx7gpc_match, imx7gpc_attach, NULL, NULL);
93
94 static const struct device_compatible_entry compat_data[] = {
95 { .compat = "fsl,imx7d-gpc" },
96 { .compat = "fsl,imx8mq-gpc" },
97 DEVICE_COMPAT_EOL
98 };
99
100 static int
imx7gpc_match(device_t parent,cfdata_t cf,void * aux)101 imx7gpc_match(device_t parent, cfdata_t cf, void *aux)
102 {
103 struct fdt_attach_args * const faa = aux;
104
105 return of_compatible_match(faa->faa_phandle, compat_data);
106 }
107
108 static void
imx7gpc_attach(device_t parent,device_t self,void * aux)109 imx7gpc_attach(device_t parent, device_t self, void *aux)
110 {
111 struct imx7gpc_softc * const sc = device_private(self);
112 struct fdt_attach_args * const faa = aux;
113 const int phandle = faa->faa_phandle;
114 bus_addr_t gpc_addr;
115 bus_size_t gpc_size;
116 int error;
117
118 KASSERT(ncpu <= IMXGPC_MAXCPUS);
119
120 if (fdtbus_get_reg(phandle, 0, &gpc_addr, &gpc_size) != 0) {
121 aprint_error(": couldn't get gpc registers\n");
122 return;
123 }
124
125 sc->sc_dev = self;
126 sc->sc_iot = faa->faa_bst;
127
128 error = bus_space_map(sc->sc_iot, gpc_addr, gpc_size, 0,
129 &sc->sc_ioh);
130 if (error) {
131 aprint_error(": couldn't map gpc registers: %d\n", error);
132 return;
133 }
134
135 error = fdtbus_register_interrupt_controller(self, faa->faa_phandle,
136 &imx7gpc_funcs);
137 if (error) {
138 aprint_error(": couldn't register with fdtbus: %d\n", error);
139 return;
140 }
141
142 aprint_naive("\n");
143 aprint_normal(": General Power Controller\n");
144
145 /* XXX enable OTG power domains */
146 imx7gpc_powerup(sc, USB_OTG2_SW_PUP_REQ | USB_OTG1_SW_PUP_REQ,
147 OTG2_A53_DOMAIN | OTG1_A53_DOMAIN);
148 }
149
150 static void
imx7gpc_powerup(struct imx7gpc_softc * sc,uint32_t req,uint32_t map)151 imx7gpc_powerup(struct imx7gpc_softc *sc, uint32_t req, uint32_t map)
152 {
153 uint32_t val;
154
155 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPC_PCG_CPU_0_1_MAPPING);
156 val |= map;
157 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPC_PCG_CPU_0_1_MAPPING, val);
158
159 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPC_PU_PGC_SW_PUP_REQ);
160 val |= req;
161 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPC_PU_PGC_SW_PUP_REQ, val);
162
163 delay(5000);
164
165 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPC_PCG_CPU_0_1_MAPPING);
166 val &= ~map;
167 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPC_PCG_CPU_0_1_MAPPING, val);
168 }
169
170 static void
imx7gpc_mask(struct imx7gpc_softc * sc,u_int irq,bool mpsafe)171 imx7gpc_mask(struct imx7gpc_softc *sc, u_int irq, bool mpsafe)
172 {
173 const u_int reg = irq / 32;
174 const u_int bit = irq % 32;
175 uint32_t val;
176
177 for (u_int cpu = 0; cpu < (mpsafe ? ncpu : 1); cpu++) {
178 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
179 GPC_IMRn_COREx(reg, cpu));
180 val |= __BIT(bit);
181 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
182 GPC_IMRn_COREx(reg, cpu), val);
183 }
184 }
185
186 static void
imx7gpc_unmask(struct imx7gpc_softc * sc,u_int irq,bool mpsafe)187 imx7gpc_unmask(struct imx7gpc_softc *sc, u_int irq, bool mpsafe)
188 {
189 const u_int reg = irq / 32;
190 const u_int bit = irq % 32;
191 uint32_t val;
192
193 for (u_int cpu = 0; cpu < (mpsafe ? ncpu : 1); cpu++) {
194 val = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
195 GPC_IMRn_COREx(reg, cpu));
196 val &= ~__BIT(bit);
197 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
198 GPC_IMRn_COREx(reg, cpu), val);
199 }
200 }
201
202
203 static void *
imx7gpc_establish(device_t dev,u_int * specifier,int ipl,int flags,int (* func)(void *),void * arg,const char * xname)204 imx7gpc_establish(device_t dev, u_int *specifier, int ipl, int flags,
205 int (*func)(void *), void *arg, const char *xname)
206 {
207 struct imx7gpc_softc * const sc = device_private(dev);
208 void *ih;
209
210 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
211 /* 2nd cell is the interrupt number */
212 /* 3rd cell is flags */
213
214 const u_int type = be32toh(specifier[0]);
215 const u_int intr = be32toh(specifier[1]);
216 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
217 const u_int trig = be32toh(specifier[2]) & 0xf;
218 const u_int level = (trig & 0x3) ? IST_EDGE : IST_LEVEL;
219
220 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0;
221
222 if (type != 0)
223 return NULL; /* Only SPIs are supported */
224
225 KASSERT(irq >= 32);
226
227 aprint_debug_dev(dev, "intr establish irq %d, level %d\n", irq, level);
228
229 ih = intr_establish_xname(irq, ipl, level | mpsafe, func, arg, xname);
230 if (ih != NULL)
231 imx7gpc_unmask(sc, irq - 32, mpsafe == IST_MPSAFE);
232
233 return ih;
234 }
235
236 static void
imx7gpc_disestablish(device_t dev,void * ih)237 imx7gpc_disestablish(device_t dev, void *ih)
238 {
239 struct imx7gpc_softc * const sc = device_private(dev);
240 struct intrsource *is = ih;
241 const u_int irq = is->is_irq;
242 const bool mpsafe = is->is_mpsafe;
243
244 intr_disestablish(ih);
245 imx7gpc_mask(sc, irq - 32, mpsafe);
246 }
247
248 static bool
imx7gpc_intrstr(device_t dev,u_int * specifier,char * buf,size_t buflen)249 imx7gpc_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
250 {
251 /* 1st cell is the interrupt type; 0 is SPI, 1 is PPI */
252 /* 2nd cell is the interrupt number */
253 /* 3rd cell is flags */
254
255 if (!specifier)
256 return false;
257
258 const u_int type = be32toh(specifier[0]);
259 const u_int intr = be32toh(specifier[1]);
260 const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
261
262 snprintf(buf, buflen, "irq %d", irq);
263
264 return true;
265 }
266